From 6c27c712333a34729190137a0058cd19f79b7d90 Mon Sep 17 00:00:00 2001 From: Maarten ter Huurne Date: Thu, 29 Mar 2012 19:17:01 +0200 Subject: [PATCH] --- yaml --- r: 319637 b: refs/heads/master c: 1471d41a5bdfdf83ed1e5c2148a9763e64b1f53b h: refs/heads/master i: 319635: 3e41b6cdbb17655c0f0936b8d6bd482e6caf2eae v: v3 --- [refs] | 2 +- .../bindings/ata/cavium-compact-flash.txt | 30 - .../bindings/gpio/cavium-octeon-gpio.txt | 49 -- .../devicetree/bindings/i2c/cavium-i2c.txt | 34 - .../bindings/mips/cavium/bootbus.txt | 126 ---- .../devicetree/bindings/mips/cavium/ciu.txt | 26 - .../devicetree/bindings/mips/cavium/ciu2.txt | 27 - .../bindings/mips/cavium/dma-engine.txt | 21 - .../devicetree/bindings/mips/cavium/uctl.txt | 46 -- .../devicetree/bindings/net/cavium-mdio.txt | 27 - .../devicetree/bindings/net/cavium-mix.txt | 39 - .../devicetree/bindings/net/cavium-pip.txt | 98 --- .../bindings/serial/cavium-uart.txt | 19 - trunk/arch/mips/Kconfig | 2 - trunk/arch/mips/cavium-octeon/.gitignore | 2 - trunk/arch/mips/cavium-octeon/Makefile | 16 - .../mips/cavium-octeon/executive/cvmx-fpa.c | 183 +++++ .../cavium-octeon/executive/cvmx-helper-fpa.c | 243 ++++++ trunk/arch/mips/cavium-octeon/octeon-irq.c | 399 +++------- .../arch/mips/cavium-octeon/octeon-platform.c | 699 +++++------------- trunk/arch/mips/cavium-octeon/octeon_3xxx.dts | 571 -------------- trunk/arch/mips/cavium-octeon/octeon_68xx.dts | 625 ---------------- trunk/arch/mips/cavium-octeon/serial.c | 134 ++-- trunk/arch/mips/cavium-octeon/setup.c | 45 -- .../mips/include/asm/mach-cavium-octeon/irq.h | 45 +- .../include/asm/mach-jz4740/jz4740_nand.h | 4 + .../mips/include/asm/octeon/cvmx-helper-fpa.h | 64 ++ .../mips/include/asm/octeon/cvmx-helper.h | 2 + trunk/arch/mips/include/asm/octeon/octeon.h | 5 + trunk/arch/mips/include/asm/prom.h | 3 + trunk/arch/mips/jz4740/platform.c | 20 +- trunk/arch/mips/kernel/prom.c | 29 + trunk/arch/mips/netlogic/xlp/Makefile | 1 - trunk/arch/mips/netlogic/xlp/of.c | 34 - trunk/drivers/i2c/busses/i2c-octeon.c | 92 ++- trunk/drivers/mtd/nand/jz4740_nand.c | 228 +++++- .../drivers/net/ethernet/octeon/octeon_mgmt.c | 312 +++----- trunk/drivers/net/phy/mdio-octeon.c | 92 +-- trunk/drivers/staging/octeon/ethernet-mdio.c | 28 +- trunk/drivers/staging/octeon/ethernet.c | 153 ++-- .../drivers/staging/octeon/octeon-ethernet.h | 3 - trunk/include/linux/libfdt.h | 8 - trunk/include/linux/libfdt_env.h | 13 - trunk/lib/Kconfig | 6 - trunk/lib/Makefile | 5 - trunk/lib/fdt.c | 2 - trunk/lib/fdt_ro.c | 2 - trunk/lib/fdt_rw.c | 2 - trunk/lib/fdt_strerror.c | 2 - trunk/lib/fdt_sw.c | 2 - trunk/lib/fdt_wip.c | 2 - 51 files changed, 1377 insertions(+), 3245 deletions(-) delete mode 100644 trunk/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt delete mode 100644 trunk/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt delete mode 100644 trunk/Documentation/devicetree/bindings/i2c/cavium-i2c.txt delete mode 100644 trunk/Documentation/devicetree/bindings/mips/cavium/bootbus.txt delete mode 100644 trunk/Documentation/devicetree/bindings/mips/cavium/ciu.txt delete mode 100644 trunk/Documentation/devicetree/bindings/mips/cavium/ciu2.txt delete mode 100644 trunk/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt delete mode 100644 trunk/Documentation/devicetree/bindings/mips/cavium/uctl.txt delete mode 100644 trunk/Documentation/devicetree/bindings/net/cavium-mdio.txt delete mode 100644 trunk/Documentation/devicetree/bindings/net/cavium-mix.txt delete mode 100644 trunk/Documentation/devicetree/bindings/net/cavium-pip.txt delete mode 100644 trunk/Documentation/devicetree/bindings/serial/cavium-uart.txt delete mode 100644 trunk/arch/mips/cavium-octeon/.gitignore create mode 100644 trunk/arch/mips/cavium-octeon/executive/cvmx-fpa.c create mode 100644 trunk/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c delete mode 100644 trunk/arch/mips/cavium-octeon/octeon_3xxx.dts delete mode 100644 trunk/arch/mips/cavium-octeon/octeon_68xx.dts create mode 100644 trunk/arch/mips/include/asm/octeon/cvmx-helper-fpa.h delete mode 100644 trunk/arch/mips/netlogic/xlp/of.c delete mode 100644 trunk/include/linux/libfdt.h delete mode 100644 trunk/include/linux/libfdt_env.h delete mode 100644 trunk/lib/fdt.c delete mode 100644 trunk/lib/fdt_ro.c delete mode 100644 trunk/lib/fdt_rw.c delete mode 100644 trunk/lib/fdt_strerror.c delete mode 100644 trunk/lib/fdt_sw.c delete mode 100644 trunk/lib/fdt_wip.c diff --git a/[refs] b/[refs] index 0b1c04d53fc3..fd3c64abe84a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b59b284101454823c77c9635f3ee8cd4f979fe6e +refs/heads/master: 1471d41a5bdfdf83ed1e5c2148a9763e64b1f53b diff --git a/trunk/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt b/trunk/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt deleted file mode 100644 index 93986a5a8018..000000000000 --- a/trunk/Documentation/devicetree/bindings/ata/cavium-compact-flash.txt +++ /dev/null @@ -1,30 +0,0 @@ -* Compact Flash - -The Cavium Compact Flash device is connected to the Octeon Boot Bus, -and is thus a child of the Boot Bus device. It can read and write -industry standard compact flash devices. - -Properties: -- compatible: "cavium,ebt3000-compact-flash"; - - Compatibility with many Cavium evaluation boards. - -- reg: The base address of the the CF chip select banks. Depending on - the device configuration, there may be one or two banks. - -- cavium,bus-width: The width of the connection to the CF devices. Valid - values are 8 and 16. - -- cavium,true-ide: Optional, if present the CF connection is in True IDE mode. - -- cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected - to this device. - -Example: - compact-flash@5,0 { - compatible = "cavium,ebt3000-compact-flash"; - reg = <5 0 0x10000>, <6 0 0x10000>; - cavium,bus-width = <16>; - cavium,true-ide; - cavium,dma-engine-handle = <&dma0>; - }; diff --git a/trunk/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt b/trunk/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt deleted file mode 100644 index 9d6dcd3fe7f9..000000000000 --- a/trunk/Documentation/devicetree/bindings/gpio/cavium-octeon-gpio.txt +++ /dev/null @@ -1,49 +0,0 @@ -* General Purpose Input Output (GPIO) bus. - -Properties: -- compatible: "cavium,octeon-3860-gpio" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the GPIO unit's register bank. - -- gpio-controller: This is a GPIO controller. - -- #gpio-cells: Must be <2>. The first cell is the GPIO pin. - -- interrupt-controller: The GPIO controller is also an interrupt - controller, many of its pins may be configured as an interrupt - source. - -- #interrupt-cells: Must be <2>. The first cell is the GPIO pin - connected to the interrupt source. The second cell is the interrupt - triggering protocol and may have one of four values: - 1 - edge triggered on the rising edge. - 2 - edge triggered on the falling edge - 4 - level triggered active high. - 8 - level triggered active low. - -- interrupts: Interrupt routing for each pin. - -Example: - - gpio-controller@1070000000800 { - #gpio-cells = <2>; - compatible = "cavium,octeon-3860-gpio"; - reg = <0x10700 0x00000800 0x0 0x100>; - gpio-controller; - /* Interrupts are specified by two parts: - * 1) GPIO pin number (0..15) - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - interrupt-controller; - #interrupt-cells = <2>; - /* The GPIO pin connect to 16 consecutive CUI bits */ - interrupts = <0 16>, <0 17>, <0 18>, <0 19>, - <0 20>, <0 21>, <0 22>, <0 23>, - <0 24>, <0 25>, <0 26>, <0 27>, - <0 28>, <0 29>, <0 30>, <0 31>; - }; diff --git a/trunk/Documentation/devicetree/bindings/i2c/cavium-i2c.txt b/trunk/Documentation/devicetree/bindings/i2c/cavium-i2c.txt deleted file mode 100644 index dced82ebe31d..000000000000 --- a/trunk/Documentation/devicetree/bindings/i2c/cavium-i2c.txt +++ /dev/null @@ -1,34 +0,0 @@ -* Two Wire Serial Interface (TWSI) / I2C - -- compatible: "cavium,octeon-3860-twsi" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the TWSI/I2C bus controller register bank. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. I2C addresses have no size component. - -- interrupts: A single interrupt specifier. - -- clock-frequency: The I2C bus clock rate in Hz. - -Example: - twsi0: i2c@1180000001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001000 0x0 0x200>; - interrupts = <0 45>; - clock-frequency = <100000>; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; - tmp@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - }; diff --git a/trunk/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/trunk/Documentation/devicetree/bindings/mips/cavium/bootbus.txt deleted file mode 100644 index 6581478225a2..000000000000 --- a/trunk/Documentation/devicetree/bindings/mips/cavium/bootbus.txt +++ /dev/null @@ -1,126 +0,0 @@ -* Boot Bus - -The Octeon Boot Bus is a configurable parallel bus with 8 chip -selects. Each chip select is independently configurable. - -Properties: -- compatible: "cavium,octeon-3860-bootbus" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the Boot Bus' register bank. - -- #address-cells: Must be <2>. The first cell is the chip select - within the bootbus. The second cell is the offset from the chip select. - -- #size-cells: Must be <1>. - -- ranges: There must be one one triplet of (child-bus-address, - parent-bus-address, length) for each active chip select. If the - length element for any triplet is zero, the chip select is disabled, - making it inactive. - -The configuration parameters for each chip select are stored in child -nodes. - -Configuration Properties: -- compatible: "cavium,octeon-3860-bootbus-config" - -- cavium,cs-index: A single cell indicating the chip select that - corresponds to this configuration. - -- cavium,t-adr: A cell specifying the ADR timing (in nS). - -- cavium,t-ce: A cell specifying the CE timing (in nS). - -- cavium,t-oe: A cell specifying the OE timing (in nS). - -- cavium,t-we: A cell specifying the WE timing (in nS). - -- cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS). - -- cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS). - -- cavium,t-pause: A cell specifying the PAUSE timing (in nS). - -- cavium,t-wait: A cell specifying the WAIT timing (in nS). - -- cavium,t-page: A cell specifying the PAGE timing (in nS). - -- cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS). - -- cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1 - = 2 bytes, 2 = 4 bytes, 3 = 8 bytes). - -- cavium,wait-mode: Optional. If present, wait mode (WAITM) is selected. - -- cavium,page-mode: Optional. If present, page mode (PAGEM) is selected. - -- cavium,bus-width: A cell specifying the WIDTH parameter (in bits) of - the bus for this chip select. - -- cavium,ale-mode: Optional. If present, ALE mode is selected. - -- cavium,sam-mode: Optional. If present, SAM mode is selected. - -- cavium,or-mode: Optional. If present, OR mode is selected. - -Example: - bootbus: bootbus@1180000000000 { - compatible = "cavium,octeon-3860-bootbus"; - reg = <0x11800 0x00000000 0x0 0x200>; - /* The chip select number and offset */ - #address-cells = <2>; - /* The size of the chip select region */ - #size-cells = <1>; - ranges = <0 0 0x0 0x1f400000 0xc00000>, - <1 0 0x10000 0x30000000 0>, - <2 0 0x10000 0x40000000 0>, - <3 0 0x10000 0x50000000 0>, - <4 0 0x0 0x1d020000 0x10000>, - <5 0 0x0 0x1d040000 0x10000>, - <6 0 0x0 0x1d050000 0x10000>, - <7 0 0x10000 0x90000000 0>; - - cavium,cs-config@0 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <0>; - cavium,t-adr = <20>; - cavium,t-ce = <60>; - cavium,t-oe = <60>; - cavium,t-we = <45>; - cavium,t-rd-hld = <35>; - cavium,t-wr-hld = <45>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <35>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - . - . - . - cavium,cs-config@6 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <6>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <270>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <70>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,wait-mode; - cavium,bus-width = <16>; - }; - . - . - . - }; diff --git a/trunk/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/trunk/Documentation/devicetree/bindings/mips/cavium/ciu.txt deleted file mode 100644 index 2c2d0746b43d..000000000000 --- a/trunk/Documentation/devicetree/bindings/mips/cavium/ciu.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Central Interrupt Unit - -Properties: -- compatible: "cavium,octeon-3860-ciu" - - Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs. - -- interrupt-controller: This is an interrupt controller. - -- reg: The base address of the CIU's register bank. - -- #interrupt-cells: Must be <2>. The first cell is the bank within - the CIU and may have a value of 0 or 1. The second cell is the bit - within the bank and may have a value between 0 and 63. - -Example: - interrupt-controller@1070000000000 { - compatible = "cavium,octeon-3860-ciu"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0 or 1) - * 2) Bit within the register (0..63) - */ - #interrupt-cells = <2>; - reg = <0x10700 0x00000000 0x0 0x7000>; - }; diff --git a/trunk/Documentation/devicetree/bindings/mips/cavium/ciu2.txt b/trunk/Documentation/devicetree/bindings/mips/cavium/ciu2.txt deleted file mode 100644 index 0ec7ba8bbbcb..000000000000 --- a/trunk/Documentation/devicetree/bindings/mips/cavium/ciu2.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Central Interrupt Unit - -Properties: -- compatible: "cavium,octeon-6880-ciu2" - - Compatibility with 68XX SOCs. - -- interrupt-controller: This is an interrupt controller. - -- reg: The base address of the CIU's register bank. - -- #interrupt-cells: Must be <2>. The first cell is the bank within - the CIU and may have a value between 0 and 63. The second cell is - the bit within the bank and may also have a value between 0 and 63. - -Example: - interrupt-controller@1070100000000 { - compatible = "cavium,octeon-6880-ciu2"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0..63) - * 2) Bit within the register (0..63) - */ - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x10701 0x00000000 0x0 0x4000000>; - }; diff --git a/trunk/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt b/trunk/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt deleted file mode 100644 index cb4291e3b1d1..000000000000 --- a/trunk/Documentation/devicetree/bindings/mips/cavium/dma-engine.txt +++ /dev/null @@ -1,21 +0,0 @@ -* DMA Engine. - -The Octeon DMA Engine transfers between the Boot Bus and main memory. -The DMA Engine will be refered to by phandle by any device that is -connected to it. - -Properties: -- compatible: "cavium,octeon-5750-bootbus-dma" - - Compatibility with all cn52XX, cn56XX and cn6XXX SOCs. - -- reg: The base address of the DMA Engine's register bank. - -- interrupts: A single interrupt specifier. - -Example: - dma0: dma-engine@1180000000100 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000100 0x0 0x8>; - interrupts = <0 63>; - }; diff --git a/trunk/Documentation/devicetree/bindings/mips/cavium/uctl.txt b/trunk/Documentation/devicetree/bindings/mips/cavium/uctl.txt deleted file mode 100644 index aa66b9b8d801..000000000000 --- a/trunk/Documentation/devicetree/bindings/mips/cavium/uctl.txt +++ /dev/null @@ -1,46 +0,0 @@ -* UCTL USB controller glue - -Properties: -- compatible: "cavium,octeon-6335-uctl" - - Compatibility with all cn6XXX SOCs. - -- reg: The base address of the UCTL register bank. - -- #address-cells: Must be <2>. - -- #size-cells: Must be <2>. - -- ranges: Empty to signify direct mapping of the children. - -- refclk-frequency: A single cell containing the reference clock - frequency in Hz. - -- refclk-type: A string describing the reference clock connection - either "crystal" or "external". - -Example: - uctl@118006f000000 { - compatible = "cavium,octeon-6335-uctl"; - reg = <0x11800 0x6f000000 0x0 0x100>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - /* 12MHz, 24MHz and 48MHz allowed */ - refclk-frequency = <24000000>; - /* Either "crystal" or "external" */ - refclk-type = "crystal"; - - ehci@16f0000000000 { - compatible = "cavium,octeon-6335-ehci","usb-ehci"; - reg = <0x16f00 0x00000000 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - ohci@16f0000000400 { - compatible = "cavium,octeon-6335-ohci","usb-ohci"; - reg = <0x16f00 0x00000400 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - }; diff --git a/trunk/Documentation/devicetree/bindings/net/cavium-mdio.txt b/trunk/Documentation/devicetree/bindings/net/cavium-mdio.txt deleted file mode 100644 index 04cb7491d232..000000000000 --- a/trunk/Documentation/devicetree/bindings/net/cavium-mdio.txt +++ /dev/null @@ -1,27 +0,0 @@ -* System Management Interface (SMI) / MDIO - -Properties: -- compatible: "cavium,octeon-3860-mdio" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the MDIO bus controller register bank. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. MDIO addresses have no size component. - -Typically an MDIO bus might have several children. - -Example: - mdio@1180000001800 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001800 0x0 0x40>; - - ethernet-phy@0 { - ... - reg = <0>; - }; - }; diff --git a/trunk/Documentation/devicetree/bindings/net/cavium-mix.txt b/trunk/Documentation/devicetree/bindings/net/cavium-mix.txt deleted file mode 100644 index 5da628db68bf..000000000000 --- a/trunk/Documentation/devicetree/bindings/net/cavium-mix.txt +++ /dev/null @@ -1,39 +0,0 @@ -* MIX Ethernet controller. - -Properties: -- compatible: "cavium,octeon-5750-mix" - - Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX - devices. - -- reg: The base addresses of four separate register banks. The first - bank contains the MIX registers. The second bank the corresponding - AGL registers. The third bank are the AGL registers shared by all - MIX devices present. The fourth bank is the AGL_PRT_CTL shared by - all MIX devices present. - -- cell-index: A single cell specifying which portion of the shared - register banks corresponds to this MIX device. - -- interrupts: Two interrupt specifiers. The first is the MIX - interrupt routing and the second the routing for the AGL interrupts. - -- mac-address: Optional, the MAC address to assign to the device. - -- local-mac-address: Optional, the MAC address to assign to the device - if mac-address is not specified. - -- phy-handle: Optional, a phandle for the PHY device connected to this device. - -Example: - ethernet@1070000100800 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ - <0x11800 0xE0000800 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <1>; - interrupts = <1 18>, < 1 46>; - local-mac-address = [ 00 0f b7 10 63 54 ]; - phy-handle = <&phy1>; - }; diff --git a/trunk/Documentation/devicetree/bindings/net/cavium-pip.txt b/trunk/Documentation/devicetree/bindings/net/cavium-pip.txt deleted file mode 100644 index d4c53ba04b3b..000000000000 --- a/trunk/Documentation/devicetree/bindings/net/cavium-pip.txt +++ /dev/null @@ -1,98 +0,0 @@ -* PIP Ethernet nexus. - -The PIP Ethernet nexus can control several data packet input/output -devices. The devices have a two level grouping scheme. There may be -several interfaces, and each interface may have several ports. These -ports might be an individual Ethernet PHY. - - -Properties for the PIP nexus: -- compatible: "cavium,octeon-3860-pip" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the PIP's register bank. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. - -Properties for PIP interfaces which is a child the PIP nexus: -- compatible: "cavium,octeon-3860-pip-interface" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The interface number. - -- #address-cells: Must be <1>. - -- #size-cells: Must be <0>. - -Properties for PIP port which is a child the PIP interface: -- compatible: "cavium,octeon-3860-pip-port" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The port number within the interface group. - -- mac-address: Optional, the MAC address to assign to the device. - -- local-mac-address: Optional, the MAC address to assign to the device - if mac-address is not specified. - -- phy-handle: Optional, a phandle for the PHY device connected to this device. - -Example: - - pip@11800a0000000 { - compatible = "cavium,octeon-3860-pip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0xa0000000 0x0 0x2000>; - - interface@0 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 60 ]; - phy-handle = <&phy2>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 61 ]; - phy-handle = <&phy3>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 62 ]; - phy-handle = <&phy4>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 63 ]; - phy-handle = <&phy5>; - }; - }; - - interface@1 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 0f b7 10 63 64 ]; - phy-handle = <&phy6>; - }; - }; - }; diff --git a/trunk/Documentation/devicetree/bindings/serial/cavium-uart.txt b/trunk/Documentation/devicetree/bindings/serial/cavium-uart.txt deleted file mode 100644 index 87a6c375cd44..000000000000 --- a/trunk/Documentation/devicetree/bindings/serial/cavium-uart.txt +++ /dev/null @@ -1,19 +0,0 @@ -* Universal Asynchronous Receiver/Transmitter (UART) - -- compatible: "cavium,octeon-3860-uart" - - Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. - -- reg: The base address of the UART register bank. - -- interrupts: A single interrupt specifier. - -- current-speed: Optional, the current bit rate in bits per second. - -Example: - uart1: serial@1180000000c00 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000c00 0x0 0x400>; - current-speed = <115200>; - interrupts = <0 35>; - }; diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index 00045d6ce8ed..b3e10fdd3898 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -1432,8 +1432,6 @@ config CPU_CAVIUM_OCTEON select WEAK_ORDERING select CPU_SUPPORTS_HIGHMEM select CPU_SUPPORTS_HUGEPAGES - select LIBFDT - select USE_OF help The Cavium Octeon processor is a highly integrated chip containing many ethernet hardware widgets for networking tasks. The processor diff --git a/trunk/arch/mips/cavium-octeon/.gitignore b/trunk/arch/mips/cavium-octeon/.gitignore deleted file mode 100644 index 39c968605ff6..000000000000 --- a/trunk/arch/mips/cavium-octeon/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.dtb.S -*.dtb diff --git a/trunk/arch/mips/cavium-octeon/Makefile b/trunk/arch/mips/cavium-octeon/Makefile index bc96e2908f14..19eb0434269f 100644 --- a/trunk/arch/mips/cavium-octeon/Makefile +++ b/trunk/arch/mips/cavium-octeon/Makefile @@ -9,25 +9,9 @@ # Copyright (C) 2005-2009 Cavium Networks # -CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt -CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt - obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o obj-y += dma-octeon.o flash_setup.o obj-y += octeon-memcpy.o obj-y += executive/ obj-$(CONFIG_SMP) += smp.o - -DTS_FILES = octeon_3xxx.dts octeon_68xx.dts -DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES)) - -obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES)) - -$(obj)/%.dtb: $(src)/%.dts FORCE - $(call if_changed_dep,dtc) - -# Let's keep the .dtb files around in case we want to look at them. -.SECONDARY: $(addprefix $(obj)/, $(DTB_FILES)) - -clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES)) diff --git a/trunk/arch/mips/cavium-octeon/executive/cvmx-fpa.c b/trunk/arch/mips/cavium-octeon/executive/cvmx-fpa.c new file mode 100644 index 000000000000..ad44b8bd8057 --- /dev/null +++ b/trunk/arch/mips/cavium-octeon/executive/cvmx-fpa.c @@ -0,0 +1,183 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Support library for the hardware Free Pool Allocator. + * + * + */ + +#include "cvmx-config.h" +#include "cvmx.h" +#include "cvmx-fpa.h" +#include "cvmx-ipd.h" + +/** + * Current state of all the pools. Use access functions + * instead of using it directly. + */ +CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; + +/** + * Setup a FPA pool to control a new block of memory. The + * buffer pointer must be a physical address. + * + * @pool: Pool to initialize + * 0 <= pool < 8 + * @name: Constant character string to name this pool. + * String is not copied. + * @buffer: Pointer to the block of memory to use. This must be + * accessible by all processors and external hardware. + * @block_size: Size for each block controlled by the FPA + * @num_blocks: Number of blocks + * + * Returns 0 on Success, + * -1 on failure + */ +int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, + uint64_t block_size, uint64_t num_blocks) +{ + char *ptr; + if (!buffer) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n"); + return -1; + } + if (pool >= CVMX_FPA_NUM_POOLS) { + cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n"); + return -1; + } + + if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n"); + return -1; + } + + if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n"); + return -1; + } + + cvmx_fpa_pool_info[pool].name = name; + cvmx_fpa_pool_info[pool].size = block_size; + cvmx_fpa_pool_info[pool].starting_element_count = num_blocks; + cvmx_fpa_pool_info[pool].base = buffer; + + ptr = (char *)buffer; + while (num_blocks--) { + cvmx_fpa_free(ptr, pool, 0); + ptr += block_size; + } + return 0; +} + +/** + * Shutdown a Memory pool and validate that it had all of + * the buffers originally placed in it. + * + * @pool: Pool to shutdown + * Returns Zero on success + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers + */ +uint64_t cvmx_fpa_shutdown_pool(uint64_t pool) +{ + uint64_t errors = 0; + uint64_t count = 0; + uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base); + uint64_t finish = + base + + cvmx_fpa_pool_info[pool].size * + cvmx_fpa_pool_info[pool].starting_element_count; + void *ptr; + uint64_t address; + + count = 0; + do { + ptr = cvmx_fpa_alloc(pool); + if (ptr) + address = cvmx_ptr_to_phys(ptr); + else + address = 0; + if (address) { + if ((address >= base) && (address < finish) && + (((address - + base) % cvmx_fpa_pool_info[pool].size) == 0)) { + count++; + } else { + cvmx_dprintf + ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n", + (unsigned long long)address, + cvmx_fpa_pool_info[pool].name, (int)pool); + errors++; + } + } + } while (address); + +#ifdef CVMX_ENABLE_PKO_FUNCTIONS + if (pool == 0) + cvmx_ipd_free_ptr(); +#endif + + if (errors) { + cvmx_dprintf + ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n", + cvmx_fpa_pool_info[pool].name, (int)pool, + (unsigned long long)base, (unsigned long long)finish, + (unsigned long long)cvmx_fpa_pool_info[pool].size); + return -errors; + } else + return 0; +} + +uint64_t cvmx_fpa_get_block_size(uint64_t pool) +{ + switch (pool) { + case 0: + return CVMX_FPA_POOL_0_SIZE; + case 1: + return CVMX_FPA_POOL_1_SIZE; + case 2: + return CVMX_FPA_POOL_2_SIZE; + case 3: + return CVMX_FPA_POOL_3_SIZE; + case 4: + return CVMX_FPA_POOL_4_SIZE; + case 5: + return CVMX_FPA_POOL_5_SIZE; + case 6: + return CVMX_FPA_POOL_6_SIZE; + case 7: + return CVMX_FPA_POOL_7_SIZE; + default: + return 0; + } +} diff --git a/trunk/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c b/trunk/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c new file mode 100644 index 000000000000..c239e5f4ab9a --- /dev/null +++ b/trunk/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c @@ -0,0 +1,243 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Helper functions for FPA setup. + * + */ +#include "executive-config.h" +#include "cvmx-config.h" +#include "cvmx.h" +#include "cvmx-bootmem.h" +#include "cvmx-fpa.h" +#include "cvmx-helper-fpa.h" + +/** + * Allocate memory for and initialize a single FPA pool. + * + * @pool: Pool to initialize + * @buffer_size: Size of buffers to allocate in bytes + * @buffers: Number of buffers to put in the pool. Zero is allowed + * @name: String name of the pool for debugging purposes + * Returns Zero on success, non-zero on failure + */ +static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size, + uint64_t buffers, const char *name) +{ + uint64_t current_num; + void *memory; + uint64_t align = CVMX_CACHE_LINE_SIZE; + + /* + * Align the allocation so that power of 2 size buffers are + * naturally aligned. + */ + while (align < buffer_size) + align = align << 1; + + if (buffers == 0) + return 0; + + current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool)); + if (current_num) { + cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. " + "Skipping setup.\n", + pool, name, (unsigned long long)current_num); + return 0; + } + + memory = cvmx_bootmem_alloc(buffer_size * buffers, align); + if (memory == NULL) { + cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n", + pool, name); + return -1; + } + cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers); + return 0; +} + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Specifying zero for the number of + * buffers will cause that FPA pool to not be setup. This is + * useful if you aren't using some of the hardware and want + * to save memory. Use cvmx_helper_initialize_fpa instead of + * this function directly. + * + * @pip_pool: Should always be CVMX_FPA_PACKET_POOL + * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE + * @pip_buffers: + * Number of packet buffers. + * @wqe_pool: Should always be CVMX_FPA_WQE_POOL + * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE + * @wqe_entries: + * Number of work queue entries + * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL + * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_pool: Should always be CVMX_FPA_TIMER_POOL + * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_pool: Should always be CVMX_FPA_DFA_POOL + * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, + int pip_buffers, int wqe_pool, + int wqe_size, int wqe_entries, + int pko_pool, int pko_size, + int pko_buffers, int tim_pool, + int tim_size, int tim_buffers, + int dfa_pool, int dfa_size, + int dfa_buffers) +{ + int status; + + cvmx_fpa_enable(); + + if ((pip_buffers > 0) && (pip_buffers <= 64)) + cvmx_dprintf + ("Warning: %d packet buffers may not be enough for hardware" + " prefetch. 65 or more is recommended.\n", pip_buffers); + + if (pip_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size, + pip_buffers, + "Packet Buffers"); + if (status) + return status; + } + + if (wqe_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size, + wqe_entries, + "Work Queue Entries"); + if (status) + return status; + } + + if (pko_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size, + pko_buffers, + "PKO Command Buffers"); + if (status) + return status; + } + + if (tim_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size, + tim_buffers, + "TIM Command Buffers"); + if (status) + return status; + } + + if (dfa_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size, + dfa_buffers, + "DFA Command Buffers"); + if (status) + return status; + } + + return 0; +} + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Sizes of each element in the pools is + * controlled by the cvmx-config.h header file. Specifying + * zero for any parameter will cause that FPA pool to not be + * setup. This is useful if you aren't using some of the + * hardware and want to save memory. + * + * @packet_buffers: + * Number of packet buffers to allocate + * @work_queue_entries: + * Number of work queue entries + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries, + int pko_buffers, int tim_buffers, + int dfa_buffers) +{ +#ifndef CVMX_FPA_PACKET_POOL +#define CVMX_FPA_PACKET_POOL -1 +#define CVMX_FPA_PACKET_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_WQE_POOL +#define CVMX_FPA_WQE_POOL -1 +#define CVMX_FPA_WQE_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL +#define CVMX_FPA_OUTPUT_BUFFER_POOL -1 +#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_TIMER_POOL +#define CVMX_FPA_TIMER_POOL -1 +#define CVMX_FPA_TIMER_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_DFA_POOL +#define CVMX_FPA_DFA_POOL -1 +#define CVMX_FPA_DFA_POOL_SIZE 0 +#endif + return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL, + CVMX_FPA_PACKET_POOL_SIZE, + packet_buffers, CVMX_FPA_WQE_POOL, + CVMX_FPA_WQE_POOL_SIZE, + work_queue_entries, + CVMX_FPA_OUTPUT_BUFFER_POOL, + CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, + pko_buffers, CVMX_FPA_TIMER_POOL, + CVMX_FPA_TIMER_POOL_SIZE, + tim_buffers, CVMX_FPA_DFA_POOL, + CVMX_FPA_DFA_POOL_SIZE, + dfa_buffers); +} diff --git a/trunk/arch/mips/cavium-octeon/octeon-irq.c b/trunk/arch/mips/cavium-octeon/octeon-irq.c index 7fb1f222b8a5..ffd4ae660f79 100644 --- a/trunk/arch/mips/cavium-octeon/octeon-irq.c +++ b/trunk/arch/mips/cavium-octeon/octeon-irq.c @@ -3,17 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2012 Cavium, Inc. + * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks */ #include -#include #include #include -#include #include #include -#include #include @@ -45,9 +42,9 @@ struct octeon_core_chip_data { static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES]; -static void octeon_irq_set_ciu_mapping(int irq, int line, int bit, - struct irq_chip *chip, - irq_flow_handler_t handler) +static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit, + struct irq_chip *chip, + irq_flow_handler_t handler) { union octeon_ciu_chip_data cd; @@ -508,85 +505,6 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data) } } -static void octeon_irq_gpio_setup(struct irq_data *data) -{ - union cvmx_gpio_bit_cfgx cfg; - union octeon_ciu_chip_data cd; - u32 t = irqd_get_trigger_type(data); - - cd.p = irq_data_get_irq_chip_data(data); - - cfg.u64 = 0; - cfg.s.int_en = 1; - cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0; - cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0; - - /* 140 nS glitch filter*/ - cfg.s.fil_cnt = 7; - cfg.s.fil_sel = 3; - - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64); -} - -static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data) -{ - octeon_irq_gpio_setup(data); - octeon_irq_ciu_enable_v2(data); -} - -static void octeon_irq_ciu_enable_gpio(struct irq_data *data) -{ - octeon_irq_gpio_setup(data); - octeon_irq_ciu_enable(data); -} - -static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t) -{ - irqd_set_trigger_type(data, t); - octeon_irq_gpio_setup(data); - - return IRQ_SET_MASK_OK; -} - -static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data) -{ - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); - - octeon_irq_ciu_disable_all_v2(data); -} - -static void octeon_irq_ciu_disable_gpio(struct irq_data *data) -{ - union octeon_ciu_chip_data cd; - - cd.p = irq_data_get_irq_chip_data(data); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0); - - octeon_irq_ciu_disable_all(data); -} - -static void octeon_irq_ciu_gpio_ack(struct irq_data *data) -{ - union octeon_ciu_chip_data cd; - u64 mask; - - cd.p = irq_data_get_irq_chip_data(data); - mask = 1ull << (cd.s.bit - 16); - - cvmx_write_csr(CVMX_GPIO_INT_CLR, mask); -} - -static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc) -{ - if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) & IRQ_TYPE_EDGE_BOTH) - handle_edge_irq(irq, desc); - else - handle_level_irq(irq, desc); -} - #ifdef CONFIG_SMP static void octeon_irq_cpu_offline_ciu(struct irq_data *data) @@ -732,6 +650,18 @@ static struct irq_chip octeon_irq_chip_ciu_v2 = { .name = "CIU", .irq_enable = octeon_irq_ciu_enable_v2, .irq_disable = octeon_irq_ciu_disable_all_v2, + .irq_mask = octeon_irq_ciu_disable_local_v2, + .irq_unmask = octeon_irq_ciu_enable_v2, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, +#endif +}; + +static struct irq_chip octeon_irq_chip_ciu_edge_v2 = { + .name = "CIU-E", + .irq_enable = octeon_irq_ciu_enable_v2, + .irq_disable = octeon_irq_ciu_disable_all_v2, .irq_ack = octeon_irq_ciu_ack, .irq_mask = octeon_irq_ciu_disable_local_v2, .irq_unmask = octeon_irq_ciu_enable_v2, @@ -745,7 +675,6 @@ static struct irq_chip octeon_irq_chip_ciu = { .name = "CIU", .irq_enable = octeon_irq_ciu_enable, .irq_disable = octeon_irq_ciu_disable_all, - .irq_ack = octeon_irq_ciu_ack, .irq_mask = octeon_irq_dummy_mask, #ifdef CONFIG_SMP .irq_set_affinity = octeon_irq_ciu_set_affinity, @@ -753,6 +682,18 @@ static struct irq_chip octeon_irq_chip_ciu = { #endif }; +static struct irq_chip octeon_irq_chip_ciu_edge = { + .name = "CIU-E", + .irq_enable = octeon_irq_ciu_enable, + .irq_disable = octeon_irq_ciu_disable_all, + .irq_mask = octeon_irq_dummy_mask, + .irq_ack = octeon_irq_ciu_ack, +#ifdef CONFIG_SMP + .irq_set_affinity = octeon_irq_ciu_set_affinity, + .irq_cpu_offline = octeon_irq_cpu_offline_ciu, +#endif +}; + /* The mbox versions don't do any affinity or round-robin. */ static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = { .name = "CIU-M", @@ -776,33 +717,6 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = { .flags = IRQCHIP_ONOFFLINE_ENABLED, }; -static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = { - .name = "CIU-GPIO", - .irq_enable = octeon_irq_ciu_enable_gpio_v2, - .irq_disable = octeon_irq_ciu_disable_gpio_v2, - .irq_ack = octeon_irq_ciu_gpio_ack, - .irq_mask = octeon_irq_ciu_disable_local_v2, - .irq_unmask = octeon_irq_ciu_enable_v2, - .irq_set_type = octeon_irq_ciu_gpio_set_type, -#ifdef CONFIG_SMP - .irq_set_affinity = octeon_irq_ciu_set_affinity_v2, -#endif - .flags = IRQCHIP_SET_TYPE_MASKED, -}; - -static struct irq_chip octeon_irq_chip_ciu_gpio = { - .name = "CIU-GPIO", - .irq_enable = octeon_irq_ciu_enable_gpio, - .irq_disable = octeon_irq_ciu_disable_gpio, - .irq_mask = octeon_irq_dummy_mask, - .irq_ack = octeon_irq_ciu_gpio_ack, - .irq_set_type = octeon_irq_ciu_gpio_set_type, -#ifdef CONFIG_SMP - .irq_set_affinity = octeon_irq_ciu_set_affinity, -#endif - .flags = IRQCHIP_SET_TYPE_MASKED, -}; - /* * Watchdog interrupts are special. They are associated with a single * core, so we hardwire the affinity to that core. @@ -850,178 +764,6 @@ static struct irq_chip octeon_irq_chip_ciu_wd = { .irq_mask = octeon_irq_dummy_mask, }; -static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit) -{ - bool edge = false; - - if (line == 0) - switch (bit) { - case 48 ... 49: /* GMX DRP */ - case 50: /* IPD_DRP */ - case 52 ... 55: /* Timers */ - case 58: /* MPI */ - edge = true; - break; - default: - break; - } - else /* line == 1 */ - switch (bit) { - case 47: /* PTP */ - edge = true; - break; - default: - break; - } - return edge; -} - -struct octeon_irq_gpio_domain_data { - unsigned int base_hwirq; -}; - -static int octeon_irq_gpio_xlat(struct irq_domain *d, - struct device_node *node, - const u32 *intspec, - unsigned int intsize, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - unsigned int type; - unsigned int pin; - unsigned int trigger; - struct octeon_irq_gpio_domain_data *gpiod; - - if (d->of_node != node) - return -EINVAL; - - if (intsize < 2) - return -EINVAL; - - pin = intspec[0]; - if (pin >= 16) - return -EINVAL; - - trigger = intspec[1]; - - switch (trigger) { - case 1: - type = IRQ_TYPE_EDGE_RISING; - break; - case 2: - type = IRQ_TYPE_EDGE_FALLING; - break; - case 4: - type = IRQ_TYPE_LEVEL_HIGH; - break; - case 8: - type = IRQ_TYPE_LEVEL_LOW; - break; - default: - pr_err("Error: (%s) Invalid irq trigger specification: %x\n", - node->name, - trigger); - type = IRQ_TYPE_LEVEL_LOW; - break; - } - *out_type = type; - gpiod = d->host_data; - *out_hwirq = gpiod->base_hwirq + pin; - - return 0; -} - -static int octeon_irq_ciu_xlat(struct irq_domain *d, - struct device_node *node, - const u32 *intspec, - unsigned int intsize, - unsigned long *out_hwirq, - unsigned int *out_type) -{ - unsigned int ciu, bit; - - ciu = intspec[0]; - bit = intspec[1]; - - if (ciu > 1 || bit > 63) - return -EINVAL; - - /* These are the GPIO lines */ - if (ciu == 0 && bit >= 16 && bit < 32) - return -EINVAL; - - *out_hwirq = (ciu << 6) | bit; - *out_type = 0; - - return 0; -} - -static struct irq_chip *octeon_irq_ciu_chip; -static struct irq_chip *octeon_irq_gpio_chip; - -static bool octeon_irq_virq_in_range(unsigned int virq) -{ - /* We cannot let it overflow the mapping array. */ - if (virq < (1ul << 8 * sizeof(octeon_irq_ciu_to_irq[0][0]))) - return true; - - WARN_ONCE(true, "virq out of range %u.\n", virq); - return false; -} - -static int octeon_irq_ciu_map(struct irq_domain *d, - unsigned int virq, irq_hw_number_t hw) -{ - unsigned int line = hw >> 6; - unsigned int bit = hw & 63; - - if (!octeon_irq_virq_in_range(virq)) - return -EINVAL; - - if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) - return -EINVAL; - - if (octeon_irq_ciu_is_edge(line, bit)) - octeon_irq_set_ciu_mapping(virq, line, bit, - octeon_irq_ciu_chip, - handle_edge_irq); - else - octeon_irq_set_ciu_mapping(virq, line, bit, - octeon_irq_ciu_chip, - handle_level_irq); - - return 0; -} - -static int octeon_irq_gpio_map(struct irq_domain *d, - unsigned int virq, irq_hw_number_t hw) -{ - unsigned int line = hw >> 6; - unsigned int bit = hw & 63; - - if (!octeon_irq_virq_in_range(virq)) - return -EINVAL; - - if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0) - return -EINVAL; - - octeon_irq_set_ciu_mapping(virq, line, bit, - octeon_irq_gpio_chip, - octeon_irq_handle_gpio); - - return 0; -} - -static struct irq_domain_ops octeon_irq_domain_ciu_ops = { - .map = octeon_irq_ciu_map, - .xlate = octeon_irq_ciu_xlat, -}; - -static struct irq_domain_ops octeon_irq_domain_gpio_ops = { - .map = octeon_irq_gpio_map, - .xlate = octeon_irq_gpio_xlat, -}; - static void octeon_irq_ip2_v1(void) { const unsigned long core_id = cvmx_get_core_num(); @@ -1145,10 +887,9 @@ static void __init octeon_irq_init_ciu(void) { unsigned int i; struct irq_chip *chip; + struct irq_chip *chip_edge; struct irq_chip *chip_mbox; struct irq_chip *chip_wd; - struct device_node *gpio_node; - struct device_node *ciu_node; octeon_irq_init_ciu_percpu(); octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu; @@ -1160,18 +901,17 @@ static void __init octeon_irq_init_ciu(void) octeon_irq_ip2 = octeon_irq_ip2_v2; octeon_irq_ip3 = octeon_irq_ip3_v2; chip = &octeon_irq_chip_ciu_v2; + chip_edge = &octeon_irq_chip_ciu_edge_v2; chip_mbox = &octeon_irq_chip_ciu_mbox_v2; chip_wd = &octeon_irq_chip_ciu_wd_v2; - octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2; } else { octeon_irq_ip2 = octeon_irq_ip2_v1; octeon_irq_ip3 = octeon_irq_ip3_v1; chip = &octeon_irq_chip_ciu; + chip_edge = &octeon_irq_chip_ciu_edge; chip_mbox = &octeon_irq_chip_ciu_mbox; chip_wd = &octeon_irq_chip_ciu_wd; - octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio; } - octeon_irq_ciu_chip = chip; octeon_irq_ip4 = octeon_irq_ip4_mask; /* Mips internal */ @@ -1180,49 +920,80 @@ static void __init octeon_irq_init_ciu(void) /* CIU_0 */ for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq); + for (i = 0; i < 16; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq); + for (i = 0; i < 4; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq); for (i = 0; i < 4; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq); + + for (i = 0; i < 2; i++) + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq); + for (i = 0; i < 4; i++) - octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip, handle_edge_irq); + octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq); /* CIU_1 */ for (i = 0; i < 16; i++) octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq); octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq); - - gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio"); - if (gpio_node) { - struct octeon_irq_gpio_domain_data *gpiod; - - gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL); - if (gpiod) { - /* gpio domain host_data is the base hwirq number. */ - gpiod->base_hwirq = 16; - irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod); - of_node_put(gpio_node); - } else - pr_warn("Cannot allocate memory for GPIO irq_domain.\n"); - } else - pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n"); - - ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu"); - if (ciu_node) { - irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL); - of_node_put(ciu_node); - } else - pr_warn("Cannot find device node for cavium,octeon-3860-ciu.\n"); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq); + + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq); + octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq); /* Enable the CIU lines */ set_c0_status(STATUSF_IP3 | STATUSF_IP2); diff --git a/trunk/arch/mips/cavium-octeon/octeon-platform.c b/trunk/arch/mips/cavium-octeon/octeon-platform.c index 0938df10a71c..cd61d7281d91 100644 --- a/trunk/arch/mips/cavium-octeon/octeon-platform.c +++ b/trunk/arch/mips/cavium-octeon/octeon-platform.c @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2004-2011 Cavium Networks + * Copyright (C) 2004-2010 Cavium Networks * Copyright (C) 2008 Wind River Systems */ @@ -13,16 +13,10 @@ #include #include #include -#include #include -#include -#include -#include #include #include -#include -#include static struct octeon_cf_data octeon_cf_data; @@ -168,6 +162,182 @@ static int __init octeon_rng_device_init(void) } device_initcall(octeon_rng_device_init); +static struct i2c_board_info __initdata octeon_i2c_devices[] = { + { + I2C_BOARD_INFO("ds1337", 0x68), + }, +}; + +static int __init octeon_i2c_devices_init(void) +{ + return i2c_register_board_info(0, octeon_i2c_devices, + ARRAY_SIZE(octeon_i2c_devices)); +} +arch_initcall(octeon_i2c_devices_init); + +#define OCTEON_I2C_IO_BASE 0x1180000001000ull +#define OCTEON_I2C_IO_UNIT_OFFSET 0x200 + +static struct octeon_i2c_data octeon_i2c_data[2]; + +static int __init octeon_i2c_device_init(void) +{ + struct platform_device *pd; + int ret = 0; + int port, num_ports; + + struct resource i2c_resources[] = { + { + .flags = IORESOURCE_MEM, + }, { + .flags = IORESOURCE_IRQ, + } + }; + + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) + num_ports = 2; + else + num_ports = 1; + + for (port = 0; port < num_ports; port++) { + octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate(); + /*FIXME: should be examined. At the moment is set for 100Khz */ + octeon_i2c_data[port].i2c_freq = 100000; + + pd = platform_device_alloc("i2c-octeon", port); + if (!pd) { + ret = -ENOMEM; + goto out; + } + + pd->dev.platform_data = octeon_i2c_data + port; + + i2c_resources[0].start = + OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET); + i2c_resources[0].end = i2c_resources[0].start + 0x1f; + switch (port) { + case 0: + i2c_resources[1].start = OCTEON_IRQ_TWSI; + i2c_resources[1].end = OCTEON_IRQ_TWSI; + break; + case 1: + i2c_resources[1].start = OCTEON_IRQ_TWSI2; + i2c_resources[1].end = OCTEON_IRQ_TWSI2; + break; + default: + BUG(); + } + + ret = platform_device_add_resources(pd, + i2c_resources, + ARRAY_SIZE(i2c_resources)); + if (ret) + goto fail; + + ret = platform_device_add(pd); + if (ret) + goto fail; + } + return ret; +fail: + platform_device_put(pd); +out: + return ret; +} +device_initcall(octeon_i2c_device_init); + +/* Octeon SMI/MDIO interface. */ +static int __init octeon_mdiobus_device_init(void) +{ + struct platform_device *pd; + int ret = 0; + + if (octeon_is_simulation()) + return 0; /* No mdio in the simulator. */ + + /* The bus number is the platform_device id. */ + pd = platform_device_alloc("mdio-octeon", 0); + if (!pd) { + ret = -ENOMEM; + goto out; + } + + ret = platform_device_add(pd); + if (ret) + goto fail; + + return ret; +fail: + platform_device_put(pd); + +out: + return ret; + +} +device_initcall(octeon_mdiobus_device_init); + +/* Octeon mgmt port Ethernet interface. */ +static int __init octeon_mgmt_device_init(void) +{ + struct platform_device *pd; + int ret = 0; + int port, num_ports; + + struct resource mgmt_port_resource = { + .flags = IORESOURCE_IRQ, + .start = -1, + .end = -1 + }; + + if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX)) + return 0; + + if (OCTEON_IS_MODEL(OCTEON_CN56XX)) + num_ports = 1; + else + num_ports = 2; + + for (port = 0; port < num_ports; port++) { + pd = platform_device_alloc("octeon_mgmt", port); + if (!pd) { + ret = -ENOMEM; + goto out; + } + /* No DMA restrictions */ + pd->dev.coherent_dma_mask = DMA_BIT_MASK(64); + pd->dev.dma_mask = &pd->dev.coherent_dma_mask; + + switch (port) { + case 0: + mgmt_port_resource.start = OCTEON_IRQ_MII0; + break; + case 1: + mgmt_port_resource.start = OCTEON_IRQ_MII1; + break; + default: + BUG(); + } + mgmt_port_resource.end = mgmt_port_resource.start; + + ret = platform_device_add_resources(pd, &mgmt_port_resource, 1); + + if (ret) + goto fail; + + ret = platform_device_add(pd); + if (ret) + goto fail; + } + return ret; +fail: + platform_device_put(pd); + +out: + return ret; + +} +device_initcall(octeon_mgmt_device_init); + #ifdef CONFIG_USB static int __init octeon_ehci_device_init(void) @@ -270,521 +440,6 @@ device_initcall(octeon_ohci_device_init); #endif /* CONFIG_USB */ -static struct of_device_id __initdata octeon_ids[] = { - { .compatible = "simple-bus", }, - { .compatible = "cavium,octeon-6335-uctl", }, - { .compatible = "cavium,octeon-3860-bootbus", }, - { .compatible = "cavium,mdio-mux", }, - { .compatible = "gpio-leds", }, - {}, -}; - -static bool __init octeon_has_88e1145(void) -{ - return !OCTEON_IS_MODEL(OCTEON_CN52XX) && - !OCTEON_IS_MODEL(OCTEON_CN6XXX) && - !OCTEON_IS_MODEL(OCTEON_CN56XX); -} - -static void __init octeon_fdt_set_phy(int eth, int phy_addr) -{ - const __be32 *phy_handle; - const __be32 *alt_phy_handle; - const __be32 *reg; - u32 phandle; - int phy; - int alt_phy; - const char *p; - int current_len; - char new_name[20]; - - phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL); - if (!phy_handle) - return; - - phandle = be32_to_cpup(phy_handle); - phy = fdt_node_offset_by_phandle(initial_boot_params, phandle); - - alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); - if (alt_phy_handle) { - u32 alt_phandle = be32_to_cpup(alt_phy_handle); - alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle); - } else { - alt_phy = -1; - } - - if (phy_addr < 0 || phy < 0) { - /* Delete the PHY things */ - fdt_nop_property(initial_boot_params, eth, "phy-handle"); - /* This one may fail */ - fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle"); - if (phy >= 0) - fdt_nop_node(initial_boot_params, phy); - if (alt_phy >= 0) - fdt_nop_node(initial_boot_params, alt_phy); - return; - } - - if (phy_addr >= 256 && alt_phy > 0) { - const struct fdt_property *phy_prop; - struct fdt_property *alt_prop; - u32 phy_handle_name; - - /* Use the alt phy node instead.*/ - phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL); - phy_handle_name = phy_prop->nameoff; - fdt_nop_node(initial_boot_params, phy); - fdt_nop_property(initial_boot_params, eth, "phy-handle"); - alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL); - alt_prop->nameoff = phy_handle_name; - phy = alt_phy; - } - - phy_addr &= 0xff; - - if (octeon_has_88e1145()) { - fdt_nop_property(initial_boot_params, phy, "marvell,reg-init"); - memset(new_name, 0, sizeof(new_name)); - strcpy(new_name, "marvell,88e1145"); - p = fdt_getprop(initial_boot_params, phy, "compatible", - ¤t_len); - if (p && current_len >= strlen(new_name)) - fdt_setprop_inplace(initial_boot_params, phy, - "compatible", new_name, current_len); - } - - reg = fdt_getprop(initial_boot_params, phy, "reg", NULL); - if (phy_addr == be32_to_cpup(reg)) - return; - - fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr); - - snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr); - - p = fdt_get_name(initial_boot_params, phy, ¤t_len); - if (p && current_len == strlen(new_name)) - fdt_set_name(initial_boot_params, phy, new_name); - else - pr_err("Error: could not rename ethernet phy: <%s>", p); -} - -static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac) -{ - u8 new_mac[6]; - u64 mac = *pmac; - int r; - - new_mac[0] = (mac >> 40) & 0xff; - new_mac[1] = (mac >> 32) & 0xff; - new_mac[2] = (mac >> 24) & 0xff; - new_mac[3] = (mac >> 16) & 0xff; - new_mac[4] = (mac >> 8) & 0xff; - new_mac[5] = mac & 0xff; - - r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address", - new_mac, sizeof(new_mac)); - - if (r) { - pr_err("Setting \"local-mac-address\" failed %d", r); - return; - } - *pmac = mac + 1; -} - -static void __init octeon_fdt_rm_ethernet(int node) -{ - const __be32 *phy_handle; - - phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL); - if (phy_handle) { - u32 ph = be32_to_cpup(phy_handle); - int p = fdt_node_offset_by_phandle(initial_boot_params, ph); - if (p >= 0) - fdt_nop_node(initial_boot_params, p); - } - fdt_nop_node(initial_boot_params, node); -} - -static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac) -{ - char name_buffer[20]; - int eth; - int phy_addr; - int ipd_port; - - snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p); - eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer); - if (eth < 0) - return; - if (p > max) { - pr_debug("Deleting port %x:%x\n", i, p); - octeon_fdt_rm_ethernet(eth); - return; - } - if (OCTEON_IS_MODEL(OCTEON_CN68XX)) - ipd_port = (0x100 * i) + (0x10 * p) + 0x800; - else - ipd_port = 16 * i + p; - - phy_addr = cvmx_helper_board_get_mii_address(ipd_port); - octeon_fdt_set_phy(eth, phy_addr); - octeon_fdt_set_mac_addr(eth, pmac); -} - -static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac) -{ - char name_buffer[20]; - int iface; - int p; - int count; - - count = cvmx_helper_interface_enumerate(idx); - - snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx); - iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer); - if (iface < 0) - return; - - for (p = 0; p < 16; p++) - octeon_fdt_pip_port(iface, idx, p, count - 1, pmac); -} - -int __init octeon_prune_device_tree(void) -{ - int i, max_port, uart_mask; - const char *pip_path; - const char *alias_prop; - char name_buffer[20]; - int aliases; - u64 mac_addr_base; - - if (fdt_check_header(initial_boot_params)) - panic("Corrupt Device Tree."); - - aliases = fdt_path_offset(initial_boot_params, "/aliases"); - if (aliases < 0) { - pr_err("Error: No /aliases node in device tree."); - return -EINVAL; - } - - - mac_addr_base = - ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 | - ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 | - ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 | - ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 | - ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 | - (octeon_bootinfo->mac_addr_base[5] & 0xffull); - - if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX)) - max_port = 2; - else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)) - max_port = 1; - else - max_port = 0; - - if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E) - max_port = 0; - - for (i = 0; i < 2; i++) { - int mgmt; - snprintf(name_buffer, sizeof(name_buffer), - "mix%d", i); - alias_prop = fdt_getprop(initial_boot_params, aliases, - name_buffer, NULL); - if (alias_prop) { - mgmt = fdt_path_offset(initial_boot_params, alias_prop); - if (mgmt < 0) - continue; - if (i >= max_port) { - pr_debug("Deleting mix%d\n", i); - octeon_fdt_rm_ethernet(mgmt); - fdt_nop_property(initial_boot_params, aliases, - name_buffer); - } else { - int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i); - octeon_fdt_set_phy(mgmt, phy_addr); - octeon_fdt_set_mac_addr(mgmt, &mac_addr_base); - } - } - } - - pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL); - if (pip_path) { - int pip = fdt_path_offset(initial_boot_params, pip_path); - if (pip >= 0) - for (i = 0; i <= 4; i++) - octeon_fdt_pip_iface(pip, i, &mac_addr_base); - } - - /* I2C */ - if (OCTEON_IS_MODEL(OCTEON_CN52XX) || - OCTEON_IS_MODEL(OCTEON_CN63XX) || - OCTEON_IS_MODEL(OCTEON_CN68XX) || - OCTEON_IS_MODEL(OCTEON_CN56XX)) - max_port = 2; - else - max_port = 1; - - for (i = 0; i < 2; i++) { - int i2c; - snprintf(name_buffer, sizeof(name_buffer), - "twsi%d", i); - alias_prop = fdt_getprop(initial_boot_params, aliases, - name_buffer, NULL); - - if (alias_prop) { - i2c = fdt_path_offset(initial_boot_params, alias_prop); - if (i2c < 0) - continue; - if (i >= max_port) { - pr_debug("Deleting twsi%d\n", i); - fdt_nop_node(initial_boot_params, i2c); - fdt_nop_property(initial_boot_params, aliases, - name_buffer); - } - } - } - - /* SMI/MDIO */ - if (OCTEON_IS_MODEL(OCTEON_CN68XX)) - max_port = 4; - else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || - OCTEON_IS_MODEL(OCTEON_CN63XX) || - OCTEON_IS_MODEL(OCTEON_CN56XX)) - max_port = 2; - else - max_port = 1; - - for (i = 0; i < 2; i++) { - int i2c; - snprintf(name_buffer, sizeof(name_buffer), - "smi%d", i); - alias_prop = fdt_getprop(initial_boot_params, aliases, - name_buffer, NULL); - - if (alias_prop) { - i2c = fdt_path_offset(initial_boot_params, alias_prop); - if (i2c < 0) - continue; - if (i >= max_port) { - pr_debug("Deleting smi%d\n", i); - fdt_nop_node(initial_boot_params, i2c); - fdt_nop_property(initial_boot_params, aliases, - name_buffer); - } - } - } - - /* Serial */ - uart_mask = 3; - - /* Right now CN52XX is the only chip with a third uart */ - if (OCTEON_IS_MODEL(OCTEON_CN52XX)) - uart_mask |= 4; /* uart2 */ - - for (i = 0; i < 3; i++) { - int uart; - snprintf(name_buffer, sizeof(name_buffer), - "uart%d", i); - alias_prop = fdt_getprop(initial_boot_params, aliases, - name_buffer, NULL); - - if (alias_prop) { - uart = fdt_path_offset(initial_boot_params, alias_prop); - if (uart_mask & (1 << i)) - continue; - pr_debug("Deleting uart%d\n", i); - fdt_nop_node(initial_boot_params, uart); - fdt_nop_property(initial_boot_params, aliases, - name_buffer); - } - } - - /* Compact Flash */ - alias_prop = fdt_getprop(initial_boot_params, aliases, - "cf0", NULL); - if (alias_prop) { - union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; - unsigned long base_ptr, region_base, region_size; - unsigned long region1_base = 0; - unsigned long region1_size = 0; - int cs, bootbus; - bool is_16bit = false; - bool is_true_ide = false; - __be32 new_reg[6]; - __be32 *ranges; - int len; - - int cf = fdt_path_offset(initial_boot_params, alias_prop); - base_ptr = 0; - if (octeon_bootinfo->major_version == 1 - && octeon_bootinfo->minor_version >= 1) { - if (octeon_bootinfo->compact_flash_common_base_addr) - base_ptr = octeon_bootinfo->compact_flash_common_base_addr; - } else { - base_ptr = 0x1d000800; - } - - if (!base_ptr) - goto no_cf; - - /* Find CS0 region. */ - for (cs = 0; cs < 8; cs++) { - mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); - region_base = mio_boot_reg_cfg.s.base << 16; - region_size = (mio_boot_reg_cfg.s.size + 1) << 16; - if (mio_boot_reg_cfg.s.en && base_ptr >= region_base - && base_ptr < region_base + region_size) { - is_16bit = mio_boot_reg_cfg.s.width; - break; - } - } - if (cs >= 7) { - /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */ - goto no_cf; - } - - if (!(base_ptr & 0xfffful)) { - /* - * Boot loader signals availability of DMA (true_ide - * mode) by setting low order bits of base_ptr to - * zero. - */ - - /* Asume that CS1 immediately follows. */ - mio_boot_reg_cfg.u64 = - cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1)); - region1_base = mio_boot_reg_cfg.s.base << 16; - region1_size = (mio_boot_reg_cfg.s.size + 1) << 16; - if (!mio_boot_reg_cfg.s.en) - goto no_cf; - is_true_ide = true; - - } else { - fdt_nop_property(initial_boot_params, cf, "cavium,true-ide"); - fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle"); - if (!is_16bit) { - __be32 width = cpu_to_be32(8); - fdt_setprop_inplace(initial_boot_params, cf, - "cavium,bus-width", &width, sizeof(width)); - } - } - new_reg[0] = cpu_to_be32(cs); - new_reg[1] = cpu_to_be32(0); - new_reg[2] = cpu_to_be32(0x10000); - new_reg[3] = cpu_to_be32(cs + 1); - new_reg[4] = cpu_to_be32(0); - new_reg[5] = cpu_to_be32(0x10000); - fdt_setprop_inplace(initial_boot_params, cf, - "reg", new_reg, sizeof(new_reg)); - - bootbus = fdt_parent_offset(initial_boot_params, cf); - if (bootbus < 0) - goto no_cf; - ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); - if (!ranges || len < (5 * 8 * sizeof(__be32))) - goto no_cf; - - ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); - ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); - ranges[(cs * 5) + 4] = cpu_to_be32(region_size); - if (is_true_ide) { - cs++; - ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32); - ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff); - ranges[(cs * 5) + 4] = cpu_to_be32(region1_size); - } - goto end_cf; -no_cf: - fdt_nop_node(initial_boot_params, cf); - -end_cf: - ; - } - - /* 8 char LED */ - alias_prop = fdt_getprop(initial_boot_params, aliases, - "led0", NULL); - if (alias_prop) { - union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; - unsigned long base_ptr, region_base, region_size; - int cs, bootbus; - __be32 new_reg[6]; - __be32 *ranges; - int len; - int led = fdt_path_offset(initial_boot_params, alias_prop); - - base_ptr = octeon_bootinfo->led_display_base_addr; - if (base_ptr == 0) - goto no_led; - /* Find CS0 region. */ - for (cs = 0; cs < 8; cs++) { - mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); - region_base = mio_boot_reg_cfg.s.base << 16; - region_size = (mio_boot_reg_cfg.s.size + 1) << 16; - if (mio_boot_reg_cfg.s.en && base_ptr >= region_base - && base_ptr < region_base + region_size) - break; - } - - if (cs > 7) - goto no_led; - - new_reg[0] = cpu_to_be32(cs); - new_reg[1] = cpu_to_be32(0x20); - new_reg[2] = cpu_to_be32(0x20); - new_reg[3] = cpu_to_be32(cs); - new_reg[4] = cpu_to_be32(0); - new_reg[5] = cpu_to_be32(0x20); - fdt_setprop_inplace(initial_boot_params, led, - "reg", new_reg, sizeof(new_reg)); - - bootbus = fdt_parent_offset(initial_boot_params, led); - if (bootbus < 0) - goto no_led; - ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len); - if (!ranges || len < (5 * 8 * sizeof(__be32))) - goto no_led; - - ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32); - ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff); - ranges[(cs * 5) + 4] = cpu_to_be32(region_size); - goto end_led; - -no_led: - fdt_nop_node(initial_boot_params, led); -end_led: - ; - } - - /* OHCI/UHCI USB */ - alias_prop = fdt_getprop(initial_boot_params, aliases, - "uctl", NULL); - if (alias_prop) { - int uctl = fdt_path_offset(initial_boot_params, alias_prop); - - if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) || - octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) { - pr_debug("Deleting uctl\n"); - fdt_nop_node(initial_boot_params, uctl); - fdt_nop_property(initial_boot_params, aliases, "uctl"); - } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E || - octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) { - /* Missing "refclk-type" defaults to crystal. */ - fdt_nop_property(initial_boot_params, uctl, "refclk-type"); - } - } - - return 0; -} - -static int __init octeon_publish_devices(void) -{ - return of_platform_bus_probe(NULL, octeon_ids, NULL); -} -device_initcall(octeon_publish_devices); - MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Platform driver for Octeon SOC"); diff --git a/trunk/arch/mips/cavium-octeon/octeon_3xxx.dts b/trunk/arch/mips/cavium-octeon/octeon_3xxx.dts deleted file mode 100644 index f28b2d0fde22..000000000000 --- a/trunk/arch/mips/cavium-octeon/octeon_3xxx.dts +++ /dev/null @@ -1,571 +0,0 @@ -/dts-v1/; -/* - * OCTEON 3XXX, 5XXX, 63XX device tree skeleton. - * - * This device tree is pruned and patched by early boot code before - * use. Because of this, it contains a super-set of the available - * devices and properties. - */ -/ { - compatible = "cavium,octeon-3860"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&ciu>; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; /* Direct mapping */ - - ciu: interrupt-controller@1070000000000 { - compatible = "cavium,octeon-3860-ciu"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0 or 1) - * 2) Bit within the register (0..63) - */ - #interrupt-cells = <2>; - reg = <0x10700 0x00000000 0x0 0x7000>; - }; - - gpio: gpio-controller@1070000000800 { - #gpio-cells = <2>; - compatible = "cavium,octeon-3860-gpio"; - reg = <0x10700 0x00000800 0x0 0x100>; - gpio-controller; - /* Interrupts are specified by two parts: - * 1) GPIO pin number (0..15) - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - interrupt-controller; - #interrupt-cells = <2>; - /* The GPIO pin connect to 16 consecutive CUI bits */ - interrupts = <0 16>, <0 17>, <0 18>, <0 19>, - <0 20>, <0 21>, <0 22>, <0 23>, - <0 24>, <0 25>, <0 26>, <0 27>, - <0 28>, <0 29>, <0 30>, <0 31>; - }; - - smi0: mdio@1180000001800 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001800 0x0 0x40>; - - phy0: ethernet-phy@0 { - compatible = "marvell,88e1118"; - marvell,reg-init = - /* Fix rx and tx clock transition timing */ - <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ - /* Adjust LED drive. */ - <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ - /* irq, blink-activity, blink-link */ - <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ - reg = <0>; - }; - - phy1: ethernet-phy@1 { - compatible = "marvell,88e1118"; - marvell,reg-init = - /* Fix rx and tx clock transition timing */ - <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ - /* Adjust LED drive. */ - <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ - /* irq, blink-activity, blink-link */ - <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ - reg = <1>; - }; - - phy2: ethernet-phy@2 { - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy3: ethernet-phy@3 { - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy4: ethernet-phy@4 { - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy5: ethernet-phy@5 { - reg = <5>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - - phy6: ethernet-phy@6 { - reg = <6>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy7: ethernet-phy@7 { - reg = <7>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy8: ethernet-phy@8 { - reg = <8>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy9: ethernet-phy@9 { - reg = <9>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi1: mdio@1180000001900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00001900 0x0 0x40>; - - phy100: ethernet-phy@1 { - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy101: ethernet-phy@2 { - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy102: ethernet-phy@3 { - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - phy103: ethernet-phy@4 { - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - interrupt-parent = <&gpio>; - interrupts = <12 8>; /* Pin 12, active low */ - }; - }; - - mix0: ethernet@1070000100000 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ - <0x11800 0xE0000000 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <0>; - interrupts = <0 62>, <1 46>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy0>; - }; - - mix1: ethernet@1070000100800 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */ - <0x11800 0xE0000800 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002008 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <1>; - interrupts = <1 18>, < 1 46>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy1>; - }; - - pip: pip@11800a0000000 { - compatible = "cavium,octeon-3860-pip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0xa0000000 0x0 0x2000>; - - interface@0 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy2>; - cavium,alt-phy-handle = <&phy100>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy3>; - cavium,alt-phy-handle = <&phy101>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy4>; - cavium,alt-phy-handle = <&phy102>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy5>; - cavium,alt-phy-handle = <&phy103>; - }; - ethernet@4 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x4>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@5 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x5>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@6 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x6>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@7 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x7>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@8 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x8>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@9 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x9>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@a { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xa>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@b { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xb>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@c { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xc>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@d { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xd>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@e { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xe>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - ethernet@f { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0xf>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - interface@1 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy6>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy7>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy8>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy9>; - }; - }; - }; - - twsi0: i2c@1180000001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001000 0x0 0x200>; - interrupts = <0 45>; - clock-frequency = <100000>; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; - tmp@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - }; - - twsi1: i2c@1180000001200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001200 0x0 0x200>; - interrupts = <0 59>; - clock-frequency = <100000>; - }; - - uart0: serial@1180000000800 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000800 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <0 34>; - }; - - uart1: serial@1180000000c00 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000c00 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <0 35>; - }; - - uart2: serial@1180000000400 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000400 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <1 16>; - }; - - bootbus: bootbus@1180000000000 { - compatible = "cavium,octeon-3860-bootbus"; - reg = <0x11800 0x00000000 0x0 0x200>; - /* The chip select number and offset */ - #address-cells = <2>; - /* The size of the chip select region */ - #size-cells = <1>; - ranges = <0 0 0x0 0x1f400000 0xc00000>, - <1 0 0x10000 0x30000000 0>, - <2 0 0x10000 0x40000000 0>, - <3 0 0x10000 0x50000000 0>, - <4 0 0x0 0x1d020000 0x10000>, - <5 0 0x0 0x1d040000 0x10000>, - <6 0 0x0 0x1d050000 0x10000>, - <7 0 0x10000 0x90000000 0>; - - cavium,cs-config@0 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <0>; - cavium,t-adr = <20>; - cavium,t-ce = <60>; - cavium,t-oe = <60>; - cavium,t-we = <45>; - cavium,t-rd-hld = <35>; - cavium,t-wr-hld = <45>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <35>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@4 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <4>; - cavium,t-adr = <320>; - cavium,t-ce = <320>; - cavium,t-oe = <320>; - cavium,t-we = <320>; - cavium,t-rd-hld = <320>; - cavium,t-wr-hld = <320>; - cavium,t-pause = <320>; - cavium,t-wait = <320>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@5 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <5>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <125>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <30>; - cavium,t-pause = <0>; - cavium,t-wait = <30>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <16>; - }; - cavium,cs-config@6 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <6>; - cavium,t-adr = <5>; - cavium,t-ce = <300>; - cavium,t-oe = <270>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <70>; - cavium,t-pause = <0>; - cavium,t-wait = <0>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,wait-mode; - cavium,bus-width = <16>; - }; - - flash0: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - }; - - led0: led-display@4,0 { - compatible = "avago,hdsp-253x"; - reg = <4 0x20 0x20>, <4 0 0x20>; - }; - - cf0: compact-flash@5,0 { - compatible = "cavium,ebt3000-compact-flash"; - reg = <5 0 0x10000>, <6 0 0x10000>; - cavium,bus-width = <16>; - cavium,true-ide; - cavium,dma-engine-handle = <&dma0>; - }; - }; - - dma0: dma-engine@1180000000100 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000100 0x0 0x8>; - interrupts = <0 63>; - }; - dma1: dma-engine@1180000000108 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000108 0x0 0x8>; - interrupts = <0 63>; - }; - - uctl: uctl@118006f000000 { - compatible = "cavium,octeon-6335-uctl"; - reg = <0x11800 0x6f000000 0x0 0x100>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - /* 12MHz, 24MHz and 48MHz allowed */ - refclk-frequency = <12000000>; - /* Either "crystal" or "external" */ - refclk-type = "crystal"; - - ehci@16f0000000000 { - compatible = "cavium,octeon-6335-ehci","usb-ehci"; - reg = <0x16f00 0x00000000 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - ohci@16f0000000400 { - compatible = "cavium,octeon-6335-ohci","usb-ohci"; - reg = <0x16f00 0x00000400 0x0 0x100>; - interrupts = <0 56>; - big-endian-regs; - }; - }; - }; - - aliases { - mix0 = &mix0; - mix1 = &mix1; - pip = &pip; - smi0 = &smi0; - smi1 = &smi1; - twsi0 = &twsi0; - twsi1 = &twsi1; - uart0 = &uart0; - uart1 = &uart1; - uart2 = &uart2; - flash0 = &flash0; - cf0 = &cf0; - uctl = &uctl; - led0 = &led0; - }; - }; diff --git a/trunk/arch/mips/cavium-octeon/octeon_68xx.dts b/trunk/arch/mips/cavium-octeon/octeon_68xx.dts deleted file mode 100644 index 1839468932b6..000000000000 --- a/trunk/arch/mips/cavium-octeon/octeon_68xx.dts +++ /dev/null @@ -1,625 +0,0 @@ -/dts-v1/; -/* - * OCTEON 68XX device tree skeleton. - * - * This device tree is pruned and patched by early boot code before - * use. Because of this, it contains a super-set of the available - * devices and properties. - */ -/ { - compatible = "cavium,octeon-6880"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&ciu2>; - - soc@0 { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; /* Direct mapping */ - - ciu2: interrupt-controller@1070100000000 { - compatible = "cavium,octeon-6880-ciu2"; - interrupt-controller; - /* Interrupts are specified by two parts: - * 1) Controller register (0 or 7) - * 2) Bit within the register (0..63) - */ - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x10701 0x00000000 0x0 0x4000000>; - }; - - gpio: gpio-controller@1070000000800 { - #gpio-cells = <2>; - compatible = "cavium,octeon-3860-gpio"; - reg = <0x10700 0x00000800 0x0 0x100>; - gpio-controller; - /* Interrupts are specified by two parts: - * 1) GPIO pin number (0..15) - * 2) Triggering (1 - edge rising - * 2 - edge falling - * 4 - level active high - * 8 - level active low) - */ - interrupt-controller; - #interrupt-cells = <2>; - /* The GPIO pins connect to 16 consecutive CUI bits */ - interrupts = <7 0>, <7 1>, <7 2>, <7 3>, - <7 4>, <7 5>, <7 6>, <7 7>, - <7 8>, <7 9>, <7 10>, <7 11>, - <7 12>, <7 13>, <7 14>, <7 15>; - }; - - smi0: mdio@1180000003800 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003800 0x0 0x40>; - - phy0: ethernet-phy@6 { - compatible = "marvell,88e1118"; - marvell,reg-init = - /* Fix rx and tx clock transition timing */ - <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ - /* Adjust LED drive. */ - <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ - /* irq, blink-activity, blink-link */ - <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ - reg = <6>; - }; - - phy1: ethernet-phy@1 { - cavium,qlm-trim = "4,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy2: ethernet-phy@2 { - cavium,qlm-trim = "4,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy3: ethernet-phy@3 { - cavium,qlm-trim = "4,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy4: ethernet-phy@4 { - cavium,qlm-trim = "4,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi1: mdio@1180000003880 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003880 0x0 0x40>; - - phy41: ethernet-phy@1 { - cavium,qlm-trim = "0,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy42: ethernet-phy@2 { - cavium,qlm-trim = "0,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy43: ethernet-phy@3 { - cavium,qlm-trim = "0,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy44: ethernet-phy@4 { - cavium,qlm-trim = "0,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi2: mdio@1180000003900 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003900 0x0 0x40>; - - phy21: ethernet-phy@1 { - cavium,qlm-trim = "2,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy22: ethernet-phy@2 { - cavium,qlm-trim = "2,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy23: ethernet-phy@3 { - cavium,qlm-trim = "2,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy24: ethernet-phy@4 { - cavium,qlm-trim = "2,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - smi3: mdio@1180000003980 { - compatible = "cavium,octeon-3860-mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0x00003980 0x0 0x40>; - - phy11: ethernet-phy@1 { - cavium,qlm-trim = "3,sgmii"; - reg = <1>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy12: ethernet-phy@2 { - cavium,qlm-trim = "3,sgmii"; - reg = <2>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy13: ethernet-phy@3 { - cavium,qlm-trim = "3,sgmii"; - reg = <3>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - phy14: ethernet-phy@4 { - cavium,qlm-trim = "3,sgmii"; - reg = <4>; - compatible = "marvell,88e1149r"; - marvell,reg-init = <3 0x10 0 0x5777>, - <3 0x11 0 0x00aa>, - <3 0x12 0 0x4105>, - <3 0x13 0 0x0a60>; - }; - }; - - mix0: ethernet@1070000100000 { - compatible = "cavium,octeon-5750-mix"; - reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */ - <0x11800 0xE0000000 0x0 0x300>, /* AGL */ - <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED */ - <0x11800 0xE0002000 0x0 0x8>; /* AGL_PRT_CTL */ - cell-index = <0>; - interrupts = <6 40>, <6 32>; - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy0>; - }; - - pip: pip@11800a0000000 { - compatible = "cavium,octeon-3860-pip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x11800 0xa0000000 0x0 0x2000>; - - interface@4 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy1>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy2>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy3>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy4>; - }; - }; - - interface@3 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy11>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy12>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy13>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy14>; - }; - }; - - interface@2 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x2>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy21>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy22>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy23>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy24>; - }; - }; - - interface@1 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x1>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - }; - }; - - interface@0 { - compatible = "cavium,octeon-3860-pip-interface"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; /* interface */ - - ethernet@0 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x0>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy41>; - }; - ethernet@1 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x1>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy42>; - }; - ethernet@2 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x2>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy43>; - }; - ethernet@3 { - compatible = "cavium,octeon-3860-pip-port"; - reg = <0x3>; /* Port */ - local-mac-address = [ 00 00 00 00 00 00 ]; - phy-handle = <&phy44>; - }; - }; - }; - - twsi0: i2c@1180000001000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001000 0x0 0x200>; - interrupts = <3 32>; - clock-frequency = <100000>; - - rtc@68 { - compatible = "dallas,ds1337"; - reg = <0x68>; - }; - tmp@4c { - compatible = "ti,tmp421"; - reg = <0x4c>; - }; - }; - - twsi1: i2c@1180000001200 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "cavium,octeon-3860-twsi"; - reg = <0x11800 0x00001200 0x0 0x200>; - interrupts = <3 33>; - clock-frequency = <100000>; - }; - - uart0: serial@1180000000800 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000800 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <3 36>; - }; - - uart1: serial@1180000000c00 { - compatible = "cavium,octeon-3860-uart","ns16550"; - reg = <0x11800 0x00000c00 0x0 0x400>; - clock-frequency = <0>; - current-speed = <115200>; - reg-shift = <3>; - interrupts = <3 37>; - }; - - bootbus: bootbus@1180000000000 { - compatible = "cavium,octeon-3860-bootbus"; - reg = <0x11800 0x00000000 0x0 0x200>; - /* The chip select number and offset */ - #address-cells = <2>; - /* The size of the chip select region */ - #size-cells = <1>; - ranges = <0 0 0 0x1f400000 0xc00000>, - <1 0 0x10000 0x30000000 0>, - <2 0 0x10000 0x40000000 0>, - <3 0 0x10000 0x50000000 0>, - <4 0 0 0x1d020000 0x10000>, - <5 0 0 0x1d040000 0x10000>, - <6 0 0 0x1d050000 0x10000>, - <7 0 0x10000 0x90000000 0>; - - cavium,cs-config@0 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <0>; - cavium,t-adr = <10>; - cavium,t-ce = <50>; - cavium,t-oe = <50>; - cavium,t-we = <35>; - cavium,t-rd-hld = <25>; - cavium,t-wr-hld = <35>; - cavium,t-pause = <0>; - cavium,t-wait = <300>; - cavium,t-page = <25>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@4 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <4>; - cavium,t-adr = <320>; - cavium,t-ce = <320>; - cavium,t-oe = <320>; - cavium,t-we = <320>; - cavium,t-rd-hld = <320>; - cavium,t-wr-hld = <320>; - cavium,t-pause = <320>; - cavium,t-wait = <320>; - cavium,t-page = <320>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <8>; - }; - cavium,cs-config@5 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <5>; - cavium,t-adr = <0>; - cavium,t-ce = <300>; - cavium,t-oe = <125>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <300>; - cavium,t-pause = <0>; - cavium,t-wait = <300>; - cavium,t-page = <310>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,bus-width = <16>; - }; - cavium,cs-config@6 { - compatible = "cavium,octeon-3860-bootbus-config"; - cavium,cs-index = <6>; - cavium,t-adr = <0>; - cavium,t-ce = <30>; - cavium,t-oe = <125>; - cavium,t-we = <150>; - cavium,t-rd-hld = <100>; - cavium,t-wr-hld = <30>; - cavium,t-pause = <0>; - cavium,t-wait = <30>; - cavium,t-page = <310>; - cavium,t-rd-dly = <0>; - - cavium,pages = <0>; - cavium,wait-mode; - cavium,bus-width = <16>; - }; - - flash0: nor@0,0 { - compatible = "cfi-flash"; - reg = <0 0 0x800000>; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bootloader"; - reg = <0 0x200000>; - read-only; - }; - partition@200000 { - label = "kernel"; - reg = <0x200000 0x200000>; - }; - partition@400000 { - label = "cramfs"; - reg = <0x400000 0x3fe000>; - }; - partition@7fe000 { - label = "environment"; - reg = <0x7fe000 0x2000>; - read-only; - }; - }; - - led0: led-display@4,0 { - compatible = "avago,hdsp-253x"; - reg = <4 0x20 0x20>, <4 0 0x20>; - }; - - compact-flash@5,0 { - compatible = "cavium,ebt3000-compact-flash"; - reg = <5 0 0x10000>, <6 0 0x10000>; - cavium,bus-width = <16>; - cavium,true-ide; - cavium,dma-engine-handle = <&dma0>; - }; - }; - - dma0: dma-engine@1180000000100 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000100 0x0 0x8>; - interrupts = <0 63>; - }; - dma1: dma-engine@1180000000108 { - compatible = "cavium,octeon-5750-bootbus-dma"; - reg = <0x11800 0x00000108 0x0 0x8>; - interrupts = <0 63>; - }; - - uctl: uctl@118006f000000 { - compatible = "cavium,octeon-6335-uctl"; - reg = <0x11800 0x6f000000 0x0 0x100>; - ranges; /* Direct mapping */ - #address-cells = <2>; - #size-cells = <2>; - /* 12MHz, 24MHz and 48MHz allowed */ - refclk-frequency = <12000000>; - /* Either "crystal" or "external" */ - refclk-type = "crystal"; - - ehci@16f0000000000 { - compatible = "cavium,octeon-6335-ehci","usb-ehci"; - reg = <0x16f00 0x00000000 0x0 0x100>; - interrupts = <3 44>; - big-endian-regs; - }; - ohci@16f0000000400 { - compatible = "cavium,octeon-6335-ohci","usb-ohci"; - reg = <0x16f00 0x00000400 0x0 0x100>; - interrupts = <3 44>; - big-endian-regs; - }; - }; - }; - - aliases { - mix0 = &mix0; - pip = &pip; - smi0 = &smi0; - smi1 = &smi1; - smi2 = &smi2; - smi3 = &smi3; - twsi0 = &twsi0; - twsi1 = &twsi1; - uart0 = &uart0; - uart1 = &uart1; - uctl = &uctl; - led0 = &led0; - flash0 = &flash0; - }; - }; diff --git a/trunk/arch/mips/cavium-octeon/serial.c b/trunk/arch/mips/cavium-octeon/serial.c index 138b2216b4f8..057f0ae88c99 100644 --- a/trunk/arch/mips/cavium-octeon/serial.c +++ b/trunk/arch/mips/cavium-octeon/serial.c @@ -43,67 +43,95 @@ void octeon_serial_out(struct uart_port *up, int offset, int value) cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); } -static int __devinit octeon_serial_probe(struct platform_device *pdev) -{ - int irq, res; - struct resource *res_mem; - struct uart_port port; - - /* All adaptors have an irq. */ - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return irq; - - memset(&port, 0, sizeof(port)); - - port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; - port.type = PORT_OCTEON; - port.iotype = UPIO_MEM; - port.regshift = 3; - port.dev = &pdev->dev; +/* + * Allocated in .bss, so it is all zeroed. + */ +#define OCTEON_MAX_UARTS 3 +static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1]; +static struct platform_device octeon_uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = octeon_uart8250_data, + }, +}; +static void __init octeon_uart_set_common(struct plat_serial8250_port *p) +{ + p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; + p->type = PORT_OCTEON; + p->iotype = UPIO_MEM; + p->regshift = 3; /* I/O addresses are every 8 bytes */ if (octeon_is_simulation()) /* Make simulator output fast*/ - port.uartclk = 115200 * 16; + p->uartclk = 115200 * 16; else - port.uartclk = octeon_get_io_clock_rate(); + p->uartclk = octeon_get_io_clock_rate(); + p->serial_in = octeon_serial_in; + p->serial_out = octeon_serial_out; +} - port.serial_in = octeon_serial_in; - port.serial_out = octeon_serial_out; - port.irq = irq; +static int __init octeon_serial_init(void) +{ + int enable_uart0; + int enable_uart1; + int enable_uart2; + struct plat_serial8250_port *p; + +#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL + /* + * If we are configured to run as the second of two kernels, + * disable uart0 and enable uart1. Uart0 is owned by the first + * kernel + */ + enable_uart0 = 0; + enable_uart1 = 1; +#else + /* + * We are configured for the first kernel. We'll enable uart0 + * if the bootloader told us to use 0, otherwise will enable + * uart 1. + */ + enable_uart0 = (octeon_get_boot_uart() == 0); + enable_uart1 = (octeon_get_boot_uart() == 1); +#ifdef CONFIG_KGDB + enable_uart1 = 1; +#endif +#endif + + /* Right now CN52XX is the only chip with a third uart */ + enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX); + + p = octeon_uart8250_data; + if (enable_uart0) { + /* Add a ttyS device for hardware uart 0 */ + octeon_uart_set_common(p); + p->membase = (void *) CVMX_MIO_UARTX_RBR(0); + p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1); + p->irq = OCTEON_IRQ_UART0; + p++; + } - res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res_mem == NULL) { - dev_err(&pdev->dev, "found no memory resource\n"); - return -ENXIO; + if (enable_uart1) { + /* Add a ttyS device for hardware uart 1 */ + octeon_uart_set_common(p); + p->membase = (void *) CVMX_MIO_UARTX_RBR(1); + p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1); + p->irq = OCTEON_IRQ_UART1; + p++; + } + if (enable_uart2) { + /* Add a ttyS device for hardware uart 2 */ + octeon_uart_set_common(p); + p->membase = (void *) CVMX_MIO_UART2_RBR; + p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1); + p->irq = OCTEON_IRQ_UART2; + p++; } - port.mapbase = res_mem->start; - port.membase = ioremap(res_mem->start, resource_size(res_mem)); - res = serial8250_register_port(&port); + BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]); - return res >= 0 ? 0 : res; + return platform_device_register(&octeon_uart8250_device); } -static struct of_device_id octeon_serial_match[] = { - { - .compatible = "cavium,octeon-3860-uart", - }, - {}, -}; -MODULE_DEVICE_TABLE(of, octeon_serial_match); - -static struct platform_driver octeon_serial_driver = { - .probe = octeon_serial_probe, - .driver = { - .owner = THIS_MODULE, - .name = "octeon_serial", - .of_match_table = octeon_serial_match, - }, -}; - -static int __init octeon_serial_init(void) -{ - return platform_driver_register(&octeon_serial_driver); -} -late_initcall(octeon_serial_init); +device_initcall(octeon_serial_init); diff --git a/trunk/arch/mips/cavium-octeon/setup.c b/trunk/arch/mips/cavium-octeon/setup.c index 919b0fb7bb1a..260dc247c052 100644 --- a/trunk/arch/mips/cavium-octeon/setup.c +++ b/trunk/arch/mips/cavium-octeon/setup.c @@ -21,8 +21,6 @@ #include #include #include -#include -#include #include #include @@ -777,46 +775,3 @@ void prom_free_prom_memory(void) } #endif } - -int octeon_prune_device_tree(void); - -extern const char __dtb_octeon_3xxx_begin; -extern const char __dtb_octeon_3xxx_end; -extern const char __dtb_octeon_68xx_begin; -extern const char __dtb_octeon_68xx_end; -void __init device_tree_init(void) -{ - int dt_size; - struct boot_param_header *fdt; - bool do_prune; - - if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) { - fdt = phys_to_virt(octeon_bootinfo->fdt_addr); - if (fdt_check_header(fdt)) - panic("Corrupt Device Tree passed to kernel."); - dt_size = be32_to_cpu(fdt->totalsize); - do_prune = false; - } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) { - fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin; - dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin; - do_prune = true; - } else { - fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin; - dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin; - do_prune = true; - } - - /* Copy the default tree from init memory. */ - initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8); - if (initial_boot_params == NULL) - panic("Could not allocate initial_boot_params\n"); - memcpy(initial_boot_params, fdt, dt_size); - - if (do_prune) { - octeon_prune_device_tree(); - pr_info("Using internal Device Tree.\n"); - } else { - pr_info("Using passed Device Tree.\n"); - } - unflatten_device_tree(); -} diff --git a/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h b/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h index 418992042f6f..5b05f186e395 100644 --- a/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h +++ b/trunk/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -41,26 +41,61 @@ enum octeon_irq { OCTEON_IRQ_TWSI, OCTEON_IRQ_TWSI2, OCTEON_IRQ_RML, + OCTEON_IRQ_TRACE0, + OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4, + OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5, + OCTEON_IRQ_KEY_ZERO, OCTEON_IRQ_TIMER0, OCTEON_IRQ_TIMER1, OCTEON_IRQ_TIMER2, OCTEON_IRQ_TIMER3, OCTEON_IRQ_USB0, OCTEON_IRQ_USB1, + OCTEON_IRQ_PCM, + OCTEON_IRQ_MPI, + OCTEON_IRQ_POWIQ, + OCTEON_IRQ_IPDPPTHR, OCTEON_IRQ_MII0, OCTEON_IRQ_MII1, OCTEON_IRQ_BOOTDMA, -#ifndef CONFIG_PCI_MSI - OCTEON_IRQ_LAST = 127 -#endif + + OCTEON_IRQ_NAND, + OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */ + OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */ + OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */ + OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */ + OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */ + OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */ + OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */ + OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */ + OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */ + OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */ + OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */ + OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */ + OCTEON_IRQ_DFA, /* Summary of DFA */ + OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */ + OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */ + OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */ + OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */ + OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5, + OCTEON_IRQ_PTP, + OCTEON_IRQ_PEM0, + OCTEON_IRQ_PEM1, + OCTEON_IRQ_SRIO0, + OCTEON_IRQ_SRIO1, + OCTEON_IRQ_LMC0, + OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */ + OCTEON_IRQ_RST, }; #ifdef CONFIG_PCI_MSI -/* 256 - 511 represent the MSI interrupts 0-255 */ -#define OCTEON_IRQ_MSI_BIT0 (256) +/* 152 - 407 represent the MSI interrupts 0-255 */ +#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1) #define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255) #define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1) +#else +#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1) #endif #endif diff --git a/trunk/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/trunk/arch/mips/include/asm/mach-jz4740/jz4740_nand.h index bb5b9a4e29c8..986982db7c38 100644 --- a/trunk/arch/mips/include/asm/mach-jz4740/jz4740_nand.h +++ b/trunk/arch/mips/include/asm/mach-jz4740/jz4740_nand.h @@ -19,6 +19,8 @@ #include #include +#define JZ_NAND_NUM_BANKS 4 + struct jz_nand_platform_data { int num_partitions; struct mtd_partition *partitions; @@ -27,6 +29,8 @@ struct jz_nand_platform_data { unsigned int busy_gpio; + unsigned char banks[JZ_NAND_NUM_BANKS]; + void (*ident_callback)(struct platform_device *, struct nand_chip *, struct mtd_partition **, int *num_partitions); }; diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/trunk/arch/mips/include/asm/octeon/cvmx-helper-fpa.h new file mode 100644 index 000000000000..5ff8c93198de --- /dev/null +++ b/trunk/arch/mips/include/asm/octeon/cvmx-helper-fpa.h @@ -0,0 +1,64 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Helper functions for FPA setup. + * + */ +#ifndef __CVMX_HELPER_H_FPA__ +#define __CVMX_HELPER_H_FPA__ + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Sizes of each element in the pools is + * controlled by the cvmx-config.h header file. Specifying + * zero for any parameter will cause that FPA pool to not be + * setup. This is useful if you aren't using some of the + * hardware and want to save memory. + * + * @packet_buffers: + * Number of packet buffers to allocate + * @work_queue_entries: + * Number of work queue entries + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +extern int cvmx_helper_initialize_fpa(int packet_buffers, + int work_queue_entries, int pko_buffers, + int tim_buffers, int dfa_buffers); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/trunk/arch/mips/include/asm/octeon/cvmx-helper.h b/trunk/arch/mips/include/asm/octeon/cvmx-helper.h index 0ac6b9f412be..3169cd79f2ac 100644 --- a/trunk/arch/mips/include/asm/octeon/cvmx-helper.h +++ b/trunk/arch/mips/include/asm/octeon/cvmx-helper.h @@ -61,6 +61,8 @@ typedef union { } s; } cvmx_helper_link_info_t; +#include "cvmx-helper-fpa.h" + #include #include "cvmx-helper-loop.h" #include "cvmx-helper-npi.h" diff --git a/trunk/arch/mips/include/asm/octeon/octeon.h b/trunk/arch/mips/include/asm/octeon/octeon.h index 1e2486e23573..f72f768cd3a4 100644 --- a/trunk/arch/mips/include/asm/octeon/octeon.h +++ b/trunk/arch/mips/include/asm/octeon/octeon.h @@ -215,6 +215,11 @@ struct octeon_cf_data { int dma_engine; /* -1 for no DMA */ }; +struct octeon_i2c_data { + unsigned int sys_freq; + unsigned int i2c_freq; +}; + extern void octeon_write_lcd(const char *s); extern void octeon_check_cpu_bist(void); extern int octeon_get_boot_debug_flag(void); diff --git a/trunk/arch/mips/include/asm/prom.h b/trunk/arch/mips/include/asm/prom.h index 8808bf548b99..7206d445bab8 100644 --- a/trunk/arch/mips/include/asm/prom.h +++ b/trunk/arch/mips/include/asm/prom.h @@ -20,6 +20,9 @@ extern int early_init_dt_scan_memory_arch(unsigned long node, const char *uname, int depth, void *data); +extern int reserve_mem_mach(unsigned long addr, unsigned long size); +extern void free_mem_mach(unsigned long addr, unsigned long size); + extern void device_tree_init(void); static inline unsigned long pci_address_to_pio(phys_addr_t address) diff --git a/trunk/arch/mips/jz4740/platform.c b/trunk/arch/mips/jz4740/platform.c index 10929e2bc6d8..e342ed4cbd43 100644 --- a/trunk/arch/mips/jz4740/platform.c +++ b/trunk/arch/mips/jz4740/platform.c @@ -157,11 +157,29 @@ static struct resource jz4740_nand_resources[] = { .flags = IORESOURCE_MEM, }, { - .name = "bank", + .name = "bank1", .start = 0x18000000, .end = 0x180C0000 - 1, .flags = IORESOURCE_MEM, }, + { + .name = "bank2", + .start = 0x14000000, + .end = 0x140C0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank3", + .start = 0x0C000000, + .end = 0x0C0C0000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "bank4", + .start = 0x08000000, + .end = 0x080C0000 - 1, + .flags = IORESOURCE_MEM, + }, }; struct platform_device jz4740_nand_device = { diff --git a/trunk/arch/mips/kernel/prom.c b/trunk/arch/mips/kernel/prom.c index 028f6f837ef9..f11b2bbb826d 100644 --- a/trunk/arch/mips/kernel/prom.c +++ b/trunk/arch/mips/kernel/prom.c @@ -35,6 +35,16 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size) return add_memory_region(base, size, BOOT_MEM_RAM); } +int __init reserve_mem_mach(unsigned long addr, unsigned long size) +{ + return reserve_bootmem(addr, size, BOOTMEM_DEFAULT); +} + +void __init free_mem_mach(unsigned long addr, unsigned long size) +{ + return free_bootmem(addr, size); +} + void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) { return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS)); @@ -67,6 +77,25 @@ void __init early_init_devtree(void *params) of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL); } +void __init device_tree_init(void) +{ + unsigned long base, size; + + if (!initial_boot_params) + return; + + base = virt_to_phys((void *)initial_boot_params); + size = be32_to_cpu(initial_boot_params->totalsize); + + /* Before we do anything, lets reserve the dt blob */ + reserve_mem_mach(base, size); + + unflatten_device_tree(); + + /* free the space reserved for the dt blob */ + free_mem_mach(base, size); +} + void __init __dt_setup_arch(struct boot_param_header *bph) { if (be32_to_cpu(bph->magic) != OF_DT_HEADER) { diff --git a/trunk/arch/mips/netlogic/xlp/Makefile b/trunk/arch/mips/netlogic/xlp/Makefile index 9007ef0c398e..b93ed83474ec 100644 --- a/trunk/arch/mips/netlogic/xlp/Makefile +++ b/trunk/arch/mips/netlogic/xlp/Makefile @@ -1,3 +1,2 @@ obj-y += setup.o platform.o nlm_hal.o -obj-$(CONFIG_OF) += of.o obj-$(CONFIG_SMP) += wakeup.o diff --git a/trunk/arch/mips/netlogic/xlp/of.c b/trunk/arch/mips/netlogic/xlp/of.c deleted file mode 100644 index 8e3921c0c201..000000000000 --- a/trunk/arch/mips/netlogic/xlp/of.c +++ /dev/null @@ -1,34 +0,0 @@ -#include -#include -#include -#include -#include - -static int __init reserve_mem_mach(unsigned long addr, unsigned long size) -{ - return reserve_bootmem(addr, size, BOOTMEM_DEFAULT); -} - -void __init free_mem_mach(unsigned long addr, unsigned long size) -{ - return free_bootmem(addr, size); -} - -void __init device_tree_init(void) -{ - unsigned long base, size; - - if (!initial_boot_params) - return; - - base = virt_to_phys((void *)initial_boot_params); - size = be32_to_cpu(initial_boot_params->totalsize); - - /* Before we do anything, lets reserve the dt blob */ - reserve_mem_mach(base, size); - - unflatten_device_tree(); - - /* free the space reserved for the dt blob */ - free_mem_mach(base, size); -} diff --git a/trunk/drivers/i2c/busses/i2c-octeon.c b/trunk/drivers/i2c/busses/i2c-octeon.c index f44c83549fe5..ee139a598814 100644 --- a/trunk/drivers/i2c/busses/i2c-octeon.c +++ b/trunk/drivers/i2c/busses/i2c-octeon.c @@ -2,7 +2,7 @@ * (C) Copyright 2009-2010 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com * - * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc. + * Portions Copyright (C) 2010 Cavium Networks, Inc. * * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors. * @@ -11,18 +11,17 @@ * warranty of any kind, whether express or implied. */ -#include -#include #include #include -#include -#include #include #include #include -#include + #include -#include +#include +#include +#include +#include #include @@ -66,7 +65,7 @@ struct octeon_i2c { wait_queue_head_t queue; struct i2c_adapter adap; int irq; - u32 twsi_freq; + int twsi_freq; int sys_freq; resource_size_t twsi_phys; void __iomem *twsi_base; @@ -122,8 +121,10 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg) */ static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) { + u64 tmp; + __raw_writeq(data, i2c->twsi_base + TWSI_INT); - __raw_readq(i2c->twsi_base + TWSI_INT); + tmp = __raw_readq(i2c->twsi_base + TWSI_INT); } /** @@ -514,6 +515,7 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) { int irq, result = 0; struct octeon_i2c *i2c; + struct octeon_i2c_data *i2c_data; struct resource *res_mem; /* All adaptors have an irq. */ @@ -521,90 +523,86 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev) if (irq < 0) return irq; - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); if (!i2c) { dev_err(&pdev->dev, "kzalloc failed\n"); result = -ENOMEM; goto out; } i2c->dev = &pdev->dev; + i2c_data = pdev->dev.platform_data; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res_mem == NULL) { dev_err(i2c->dev, "found no memory resource\n"); result = -ENXIO; - goto out; + goto fail_region; } - i2c->twsi_phys = res_mem->start; - i2c->regsize = resource_size(res_mem); - /* - * "clock-rate" is a legacy binding, the official binding is - * "clock-frequency". Try the official one first and then - * fall back if it doesn't exist. - */ - if (of_property_read_u32(pdev->dev.of_node, - "clock-frequency", &i2c->twsi_freq) && - of_property_read_u32(pdev->dev.of_node, - "clock-rate", &i2c->twsi_freq)) { - dev_err(i2c->dev, - "no I2C 'clock-rate' or 'clock-frequency' property\n"); + if (i2c_data == NULL) { + dev_err(i2c->dev, "no I2C frequency data\n"); result = -ENXIO; - goto out; + goto fail_region; } - i2c->sys_freq = octeon_get_io_clock_rate(); + i2c->twsi_phys = res_mem->start; + i2c->regsize = resource_size(res_mem); + i2c->twsi_freq = i2c_data->i2c_freq; + i2c->sys_freq = i2c_data->sys_freq; - if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize, - res_mem->name)) { + if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) { dev_err(i2c->dev, "request_mem_region failed\n"); - goto out; + goto fail_region; } - i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize); + i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize); init_waitqueue_head(&i2c->queue); i2c->irq = irq; - result = devm_request_irq(&pdev->dev, i2c->irq, - octeon_i2c_isr, 0, DRV_NAME, i2c); + result = request_irq(i2c->irq, octeon_i2c_isr, 0, DRV_NAME, i2c); if (result < 0) { dev_err(i2c->dev, "failed to attach interrupt\n"); - goto out; + goto fail_irq; } result = octeon_i2c_initlowlevel(i2c); if (result) { dev_err(i2c->dev, "init low level failed\n"); - goto out; + goto fail_add; } result = octeon_i2c_setclock(i2c); if (result) { dev_err(i2c->dev, "clock init failed\n"); - goto out; + goto fail_add; } i2c->adap = octeon_i2c_ops; i2c->adap.dev.parent = &pdev->dev; - i2c->adap.dev.of_node = pdev->dev.of_node; + i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0; i2c_set_adapdata(&i2c->adap, i2c); platform_set_drvdata(pdev, i2c); - result = i2c_add_adapter(&i2c->adap); + result = i2c_add_numbered_adapter(&i2c->adap); if (result < 0) { dev_err(i2c->dev, "failed to add adapter\n"); goto fail_add; } - dev_info(i2c->dev, "version %s\n", DRV_VERSION); - of_i2c_register_devices(&i2c->adap); + dev_info(i2c->dev, "version %s\n", DRV_VERSION); - return 0; + return result; fail_add: platform_set_drvdata(pdev, NULL); + free_irq(i2c->irq, i2c); +fail_irq: + iounmap(i2c->twsi_base); + release_mem_region(i2c->twsi_phys, i2c->regsize); +fail_region: + kfree(i2c); out: return result; }; @@ -615,24 +613,19 @@ static int __devexit octeon_i2c_remove(struct platform_device *pdev) i2c_del_adapter(&i2c->adap); platform_set_drvdata(pdev, NULL); + free_irq(i2c->irq, i2c); + iounmap(i2c->twsi_base); + release_mem_region(i2c->twsi_phys, i2c->regsize); + kfree(i2c); return 0; }; -static struct of_device_id octeon_i2c_match[] = { - { - .compatible = "cavium,octeon-3860-twsi", - }, - {}, -}; -MODULE_DEVICE_TABLE(of, octeon_i2c_match); - static struct platform_driver octeon_i2c_driver = { .probe = octeon_i2c_probe, .remove = __devexit_p(octeon_i2c_remove), .driver = { .owner = THIS_MODULE, .name = DRV_NAME, - .of_match_table = octeon_i2c_match, }, }; @@ -642,3 +635,4 @@ MODULE_AUTHOR("Michael Lawnick "); MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/trunk/drivers/mtd/nand/jz4740_nand.c b/trunk/drivers/mtd/nand/jz4740_nand.c index a6fa884ae49b..100b6775e175 100644 --- a/trunk/drivers/mtd/nand/jz4740_nand.c +++ b/trunk/drivers/mtd/nand/jz4740_nand.c @@ -52,9 +52,10 @@ #define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1) #define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1) +#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa -#define JZ_NAND_MEM_ADDR_OFFSET 0x10000 #define JZ_NAND_MEM_CMD_OFFSET 0x08000 +#define JZ_NAND_MEM_ADDR_OFFSET 0x10000 struct jz_nand { struct mtd_info mtd; @@ -62,8 +63,11 @@ struct jz_nand { void __iomem *base; struct resource *mem; - void __iomem *bank_base; - struct resource *bank_mem; + unsigned char banks[JZ_NAND_NUM_BANKS]; + void __iomem *bank_base[JZ_NAND_NUM_BANKS]; + struct resource *bank_mem[JZ_NAND_NUM_BANKS]; + + int selected_bank; struct jz_nand_platform_data *pdata; bool is_reading; @@ -74,26 +78,50 @@ static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd) return container_of(mtd, struct jz_nand, mtd); } +static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr) +{ + struct jz_nand *nand = mtd_to_jz_nand(mtd); + struct nand_chip *chip = mtd->priv; + uint32_t ctrl; + int banknr; + + ctrl = readl(nand->base + JZ_REG_NAND_CTRL); + ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK; + + if (chipnr == -1) { + banknr = -1; + } else { + banknr = nand->banks[chipnr] - 1; + chip->IO_ADDR_R = nand->bank_base[banknr]; + chip->IO_ADDR_W = nand->bank_base[banknr]; + } + writel(ctrl, nand->base + JZ_REG_NAND_CTRL); + + nand->selected_bank = banknr; +} + static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) { struct jz_nand *nand = mtd_to_jz_nand(mtd); struct nand_chip *chip = mtd->priv; uint32_t reg; + void __iomem *bank_base = nand->bank_base[nand->selected_bank]; + + BUG_ON(nand->selected_bank < 0); if (ctrl & NAND_CTRL_CHANGE) { BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE)); if (ctrl & NAND_ALE) - chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET; + bank_base += JZ_NAND_MEM_ADDR_OFFSET; else if (ctrl & NAND_CLE) - chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET; - else - chip->IO_ADDR_W = nand->bank_base; + bank_base += JZ_NAND_MEM_CMD_OFFSET; + chip->IO_ADDR_W = bank_base; reg = readl(nand->base + JZ_REG_NAND_CTRL); if (ctrl & NAND_NCE) - reg |= JZ_NAND_CTRL_ASSERT_CHIP(0); + reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank); else - reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0); + reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank); writel(reg, nand->base + JZ_REG_NAND_CTRL); } if (dat != NAND_CMD_NONE) @@ -252,7 +280,7 @@ static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat, } static int jz_nand_ioremap_resource(struct platform_device *pdev, - const char *name, struct resource **res, void __iomem **base) + const char *name, struct resource **res, void *__iomem *base) { int ret; @@ -288,6 +316,90 @@ static int jz_nand_ioremap_resource(struct platform_device *pdev, return ret; } +static inline void jz_nand_iounmap_resource(struct resource *res, void __iomem *base) +{ + iounmap(base); + release_mem_region(res->start, resource_size(res)); +} + +static int __devinit jz_nand_detect_bank(struct platform_device *pdev, struct jz_nand *nand, unsigned char bank, size_t chipnr, uint8_t *nand_maf_id, uint8_t *nand_dev_id) { + int ret; + int gpio; + char gpio_name[9]; + char res_name[6]; + uint32_t ctrl; + struct mtd_info *mtd = &nand->mtd; + struct nand_chip *chip = &nand->chip; + + /* Request GPIO port. */ + gpio = JZ_GPIO_MEM_CS0 + bank - 1; + sprintf(gpio_name, "NAND CS%d", bank); + ret = gpio_request(gpio, gpio_name); + if (ret) { + dev_warn(&pdev->dev, + "Failed to request %s gpio %d: %d\n", + gpio_name, gpio, ret); + goto notfound_gpio; + } + + /* Request I/O resource. */ + sprintf(res_name, "bank%d", bank); + ret = jz_nand_ioremap_resource(pdev, res_name, + &nand->bank_mem[bank - 1], + &nand->bank_base[bank - 1]); + if (ret) + goto notfound_resource; + + /* Enable chip in bank. */ + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0); + ctrl = readl(nand->base + JZ_REG_NAND_CTRL); + ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1); + writel(ctrl, nand->base + JZ_REG_NAND_CTRL); + + if (chipnr == 0) { + /* Detect first chip. */ + ret = nand_scan_ident(mtd, 1, NULL); + if (ret) + goto notfound_id; + + /* Retrieve the IDs from the first chip. */ + chip->select_chip(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + *nand_maf_id = chip->read_byte(mtd); + *nand_dev_id = chip->read_byte(mtd); + } else { + /* Detect additional chip. */ + chip->select_chip(mtd, chipnr); + chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + if (*nand_maf_id != chip->read_byte(mtd) + || *nand_dev_id != chip->read_byte(mtd)) { + ret = -ENODEV; + goto notfound_id; + } + + /* Update size of the MTD. */ + chip->numchips++; + mtd->size += chip->chipsize; + } + + dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank); + return 0; + +notfound_id: + dev_info(&pdev->dev, "No chip found on bank %i\n", bank); + ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1)); + writel(ctrl, nand->base + JZ_REG_NAND_CTRL); + jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE); + jz_nand_iounmap_resource(nand->bank_mem[bank - 1], + nand->bank_base[bank - 1]); +notfound_resource: + gpio_free(gpio); +notfound_gpio: + return ret; +} + static int __devinit jz_nand_probe(struct platform_device *pdev) { int ret; @@ -295,6 +407,8 @@ static int __devinit jz_nand_probe(struct platform_device *pdev) struct nand_chip *chip; struct mtd_info *mtd; struct jz_nand_platform_data *pdata = pdev->dev.platform_data; + size_t chipnr, bank_idx; + uint8_t nand_maf_id = 0, nand_dev_id = 0; nand = kzalloc(sizeof(*nand), GFP_KERNEL); if (!nand) { @@ -305,10 +419,6 @@ static int __devinit jz_nand_probe(struct platform_device *pdev) ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base); if (ret) goto err_free; - ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem, - &nand->bank_base); - if (ret) - goto err_iounmap_mmio; if (pdata && gpio_is_valid(pdata->busy_gpio)) { ret = gpio_request(pdata->busy_gpio, "NAND busy pin"); @@ -316,7 +426,7 @@ static int __devinit jz_nand_probe(struct platform_device *pdev) dev_err(&pdev->dev, "Failed to request busy gpio %d: %d\n", pdata->busy_gpio, ret); - goto err_iounmap_mem; + goto err_iounmap_mmio; } } @@ -339,22 +449,51 @@ static int __devinit jz_nand_probe(struct platform_device *pdev) chip->chip_delay = 50; chip->cmd_ctrl = jz_nand_cmd_ctrl; + chip->select_chip = jz_nand_select_chip; if (pdata && gpio_is_valid(pdata->busy_gpio)) chip->dev_ready = jz_nand_dev_ready; - chip->IO_ADDR_R = nand->bank_base; - chip->IO_ADDR_W = nand->bank_base; - nand->pdata = pdata; platform_set_drvdata(pdev, nand); - writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL); - - ret = nand_scan_ident(mtd, 1, NULL); - if (ret) { - dev_err(&pdev->dev, "Failed to scan nand\n"); - goto err_gpio_free; + /* We are going to autodetect NAND chips in the banks specified in the + * platform data. Although nand_scan_ident() can detect multiple chips, + * it requires those chips to be numbered consecuitively, which is not + * always the case for external memory banks. And a fixed chip-to-bank + * mapping is not practical either, since for example Dingoo units + * produced at different times have NAND chips in different banks. + */ + chipnr = 0; + for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) { + unsigned char bank; + + /* If there is no platform data, look for NAND in bank 1, + * which is the most likely bank since it is the only one + * that can be booted from. + */ + bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1; + if (bank == 0) + break; + if (bank > JZ_NAND_NUM_BANKS) { + dev_warn(&pdev->dev, + "Skipping non-existing bank: %d\n", bank); + continue; + } + /* The detection routine will directly or indirectly call + * jz_nand_select_chip(), so nand->banks has to contain the + * bank we're checking. + */ + nand->banks[chipnr] = bank; + if (jz_nand_detect_bank(pdev, nand, bank, chipnr, + &nand_maf_id, &nand_dev_id) == 0) + chipnr++; + else + nand->banks[chipnr] = 0; + } + if (chipnr == 0) { + dev_err(&pdev->dev, "No NAND chips found\n"); + goto err_gpio_busy; } if (pdata && pdata->ident_callback) { @@ -364,8 +503,8 @@ static int __devinit jz_nand_probe(struct platform_device *pdev) ret = nand_scan_tail(mtd); if (ret) { - dev_err(&pdev->dev, "Failed to scan nand\n"); - goto err_gpio_free; + dev_err(&pdev->dev, "Failed to scan NAND\n"); + goto err_unclaim_banks; } ret = mtd_device_parse_register(mtd, NULL, NULL, @@ -382,14 +521,21 @@ static int __devinit jz_nand_probe(struct platform_device *pdev) return 0; err_nand_release: - nand_release(&nand->mtd); -err_gpio_free: + nand_release(mtd); +err_unclaim_banks: + while (chipnr--) { + unsigned char bank = nand->banks[chipnr]; + gpio_free(JZ_GPIO_MEM_CS0 + bank - 1); + jz_nand_iounmap_resource(nand->bank_mem[bank - 1], + nand->bank_base[bank - 1]); + } + writel(0, nand->base + JZ_REG_NAND_CTRL); +err_gpio_busy: + if (pdata && gpio_is_valid(pdata->busy_gpio)) + gpio_free(pdata->busy_gpio); platform_set_drvdata(pdev, NULL); - gpio_free(pdata->busy_gpio); -err_iounmap_mem: - iounmap(nand->bank_base); err_iounmap_mmio: - iounmap(nand->base); + jz_nand_iounmap_resource(nand->mem, nand->base); err_free: kfree(nand); return ret; @@ -398,16 +544,26 @@ static int __devinit jz_nand_probe(struct platform_device *pdev) static int __devexit jz_nand_remove(struct platform_device *pdev) { struct jz_nand *nand = platform_get_drvdata(pdev); + struct jz_nand_platform_data *pdata = pdev->dev.platform_data; + size_t i; nand_release(&nand->mtd); /* Deassert and disable all chips */ writel(0, nand->base + JZ_REG_NAND_CTRL); - iounmap(nand->bank_base); - release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem)); - iounmap(nand->base); - release_mem_region(nand->mem->start, resource_size(nand->mem)); + for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) { + unsigned char bank = nand->banks[i]; + if (bank != 0) { + jz_nand_iounmap_resource(nand->bank_mem[bank - 1], + nand->bank_base[bank - 1]); + gpio_free(JZ_GPIO_MEM_CS0 + bank - 1); + } + } + if (pdata && gpio_is_valid(pdata->busy_gpio)) + gpio_free(pdata->busy_gpio); + + jz_nand_iounmap_resource(nand->mem, nand->base); platform_set_drvdata(pdev, NULL); kfree(nand); diff --git a/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c b/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c index c42bbb16cdae..cd827ff4a021 100644 --- a/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c +++ b/trunk/drivers/net/ethernet/octeon/octeon_mgmt.c @@ -6,21 +6,19 @@ * Copyright (C) 2009 Cavium Networks */ -#include -#include -#include #include +#include +#include +#include #include +#include #include -#include +#include +#include #include -#include -#include -#include -#include #include #include -#include +#include #include #include @@ -60,56 +58,8 @@ union mgmt_port_ring_entry { } s; }; -#define MIX_ORING1 0x0 -#define MIX_ORING2 0x8 -#define MIX_IRING1 0x10 -#define MIX_IRING2 0x18 -#define MIX_CTL 0x20 -#define MIX_IRHWM 0x28 -#define MIX_IRCNT 0x30 -#define MIX_ORHWM 0x38 -#define MIX_ORCNT 0x40 -#define MIX_ISR 0x48 -#define MIX_INTENA 0x50 -#define MIX_REMCNT 0x58 -#define MIX_BIST 0x78 - -#define AGL_GMX_PRT_CFG 0x10 -#define AGL_GMX_RX_FRM_CTL 0x18 -#define AGL_GMX_RX_FRM_MAX 0x30 -#define AGL_GMX_RX_JABBER 0x38 -#define AGL_GMX_RX_STATS_CTL 0x50 - -#define AGL_GMX_RX_STATS_PKTS_DRP 0xb0 -#define AGL_GMX_RX_STATS_OCTS_DRP 0xb8 -#define AGL_GMX_RX_STATS_PKTS_BAD 0xc0 - -#define AGL_GMX_RX_ADR_CTL 0x100 -#define AGL_GMX_RX_ADR_CAM_EN 0x108 -#define AGL_GMX_RX_ADR_CAM0 0x180 -#define AGL_GMX_RX_ADR_CAM1 0x188 -#define AGL_GMX_RX_ADR_CAM2 0x190 -#define AGL_GMX_RX_ADR_CAM3 0x198 -#define AGL_GMX_RX_ADR_CAM4 0x1a0 -#define AGL_GMX_RX_ADR_CAM5 0x1a8 - -#define AGL_GMX_TX_STATS_CTL 0x268 -#define AGL_GMX_TX_CTL 0x270 -#define AGL_GMX_TX_STAT0 0x280 -#define AGL_GMX_TX_STAT1 0x288 -#define AGL_GMX_TX_STAT2 0x290 -#define AGL_GMX_TX_STAT3 0x298 -#define AGL_GMX_TX_STAT4 0x2a0 -#define AGL_GMX_TX_STAT5 0x2a8 -#define AGL_GMX_TX_STAT6 0x2b0 -#define AGL_GMX_TX_STAT7 0x2b8 -#define AGL_GMX_TX_STAT8 0x2c0 -#define AGL_GMX_TX_STAT9 0x2c8 - struct octeon_mgmt { struct net_device *netdev; - u64 mix; - u64 agl; int port; int irq; u64 *tx_ring; @@ -135,34 +85,31 @@ struct octeon_mgmt { struct napi_struct napi; struct tasklet_struct tx_clean_tasklet; struct phy_device *phydev; - struct device_node *phy_np; - resource_size_t mix_phys; - resource_size_t mix_size; - resource_size_t agl_phys; - resource_size_t agl_size; }; static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) { + int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); + mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); mix_intena.s.ithena = enable ? 1 : 0; - cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); + cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) { + int port = p->port; union cvmx_mixx_intena mix_intena; unsigned long flags; spin_lock_irqsave(&p->lock, flags); - mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA); + mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); mix_intena.s.othena = enable ? 1 : 0; - cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); + cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -199,6 +146,7 @@ static unsigned int ring_size_to_bytes(unsigned int ring_size) static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { unsigned int size; @@ -229,23 +177,24 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; p->rx_current_fill++; /* Ring the bell. */ - cvmx_write_csr(p->mix + MIX_IRING2, 1); + cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); } } static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) { + int port = p->port; union cvmx_mixx_orcnt mix_orcnt; union mgmt_port_ring_entry re; struct sk_buff *skb; int cleaned = 0; unsigned long flags; - mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); + mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); while (mix_orcnt.s.orcnt) { spin_lock_irqsave(&p->tx_list.lock, flags); - mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); + mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); if (mix_orcnt.s.orcnt == 0) { spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -265,7 +214,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) mix_orcnt.s.orcnt = 1; /* Acknowledge to hardware that we have the buffer. */ - cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64); + cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64); p->tx_current_fill--; spin_unlock_irqrestore(&p->tx_list.lock, flags); @@ -275,7 +224,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) dev_kfree_skb_any(skb); cleaned++; - mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT); + mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); } if (cleaned && netif_queue_stopped(p->netdev)) @@ -292,12 +241,13 @@ static void octeon_mgmt_clean_tx_tasklet(unsigned long arg) static void octeon_mgmt_update_rx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; unsigned long flags; u64 drop, bad; /* These reads also clear the count registers. */ - drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP); - bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD); + drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port)); + bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port)); if (drop || bad) { /* Do an atomic update. */ @@ -311,14 +261,15 @@ static void octeon_mgmt_update_rx_stats(struct net_device *netdev) static void octeon_mgmt_update_tx_stats(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; unsigned long flags; union cvmx_agl_gmx_txx_stat0 s0; union cvmx_agl_gmx_txx_stat1 s1; /* These reads also clear the count registers. */ - s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0); - s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1); + s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port)); + s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port)); if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { /* Do an atomic update. */ @@ -357,6 +308,7 @@ static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p, static int octeon_mgmt_receive_one(struct octeon_mgmt *p) { + int port = p->port; struct net_device *netdev = p->netdev; union cvmx_mixx_ircnt mix_ircnt; union mgmt_port_ring_entry re; @@ -429,17 +381,18 @@ static int octeon_mgmt_receive_one(struct octeon_mgmt *p) /* Tell the hardware we processed a packet. */ mix_ircnt.u64 = 0; mix_ircnt.s.ircnt = 1; - cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64); + cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64); return rc; } static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) { + int port = p->port; unsigned int work_done = 0; union cvmx_mixx_ircnt mix_ircnt; int rc; - mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); + mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); while (work_done < budget && mix_ircnt.s.ircnt) { rc = octeon_mgmt_receive_one(p); @@ -447,7 +400,7 @@ static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) work_done++; /* Check for more packets. */ - mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT); + mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); } octeon_mgmt_rx_fill_ring(p->netdev); @@ -481,16 +434,16 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p) union cvmx_agl_gmx_bist agl_gmx_bist; mix_ctl.u64 = 0; - cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); + cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); + mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port)); } while (mix_ctl.s.busy); mix_ctl.s.reset = 1; - cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); - cvmx_read_csr(p->mix + MIX_CTL); + cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); + cvmx_read_csr(CVMX_MIXX_CTL(p->port)); cvmx_wait(64); - mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST); + mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port)); if (mix_bist.u64) dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", (unsigned long long)mix_bist.u64); @@ -521,6 +474,7 @@ static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs, static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; unsigned long flags; @@ -566,29 +520,29 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) spin_lock_irqsave(&p->lock, flags); /* Disable packet I/O. */ - agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); prev_packet_enable = agl_gmx_prtx.s.en; agl_gmx_prtx.s.en = 0; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); + cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); adr_ctl.u64 = 0; adr_ctl.s.cam_mode = cam_mode; adr_ctl.s.mcst = multicast_mode; adr_ctl.s.bcst = 1; /* Allow broadcast */ - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64); - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]); - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]); - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]); - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]); - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]); - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]); - cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]); + cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask); /* Restore packet I/O. */ agl_gmx_prtx.s.en = prev_packet_enable; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64); + cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); spin_unlock_irqrestore(&p->lock, flags); } @@ -610,6 +564,7 @@ static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr) static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; /* @@ -625,8 +580,8 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) netdev->mtu = new_mtu; - cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs); - cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER, + cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs); + cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), (size_without_fcs + 7) & 0xfff8); return 0; @@ -636,13 +591,14 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id) { struct net_device *netdev = dev_id; struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; union cvmx_mixx_isr mixx_isr; - mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR); + mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port)); /* Clear any pending interrupts */ - cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64); - cvmx_read_csr(p->mix + MIX_ISR); + cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64); + cvmx_read_csr(CVMX_MIXX_ISR(port)); if (mixx_isr.s.irthresh) { octeon_mgmt_disable_rx_irq(p); @@ -673,6 +629,7 @@ static int octeon_mgmt_ioctl(struct net_device *netdev, static void octeon_mgmt_adjust_link(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; union cvmx_agl_gmx_prtx_cfg prtx_cfg; unsigned long flags; int link_changed = 0; @@ -683,9 +640,11 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) link_changed = 1; if (p->last_duplex != p->phydev->duplex) { p->last_duplex = p->phydev->duplex; - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.u64 = + cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); prtx_cfg.s.duplex = p->phydev->duplex; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), + prtx_cfg.u64); } } else { if (p->last_link) @@ -711,16 +670,18 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev) static int octeon_mgmt_init_phy(struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + char phy_id[MII_BUS_ID_SIZE + 3]; - if (octeon_is_simulation() || p->phy_np == NULL) { + if (octeon_is_simulation()) { /* No PHYs in the simulator. */ netif_carrier_on(netdev); return 0; } - p->phydev = of_phy_connect(netdev, p->phy_np, - octeon_mgmt_adjust_link, 0, - PHY_INTERFACE_MODE_MII); + snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", p->port); + + p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0, + PHY_INTERFACE_MODE_MII); if (IS_ERR(p->phydev)) { p->phydev = NULL; @@ -776,14 +737,14 @@ static int octeon_mgmt_open(struct net_device *netdev) octeon_mgmt_reset_hw(p); - mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); + mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); /* Bring it out of reset if needed. */ if (mix_ctl.s.reset) { mix_ctl.s.reset = 0; - cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); + cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); do { - mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL); + mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); } while (mix_ctl.s.reset); } @@ -794,17 +755,17 @@ static int octeon_mgmt_open(struct net_device *netdev) oring1.u64 = 0; oring1.s.obase = p->tx_ring_handle >> 3; oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; - cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64); + cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); iring1.u64 = 0; iring1.s.ibase = p->rx_ring_handle >> 3; iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; - cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64); + cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64); /* Disable packet I/O. */ - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); prtx_cfg.s.en = 0; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); octeon_mgmt_set_mac_address(netdev, &sa); @@ -821,7 +782,7 @@ static int octeon_mgmt_open(struct net_device *netdev) mix_ctl.s.nbtarb = 0; /* Arbitration mode */ /* MII CB-request FIFO programmable high watermark */ mix_ctl.s.mrq_hwm = 1; - cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64); + cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { @@ -848,16 +809,16 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Clear statistics. */ /* Clear on read. */ - cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1); - cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0); - cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0); + cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1); + cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0); + cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0); - cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1); - cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0); - cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0); + cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1); + cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0); + cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0); /* Clear any pending interrupts */ - cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR)); + cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port))); if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, netdev)) { @@ -868,18 +829,18 @@ static int octeon_mgmt_open(struct net_device *netdev) /* Interrupt every single RX packet */ mix_irhwm.u64 = 0; mix_irhwm.s.irhwm = 0; - cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64); + cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64); /* Interrupt when we have 1 or more packets to clean. */ mix_orhwm.u64 = 0; mix_orhwm.s.orhwm = 1; - cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64); + cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64); /* Enable receive and transmit interrupts */ mix_intena.u64 = 0; mix_intena.s.ithena = 1; mix_intena.s.othena = 1; - cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64); + cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); /* Enable packet I/O. */ @@ -910,7 +871,7 @@ static int octeon_mgmt_open(struct net_device *netdev) * frame. GMX checks that the PREAMBLE is sent correctly. */ rxx_frm_ctl.s.pre_chk = 1; - cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64); + cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); /* Enable the AGL block */ agl_gmx_inf_mode.u64 = 0; @@ -918,13 +879,13 @@ static int octeon_mgmt_open(struct net_device *netdev) cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); /* Configure the port duplex and enables */ - prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG); + prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); prtx_cfg.s.tx_en = 1; prtx_cfg.s.rx_en = 1; prtx_cfg.s.en = 1; p->last_duplex = 1; prtx_cfg.s.duplex = p->last_duplex; - cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64); + cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); p->last_link = 0; netif_carrier_off(netdev); @@ -988,6 +949,7 @@ static int octeon_mgmt_stop(struct net_device *netdev) static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) { struct octeon_mgmt *p = netdev_priv(netdev); + int port = p->port; union mgmt_port_ring_entry re; unsigned long flags; int rv = NETDEV_TX_BUSY; @@ -1031,7 +993,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) netdev->stats.tx_bytes += skb->len; /* Ring the bell. */ - cvmx_write_csr(p->mix + MIX_ORING2, 1); + cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); rv = NETDEV_TX_OK; out: @@ -1109,14 +1071,10 @@ static const struct net_device_ops octeon_mgmt_ops = { static int __devinit octeon_mgmt_probe(struct platform_device *pdev) { + struct resource *res_irq; struct net_device *netdev; struct octeon_mgmt *p; - const __be32 *data; - const u8 *mac; - struct resource *res_mix; - struct resource *res_agl; - int len; - int result; + int i; netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); if (netdev == NULL) @@ -1130,63 +1088,14 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) p->netdev = netdev; p->dev = &pdev->dev; - data = of_get_property(pdev->dev.of_node, "cell-index", &len); - if (data && len == sizeof(*data)) { - p->port = be32_to_cpup(data); - } else { - dev_err(&pdev->dev, "no 'cell-index' property\n"); - result = -ENXIO; - goto err; - } - + p->port = pdev->id; snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); - result = platform_get_irq(pdev, 0); - if (result < 0) - goto err; - - p->irq = result; - - res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res_mix == NULL) { - dev_err(&pdev->dev, "no 'reg' resource\n"); - result = -ENXIO; - goto err; - } - - res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res_agl == NULL) { - dev_err(&pdev->dev, "no 'reg' resource\n"); - result = -ENXIO; - goto err; - } - - p->mix_phys = res_mix->start; - p->mix_size = resource_size(res_mix); - p->agl_phys = res_agl->start; - p->agl_size = resource_size(res_agl); - - - if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size, - res_mix->name)) { - dev_err(&pdev->dev, "request_mem_region (%s) failed\n", - res_mix->name); - result = -ENXIO; - goto err; - } - - if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size, - res_agl->name)) { - result = -ENXIO; - dev_err(&pdev->dev, "request_mem_region (%s) failed\n", - res_agl->name); + res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res_irq) goto err; - } - - - p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size); - p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size); + p->irq = res_irq->start; spin_lock_init(&p->lock); skb_queue_head_init(&p->tx_list); @@ -1199,26 +1108,24 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev) netdev->netdev_ops = &octeon_mgmt_ops; netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; - mac = of_get_mac_address(pdev->dev.of_node); - - if (mac) - memcpy(netdev->dev_addr, mac, 6); - - p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0); + /* The mgmt ports get the first N MACs. */ + for (i = 0; i < 6; i++) + netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i]; + netdev->dev_addr[5] += p->port; - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64); - pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; + if (p->port >= octeon_bootinfo->mac_addr_count) + dev_err(&pdev->dev, + "Error %s: Using MAC outside of the assigned range: %pM\n", + netdev->name, netdev->dev_addr); - result = register_netdev(netdev); - if (result) + if (register_netdev(netdev)) goto err; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; - err: free_netdev(netdev); - return result; + return -ENOENT; } static int __devexit octeon_mgmt_remove(struct platform_device *pdev) @@ -1230,19 +1137,10 @@ static int __devexit octeon_mgmt_remove(struct platform_device *pdev) return 0; } -static struct of_device_id octeon_mgmt_match[] = { - { - .compatible = "cavium,octeon-5750-mix", - }, - {}, -}; -MODULE_DEVICE_TABLE(of, octeon_mgmt_match); - static struct platform_driver octeon_mgmt_driver = { .driver = { .name = "octeon_mgmt", .owner = THIS_MODULE, - .of_match_table = octeon_mgmt_match, }, .probe = octeon_mgmt_probe, .remove = __devexit_p(octeon_mgmt_remove), diff --git a/trunk/drivers/net/phy/mdio-octeon.c b/trunk/drivers/net/phy/mdio-octeon.c index d4015aa663e6..826d961f39f7 100644 --- a/trunk/drivers/net/phy/mdio-octeon.c +++ b/trunk/drivers/net/phy/mdio-octeon.c @@ -3,17 +3,14 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2009,2011 Cavium, Inc. + * Copyright (C) 2009 Cavium Networks */ -#include -#include -#include -#include -#include #include +#include +#include +#include #include -#include #include #include @@ -21,17 +18,9 @@ #define DRV_VERSION "1.0" #define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver" -#define SMI_CMD 0x0 -#define SMI_WR_DAT 0x8 -#define SMI_RD_DAT 0x10 -#define SMI_CLK 0x18 -#define SMI_EN 0x20 - struct octeon_mdiobus { struct mii_bus *mii_bus; - u64 register_base; - resource_size_t mdio_phys; - resource_size_t regsize; + int unit; int phy_irq[PHY_MAX_ADDR]; }; @@ -46,15 +35,15 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum) smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); + cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - __delay(1000); - smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT); + cvmx_wait(1000); + smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit)); } while (smi_rd.s.pending && --timeout); if (smi_rd.s.val) @@ -73,21 +62,21 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, smi_wr.u64 = 0; smi_wr.s.dat = val; - cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64); + cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64); smi_cmd.u64 = 0; smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); + cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); do { /* * Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ - __delay(1000); - smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT); + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit)); } while (smi_wr.s.pending && --timeout); if (timeout <= 0) @@ -99,44 +88,38 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) { struct octeon_mdiobus *bus; - struct resource *res_mem; union cvmx_smix_en smi_en; + int i; int err = -ENOENT; bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); if (!bus) return -ENOMEM; - res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - - if (res_mem == NULL) { - dev_err(&pdev->dev, "found no memory resource\n"); - err = -ENXIO; - goto fail; - } - bus->mdio_phys = res_mem->start; - bus->regsize = resource_size(res_mem); - if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize, - res_mem->name)) { - dev_err(&pdev->dev, "request_mem_region failed\n"); - goto fail; - } - bus->register_base = - (u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize); + /* The platform_device id is our unit number. */ + bus->unit = pdev->id; bus->mii_bus = mdiobus_alloc(); if (!bus->mii_bus) - goto fail; + goto err; smi_en.u64 = 0; smi_en.s.en = 1; - cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); + + /* + * Standard Octeon evaluation boards don't support phy + * interrupts, we need to poll. + */ + for (i = 0; i < PHY_MAX_ADDR; i++) + bus->phy_irq[i] = PHY_POLL; bus->mii_bus->priv = bus; bus->mii_bus->irq = bus->phy_irq; bus->mii_bus->name = "mdio-octeon"; - snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base); + snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + bus->mii_bus->name, bus->unit); bus->mii_bus->parent = &pdev->dev; bus->mii_bus->read = octeon_mdiobus_read; @@ -144,18 +127,20 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, bus); - err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node); + err = mdiobus_register(bus->mii_bus); if (err) - goto fail_register; + goto err_register; dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); return 0; -fail_register: +err_register: mdiobus_free(bus->mii_bus); -fail: + +err: + devm_kfree(&pdev->dev, bus); smi_en.u64 = 0; - cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); return err; } @@ -169,23 +154,14 @@ static int __devexit octeon_mdiobus_remove(struct platform_device *pdev) mdiobus_unregister(bus->mii_bus); mdiobus_free(bus->mii_bus); smi_en.u64 = 0; - cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); return 0; } -static struct of_device_id octeon_mdiobus_match[] = { - { - .compatible = "cavium,octeon-3860-mdio", - }, - {}, -}; -MODULE_DEVICE_TABLE(of, octeon_mdiobus_match); - static struct platform_driver octeon_mdiobus_driver = { .driver = { .name = "mdio-octeon", .owner = THIS_MODULE, - .of_match_table = octeon_mdiobus_match, }, .probe = octeon_mdiobus_probe, .remove = __devexit_p(octeon_mdiobus_remove), diff --git a/trunk/drivers/staging/octeon/ethernet-mdio.c b/trunk/drivers/staging/octeon/ethernet-mdio.c index f15b31b37ca5..e31949c9c87e 100644 --- a/trunk/drivers/staging/octeon/ethernet-mdio.c +++ b/trunk/drivers/staging/octeon/ethernet-mdio.c @@ -28,7 +28,6 @@ #include #include #include -#include #include @@ -162,23 +161,22 @@ static void cvm_oct_adjust_link(struct net_device *dev) int cvm_oct_phy_setup_device(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); - struct device_node *phy_node; - if (!priv->of_node) - return 0; + int phy_addr = cvmx_helper_board_get_mii_address(priv->port); + if (phy_addr != -1) { + char phy_id[MII_BUS_ID_SIZE + 3]; - phy_node = of_parse_phandle(priv->of_node, "phy-handle", 0); - if (!phy_node) - return 0; + snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", phy_addr); - priv->phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0, - PHY_INTERFACE_MODE_GMII); - - if (priv->phydev == NULL) - return -ENODEV; - - priv->last_link = 0; - phy_start_aneg(priv->phydev); + priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, + PHY_INTERFACE_MODE_GMII); + if (IS_ERR(priv->phydev)) { + priv->phydev = NULL; + return -1; + } + priv->last_link = 0; + phy_start_aneg(priv->phydev); + } return 0; } diff --git a/trunk/drivers/staging/octeon/ethernet.c b/trunk/drivers/staging/octeon/ethernet.c index 683bedc74dde..18f7a790f73d 100644 --- a/trunk/drivers/staging/octeon/ethernet.c +++ b/trunk/drivers/staging/octeon/ethernet.c @@ -24,7 +24,6 @@ * This file may also be available under a different license from Cavium. * Contact Cavium Networks for more information **********************************************************************/ -#include #include #include #include @@ -33,7 +32,6 @@ #include #include #include -#include #include @@ -115,6 +113,15 @@ int rx_napi_weight = 32; module_param(rx_napi_weight, int, 0444); MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); +/* + * The offset from mac_addr_base that should be used for the next port + * that is configured. By convention, if any mgmt ports exist on the + * chip, they get the first mac addresses, The ports controlled by + * this driver are numbered sequencially following any mgmt addresses + * that may exist. + */ +static unsigned int cvm_oct_mac_addr_offset; + /** * cvm_oct_poll_queue - Workqueue for polling operations. */ @@ -169,7 +176,7 @@ static void cvm_oct_periodic_worker(struct work_struct *work) queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ); } -static __devinit void cvm_oct_configure_common_hw(void) +static __init void cvm_oct_configure_common_hw(void) { /* Setup the FPA */ cvmx_fpa_enable(); @@ -389,21 +396,23 @@ static void cvm_oct_common_set_multicast_list(struct net_device *dev) * Returns Zero on success */ -static int cvm_oct_set_mac_filter(struct net_device *dev) +static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) { struct octeon_ethernet *priv = netdev_priv(dev); union cvmx_gmxx_prtx_cfg gmx_cfg; int interface = INTERFACE(priv->port); int index = INDEX(priv->port); + memcpy(dev->dev_addr, addr + 2, 6); + if ((interface < 2) && (cvmx_helper_interface_get_mode(interface) != CVMX_HELPER_INTERFACE_MODE_SPI)) { int i; - uint8_t *ptr = dev->dev_addr; + uint8_t *ptr = addr; uint64_t mac = 0; for (i = 0; i < 6; i++) - mac = (mac << 8) | (uint64_t)ptr[i]; + mac = (mac << 8) | (uint64_t) (ptr[i + 2]); gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); @@ -412,17 +421,17 @@ static int cvm_oct_set_mac_filter(struct net_device *dev) cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), - ptr[0]); + ptr[2]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), - ptr[1]); + ptr[3]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), - ptr[2]); + ptr[4]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), - ptr[3]); + ptr[5]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), - ptr[4]); + ptr[6]); cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), - ptr[5]); + ptr[7]); cvm_oct_common_set_multicast_list(dev); cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); @@ -430,15 +439,6 @@ static int cvm_oct_set_mac_filter(struct net_device *dev) return 0; } -static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) -{ - int r = eth_mac_addr(dev, addr); - - if (r) - return r; - return cvm_oct_set_mac_filter(dev); -} - /** * cvm_oct_common_init - per network device initialization * @dev: Device to initialize @@ -448,17 +448,26 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) int cvm_oct_common_init(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); - const u8 *mac = NULL; - - if (priv->of_node) - mac = of_get_mac_address(priv->of_node); - - if (mac && is_valid_ether_addr(mac)) { - memcpy(dev->dev_addr, mac, ETH_ALEN); - dev->addr_assign_type &= ~NET_ADDR_RANDOM; - } else { - eth_hw_addr_random(dev); - } + struct sockaddr sa; + u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) | + ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) | + ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) | + ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) | + ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) | + (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff); + + mac += cvm_oct_mac_addr_offset; + sa.sa_data[0] = (mac >> 40) & 0xff; + sa.sa_data[1] = (mac >> 32) & 0xff; + sa.sa_data[2] = (mac >> 24) & 0xff; + sa.sa_data[3] = (mac >> 16) & 0xff; + sa.sa_data[4] = (mac >> 8) & 0xff; + sa.sa_data[5] = mac & 0xff; + + if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count) + printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:" + " %pM\n", dev->name, sa.sa_data); + cvm_oct_mac_addr_offset++; /* * Force the interface to use the POW send if always_use_pow @@ -479,7 +488,7 @@ int cvm_oct_common_init(struct net_device *dev) SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops); cvm_oct_phy_setup_device(dev); - cvm_oct_set_mac_filter(dev); + dev->netdev_ops->ndo_set_mac_address(dev, &sa); dev->netdev_ops->ndo_change_mtu(dev, dev->mtu); /* @@ -586,55 +595,22 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = { extern void octeon_mdiobus_force_mod_depencency(void); -static struct device_node * __devinit cvm_oct_of_get_child(const struct device_node *parent, - int reg_val) -{ - struct device_node *node = NULL; - int size; - const __be32 *addr; - - for (;;) { - node = of_get_next_child(parent, node); - if (!node) - break; - addr = of_get_property(node, "reg", &size); - if (addr && (be32_to_cpu(*addr) == reg_val)) - break; - } - return node; -} - -static struct device_node * __devinit cvm_oct_node_for_port(struct device_node *pip, - int interface, int port) -{ - struct device_node *ni, *np; - - ni = cvm_oct_of_get_child(pip, interface); - if (!ni) - return NULL; - - np = cvm_oct_of_get_child(ni, port); - of_node_put(ni); - - return np; -} - -static int __devinit cvm_oct_probe(struct platform_device *pdev) +static int __init cvm_oct_init_module(void) { int num_interfaces; int interface; int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; int qos; - struct device_node *pip; octeon_mdiobus_force_mod_depencency(); pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); - pip = pdev->dev.of_node; - if (!pip) { - pr_err("Error: No 'pip' in /aliases\n"); - return -EINVAL; - } + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) + cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */ + else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) + cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */ + else + cvm_oct_mac_addr_offset = 0; cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet"); if (cvm_oct_poll_queue == NULL) { @@ -713,11 +689,10 @@ static int __devinit cvm_oct_probe(struct platform_device *pdev) cvmx_helper_interface_get_mode(interface); int num_ports = cvmx_helper_ports_on_interface(interface); int port; - int port_index; - for (port_index = 0, port = cvmx_helper_get_ipd_port(interface, 0); + for (port = cvmx_helper_get_ipd_port(interface, 0); port < cvmx_helper_get_ipd_port(interface, num_ports); - port_index++, port++) { + port++) { struct octeon_ethernet *priv; struct net_device *dev = alloc_etherdev(sizeof(struct octeon_ethernet)); @@ -728,7 +703,6 @@ static int __devinit cvm_oct_probe(struct platform_device *pdev) /* Initialize the device private structure. */ priv = netdev_priv(dev); - priv->of_node = cvm_oct_node_for_port(pip, interface, port_index); INIT_DELAYED_WORK(&priv->port_periodic_work, cvm_oct_periodic_worker); @@ -813,7 +787,7 @@ static int __devinit cvm_oct_probe(struct platform_device *pdev) return 0; } -static int __devexit cvm_oct_remove(struct platform_device *pdev) +static void __exit cvm_oct_cleanup_module(void) { int port; @@ -861,29 +835,10 @@ static int __devexit cvm_oct_remove(struct platform_device *pdev) if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL) cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL, CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128); - return 0; } -static struct of_device_id cvm_oct_match[] = { - { - .compatible = "cavium,octeon-3860-pip", - }, - {}, -}; -MODULE_DEVICE_TABLE(of, cvm_oct_match); - -static struct platform_driver cvm_oct_driver = { - .probe = cvm_oct_probe, - .remove = __devexit_p(cvm_oct_remove), - .driver = { - .owner = THIS_MODULE, - .name = KBUILD_MODNAME, - .of_match_table = cvm_oct_match, - }, -}; - -module_platform_driver(cvm_oct_driver); - MODULE_LICENSE("GPL"); MODULE_AUTHOR("Cavium Networks "); MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver."); +module_init(cvm_oct_init_module); +module_exit(cvm_oct_cleanup_module); diff --git a/trunk/drivers/staging/octeon/octeon-ethernet.h b/trunk/drivers/staging/octeon/octeon-ethernet.h index 9360e22e0739..d58192563552 100644 --- a/trunk/drivers/staging/octeon/octeon-ethernet.h +++ b/trunk/drivers/staging/octeon/octeon-ethernet.h @@ -31,8 +31,6 @@ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H -#include - /** * This is the definition of the Ethernet driver's private * driver state stored in netdev_priv(dev). @@ -61,7 +59,6 @@ struct octeon_ethernet { void (*poll) (struct net_device *dev); struct delayed_work port_periodic_work; struct work_struct port_work; /* may be unused. */ - struct device_node *of_node; }; int cvm_oct_free_work(void *work_queue_entry); diff --git a/trunk/include/linux/libfdt.h b/trunk/include/linux/libfdt.h deleted file mode 100644 index 4c0306c69b4e..000000000000 --- a/trunk/include/linux/libfdt.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _INCLUDE_LIBFDT_H_ -#define _INCLUDE_LIBFDT_H_ - -#include -#include "../../scripts/dtc/libfdt/fdt.h" -#include "../../scripts/dtc/libfdt/libfdt.h" - -#endif /* _INCLUDE_LIBFDT_H_ */ diff --git a/trunk/include/linux/libfdt_env.h b/trunk/include/linux/libfdt_env.h deleted file mode 100644 index 01508c7b8c81..000000000000 --- a/trunk/include/linux/libfdt_env.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _LIBFDT_ENV_H -#define _LIBFDT_ENV_H - -#include - -#include - -#define fdt32_to_cpu(x) be32_to_cpu(x) -#define cpu_to_fdt32(x) cpu_to_be32(x) -#define fdt64_to_cpu(x) be64_to_cpu(x) -#define cpu_to_fdt64(x) cpu_to_be64(x) - -#endif /* _LIBFDT_ENV_H */ diff --git a/trunk/lib/Kconfig b/trunk/lib/Kconfig index e091300b2045..a9e15403434e 100644 --- a/trunk/lib/Kconfig +++ b/trunk/lib/Kconfig @@ -395,10 +395,4 @@ config SIGNATURE Digital signature verification. Currently only RSA is supported. Implementation is done using GnuPG MPI library -# -# libfdt files, only selected if needed. -# -config LIBFDT - bool - endmenu diff --git a/trunk/lib/Makefile b/trunk/lib/Makefile index 2f2be5a8734c..8c31a0cb75e9 100644 --- a/trunk/lib/Makefile +++ b/trunk/lib/Makefile @@ -130,11 +130,6 @@ obj-$(CONFIG_GENERIC_STRNLEN_USER) += strnlen_user.o obj-$(CONFIG_STMP_DEVICE) += stmp_device.o -libfdt_files = fdt.o fdt_ro.o fdt_wip.o fdt_rw.o fdt_sw.o fdt_strerror.o -$(foreach file, $(libfdt_files), \ - $(eval CFLAGS_$(file) = -I$(src)/../scripts/dtc/libfdt)) -lib-$(CONFIG_LIBFDT) += $(libfdt_files) - hostprogs-y := gen_crc32table clean-files := crc32table.h diff --git a/trunk/lib/fdt.c b/trunk/lib/fdt.c deleted file mode 100644 index 97f20069fc37..000000000000 --- a/trunk/lib/fdt.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../scripts/dtc/libfdt/fdt.c" diff --git a/trunk/lib/fdt_ro.c b/trunk/lib/fdt_ro.c deleted file mode 100644 index f73c04ea7be4..000000000000 --- a/trunk/lib/fdt_ro.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../scripts/dtc/libfdt/fdt_ro.c" diff --git a/trunk/lib/fdt_rw.c b/trunk/lib/fdt_rw.c deleted file mode 100644 index 0c1f0f4a4b13..000000000000 --- a/trunk/lib/fdt_rw.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../scripts/dtc/libfdt/fdt_rw.c" diff --git a/trunk/lib/fdt_strerror.c b/trunk/lib/fdt_strerror.c deleted file mode 100644 index 8713e3ff4707..000000000000 --- a/trunk/lib/fdt_strerror.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../scripts/dtc/libfdt/fdt_strerror.c" diff --git a/trunk/lib/fdt_sw.c b/trunk/lib/fdt_sw.c deleted file mode 100644 index 9ac7e50c76ce..000000000000 --- a/trunk/lib/fdt_sw.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../scripts/dtc/libfdt/fdt_sw.c" diff --git a/trunk/lib/fdt_wip.c b/trunk/lib/fdt_wip.c deleted file mode 100644 index 45b3fc3d3ba1..000000000000 --- a/trunk/lib/fdt_wip.c +++ /dev/null @@ -1,2 +0,0 @@ -#include -#include "../scripts/dtc/libfdt/fdt_wip.c"