From 6c476b8680fc5a81f64708b2271a6ab2bf97e23d Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 18 Oct 2012 10:15:30 +0200 Subject: [PATCH] --- yaml --- r: 345157 b: refs/heads/master c: a7c9655fdd89fae1749c2e5beadae8b7d32093af h: refs/heads/master i: 345155: 2e529c149c0a524a86749d6da4865bda0861d9b5 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_dp.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 2cb329b5d742..5c660fb9e7cc 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1a644cd47ca0c40a9210db170bd0630031c3a60b +refs/heads/master: a7c9655fdd89fae1749c2e5beadae8b7d32093af diff --git a/trunk/drivers/gpu/drm/i915/intel_dp.c b/trunk/drivers/gpu/drm/i915/intel_dp.c index cd23ffadfda1..3cb180e38ca1 100644 --- a/trunk/drivers/gpu/drm/i915/intel_dp.c +++ b/trunk/drivers/gpu/drm/i915/intel_dp.c @@ -1821,13 +1821,13 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels); + /* Set training pattern 1 */ if (!intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE)) break; - /* Set training pattern 1 */ - udelay(100); + drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); if (!intel_dp_get_link_status(intel_dp, link_status)) { DRM_ERROR("failed to get link status\n"); break; @@ -1910,7 +1910,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp) DP_LINK_SCRAMBLING_DISABLE)) break; - udelay(400); + drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); if (!intel_dp_get_link_status(intel_dp, link_status)) break;