diff --git a/[refs] b/[refs] index 3186b058dcb8..cf61d9151a8a 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fcae8e098877b798c365fd9d807f86d5e2a2b324 +refs/heads/master: f62c3f2c35874713ebbb6b6a4b9d9c6caaed4f14 diff --git a/trunk/arch/arm/boot/compressed/.gitignore b/trunk/arch/arm/boot/compressed/.gitignore index b15f927a5926..aefee20cbf98 100644 --- a/trunk/arch/arm/boot/compressed/.gitignore +++ b/trunk/arch/arm/boot/compressed/.gitignore @@ -1,2 +1 @@ piggy.gz -font.c diff --git a/trunk/arch/arm/boot/compressed/Makefile b/trunk/arch/arm/boot/compressed/Makefile index a1f1691b67fe..adddc7131685 100644 --- a/trunk/arch/arm/boot/compressed/Makefile +++ b/trunk/arch/arm/boot/compressed/Makefile @@ -6,13 +6,15 @@ HEAD = head.o OBJS = misc.o -FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c +FONTC = drivers/video/console/font_acorn_8x8.c + +FONT = $(addprefix ../../../../drivers/video/console/, font_acorn_8x8.o) # # Architecture dependencies # ifeq ($(CONFIG_ARCH_ACORN),y) -OBJS += ll_char_wr.o font.o +OBJS += ll_char_wr.o $(FONT) endif ifeq ($(CONFIG_ARCH_SHARK),y) @@ -71,7 +73,7 @@ endif SEDFLAGS = s/TEXT_START/$(ZTEXTADDR)/;s/BSS_START/$(ZBSSADDR)/ -targets := vmlinux vmlinux.lds piggy.gz piggy.o font.o font.c \ +targets := vmlinux vmlinux.lds piggy.gz piggy.o $(FONT) \ head.o misc.o $(OBJS) EXTRA_CFLAGS := -fpic EXTRA_AFLAGS := @@ -103,10 +105,7 @@ $(obj)/piggy.gz: $(obj)/../Image FORCE $(obj)/piggy.o: $(obj)/piggy.gz FORCE -CFLAGS_font.o := -Dstatic= - -$(obj)/font.c: $(FONTC) - $(call cmd,shipped) +CFLAGS_font_acorn_8x8.o := -Dstatic= $(obj)/vmlinux.lds: $(obj)/vmlinux.lds.in arch/arm/boot/Makefile .config @sed "$(SEDFLAGS)" < $< > $@ diff --git a/trunk/arch/arm/boot/compressed/head.S b/trunk/arch/arm/boot/compressed/head.S index d7fb5ee1637e..680ea6ed77b8 100644 --- a/trunk/arch/arm/boot/compressed/head.S +++ b/trunk/arch/arm/boot/compressed/head.S @@ -436,28 +436,6 @@ __armv4_mmu_cache_on: mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs mov pc, r12 -__armv7_mmu_cache_on: - mov r12, lr - mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 - tst r11, #0xf @ VMSA - blne __setup_mmu - mov r0, #0 - mcr p15, 0, r0, c7, c10, 4 @ drain write buffer - tst r11, #0xf @ VMSA - mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs - mrc p15, 0, r0, c1, c0, 0 @ read control reg - orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement - orr r0, r0, #0x003c @ write buffer - orrne r0, r0, #1 @ MMU enabled - movne r1, #-1 - mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer - mcrne p15, 0, r1, c3, c0, 0 @ load domain access control - mcr p15, 0, r0, c1, c0, 0 @ load control register - mrc p15, 0, r0, c1, c0, 0 @ and read it back - mov r0, #0 - mcr p15, 0, r0, c7, c5, 4 @ ISB - mov pc, r12 - __arm6_mmu_cache_on: mov r12, lr bl __setup_mmu @@ -644,17 +622,11 @@ proc_types: b __armv4_mmu_cache_flush .word 0x0007b000 @ ARMv6 - .word 0x000ff000 + .word 0x0007f000 b __armv4_mmu_cache_on b __armv4_mmu_cache_off b __armv6_mmu_cache_flush - .word 0x000f0000 @ new CPU Id - .word 0x000f0000 - b __armv7_mmu_cache_on - b __armv7_mmu_cache_off - b __armv7_mmu_cache_flush - .word 0 @ unrecognised type .word 0 mov pc, lr @@ -702,16 +674,6 @@ __armv4_mmu_cache_off: mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 mov pc, lr -__armv7_mmu_cache_off: - mrc p15, 0, r0, c1, c0 - bic r0, r0, #0x000d - mcr p15, 0, r0, c1, c0 @ turn MMU and cache off - mov r12, lr - bl __armv7_mmu_cache_flush - mov r0, #0 - mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB - mov pc, r12 - __arm6_mmu_cache_off: mov r0, #0x00000030 @ ARM6 control reg. b __armv3_mmu_cache_off @@ -768,59 +730,6 @@ __armv6_mmu_cache_flush: mcr p15, 0, r1, c7, c10, 4 @ drain WB mov pc, lr -__armv7_mmu_cache_flush: - mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 - tst r10, #0xf << 16 @ hierarchical cache (ARMv7) - beq hierarchical - mov r10, #0 - mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D - b iflush -hierarchical: - stmfd sp!, {r0-r5, r7, r9-r11} - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished @ if loc is 0, then no need to clean - mov r10, #0 @ start clean at cache level 0 -loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache level - mov r1, r0, lsr r2 @ extract cache type bits from clidr - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the way size - .word 0xe16f5f14 @ clz r5, r4 - find bit position of way size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the index size -loop2: - mov r9, r4 @ create working copy of max way size -loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge loop3 - subs r7, r7, #1 @ decrement the index - bge loop2 -skip: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt loop1 -finished: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - ldmfd sp!, {r0-r5, r7, r9-r11} -iflush: - mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB - mcr p15, 0, r10, c7, c10, 4 @ drain WB - mov pc, lr - __armv4_mmu_cache_flush: mov r2, #64*1024 @ default: 32K dcache size (*2) mov r11, #32 @ default: 32 byte line size diff --git a/trunk/arch/arm/common/sharpsl_pm.c b/trunk/arch/arm/common/sharpsl_pm.c index 3bf3a927ae22..62cb50816cc6 100644 --- a/trunk/arch/arm/common/sharpsl_pm.c +++ b/trunk/arch/arm/common/sharpsl_pm.c @@ -768,7 +768,6 @@ static void sharpsl_apm_get_power_status(struct apm_power_info *info) static struct pm_ops sharpsl_pm_ops = { .prepare = pxa_pm_prepare, .enter = corgi_pxa_pm_enter, - .finish = pxa_pm_finish, .valid = pm_valid_only_mem, }; diff --git a/trunk/arch/arm/kernel/head-common.S b/trunk/arch/arm/kernel/head-common.S index 024a9cf469b4..a52da0ddb43d 100644 --- a/trunk/arch/arm/kernel/head-common.S +++ b/trunk/arch/arm/kernel/head-common.S @@ -20,8 +20,7 @@ __switch_data: .long _end @ r7 .long processor_id @ r4 .long __machine_arch_type @ r5 - .long __atags_pointer @ r6 - .long cr_alignment @ r7 + .long cr_alignment @ r6 .long init_thread_union + THREAD_START_SP @ sp /* @@ -30,7 +29,6 @@ __switch_data: * * r0 = cp#15 control register * r1 = machine ID - * r2 = atags pointer * r9 = processor ID */ .type __mmap_switched, %function @@ -49,12 +47,11 @@ __mmap_switched: strcc fp, [r6],#4 bcc 1b - ldmia r3, {r4, r5, r6, r7, sp} + ldmia r3, {r4, r5, r6, sp} str r9, [r4] @ Save processor ID str r1, [r5] @ Save machine type - str r2, [r6] @ Save atags pointer bic r4, r0, #CR_A @ Clear 'A' bit - stmia r7, {r0, r4} @ Save control register values + stmia r6, {r0, r4} @ Save control register values b start_kernel /* @@ -218,34 +215,3 @@ ENTRY(lookup_machine_type) bl __lookup_machine_type mov r0, r5 ldmfd sp!, {r4 - r6, pc} - -/* Determine validity of the r2 atags pointer. The heuristic requires - * that the pointer be aligned, in the first 16k of physical RAM and - * that the ATAG_CORE marker is first and present. Future revisions - * of this function may be more lenient with the physical address and - * may also be able to move the ATAGS block if necessary. - * - * r8 = machinfo - * - * Returns: - * r2 either valid atags pointer, or zero - * r5, r6 corrupted - */ - - .type __vet_atags, %function -__vet_atags: - tst r2, #0x3 @ aligned? - bne 1f - - ldr r5, [r2, #0] @ is first tag ATAG_CORE? - subs r5, r5, #ATAG_CORE_SIZE - bne 1f - ldr r5, [r2, #4] - ldr r6, =ATAG_CORE - cmp r5, r6 - bne 1f - - mov pc, lr @ atag pointer is ok - -1: mov r2, #0 - mov pc, lr diff --git a/trunk/arch/arm/kernel/head.S b/trunk/arch/arm/kernel/head.S index 7898cbc9861a..41f98b4ba2ee 100644 --- a/trunk/arch/arm/kernel/head.S +++ b/trunk/arch/arm/kernel/head.S @@ -29,10 +29,6 @@ #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) #define KERNEL_RAM_PADDR (PHYS_OFFSET + TEXT_OFFSET) -#define ATAG_CORE 0x54410001 -#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2) - - /* * swapper_pg_dir is the virtual address of the initial page table. * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must @@ -65,7 +61,7 @@ * * This is normally called from the decompressor code. The requirements * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, - * r1 = machine nr, r2 = atags pointer. + * r1 = machine nr. * * This code is mostly position independent, so if you link the kernel at * 0xc0008000, you call this at __pa(0xc0008000). @@ -89,7 +85,6 @@ ENTRY(stext) bl __lookup_machine_type @ r5=machinfo movs r8, r5 @ invalid machine (r5=0)? beq __error_a @ yes, error 'a' - bl __vet_atags bl __create_page_tables /* diff --git a/trunk/arch/arm/kernel/process.c b/trunk/arch/arm/kernel/process.c index 93b7f8e22dcc..842361777d4e 100644 --- a/trunk/arch/arm/kernel/process.c +++ b/trunk/arch/arm/kernel/process.c @@ -44,10 +44,6 @@ static const char *processor_modes[] = { "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32" }; -static const char *isa_modes[] = { - "ARM" , "Thumb" , "Jazelle", "ThumbEE" -}; - extern void setup_mm_for_reboot(char mode); static volatile int hlt_counter; @@ -234,11 +230,11 @@ void __show_regs(struct pt_regs *regs) buf[3] = flags & PSR_V_BIT ? 'V' : 'v'; buf[4] = '\0'; - printk("Flags: %s IRQs o%s FIQs o%s Mode %s ISA %s Segment %s\n", + printk("Flags: %s IRQs o%s FIQs o%s Mode %s%s Segment %s\n", buf, interrupts_enabled(regs) ? "n" : "ff", fast_interrupts_enabled(regs) ? "n" : "ff", processor_modes[processor_mode(regs)], - isa_modes[isa_mode(regs)], + thumb_mode(regs) ? " (T)" : "", get_fs() == get_ds() ? "kernel" : "user"); #ifdef CONFIG_CPU_CP15 { diff --git a/trunk/arch/arm/kernel/setup.c b/trunk/arch/arm/kernel/setup.c index 5be2e987b843..650eac1bc0a6 100644 --- a/trunk/arch/arm/kernel/setup.c +++ b/trunk/arch/arm/kernel/setup.c @@ -63,8 +63,6 @@ unsigned int processor_id; unsigned int __machine_arch_type; EXPORT_SYMBOL(__machine_arch_type); -unsigned int __atags_pointer __initdata; - unsigned int system_rev; EXPORT_SYMBOL(system_rev); @@ -782,9 +780,7 @@ void __init setup_arch(char **cmdline_p) if (mdesc->soft_reboot) reboot_setup("s"); - if (__atags_pointer) - tags = phys_to_virt(__atags_pointer); - else if (mdesc->boot_params) + if (mdesc->boot_params) tags = phys_to_virt(mdesc->boot_params); /* diff --git a/trunk/arch/arm/mach-pxa/pm.c b/trunk/arch/arm/mach-pxa/pm.c index 6bf15ae73848..6d86203aef7b 100644 --- a/trunk/arch/arm/mach-pxa/pm.c +++ b/trunk/arch/arm/mach-pxa/pm.c @@ -213,20 +213,9 @@ int pxa_pm_prepare(suspend_state_t state) EXPORT_SYMBOL_GPL(pxa_pm_prepare); -/* - * Called after devices are re-setup, but before processes are thawed. - */ -int pxa_pm_finish(suspend_state_t state) -{ - return 0; -} - -EXPORT_SYMBOL_GPL(pxa_pm_finish); - static struct pm_ops pxa_pm_ops = { .prepare = pxa_pm_prepare, .enter = pxa_pm_enter, - .finish = pxa_pm_finish, .valid = pm_valid_only_mem, }; diff --git a/trunk/arch/arm/mach-sa1100/pm.c b/trunk/arch/arm/mach-sa1100/pm.c index 01a37d3c0727..d674cf343156 100644 --- a/trunk/arch/arm/mach-sa1100/pm.c +++ b/trunk/arch/arm/mach-sa1100/pm.c @@ -57,7 +57,12 @@ enum { SLEEP_SAVE_SP = 0, static int sa11x0_pm_enter(suspend_state_t state) { unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE]; + struct timespec delta, rtc; + /* preserve current time */ + rtc.tv_sec = RCNR; + rtc.tv_nsec = 0; + save_time_delta(&delta, &rtc); gpio = GPLR; /* save vital registers */ @@ -114,6 +119,10 @@ static int sa11x0_pm_enter(suspend_state_t state) */ PSSR = PSSR_PH; + /* restore current time */ + rtc.tv_sec = RCNR; + restore_time_delta(&delta, &rtc); + return 0; } diff --git a/trunk/arch/arm/mach-sa1100/time.c b/trunk/arch/arm/mach-sa1100/time.c index fdf7b016e7ad..29cb0c1604ab 100644 --- a/trunk/arch/arm/mach-sa1100/time.c +++ b/trunk/arch/arm/mach-sa1100/time.c @@ -21,6 +21,25 @@ #define RTC_DEF_DIVIDER (32768 - 1) #define RTC_DEF_TRIM 0 +static unsigned long __init sa1100_get_rtc_time(void) +{ + /* + * According to the manual we should be able to let RTTR be zero + * and then a default divisor for a 32.768KHz clock is used. + * Apparently this doesn't work, at least for my SA1110 rev 5. + * If the clock divider is uninitialized then reset it to the + * default value to get the 1Hz clock. + */ + if (RTTR == 0) { + RTTR = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16); + printk(KERN_WARNING "Warning: uninitialized Real Time Clock\n"); + /* The current RTC value probably doesn't make sense either */ + RCNR = 0; + return 0; + } + return RCNR; +} + static int sa1100_set_rtc(void) { unsigned long current_time = xtime.tv_sec; @@ -98,10 +117,15 @@ static struct irqaction sa1100_timer_irq = { static void __init sa1100_timer_init(void) { + struct timespec tv; unsigned long flags; set_rtc = sa1100_set_rtc; + tv.tv_nsec = 0; + tv.tv_sec = sa1100_get_rtc_time(); + do_settimeofday(&tv); + OIER = 0; /* disable any timer interrupts */ OSSR = 0xf; /* clear status on all timers */ setup_irq(IRQ_OST0, &sa1100_timer_irq); diff --git a/trunk/arch/arm/mm/ioremap.c b/trunk/arch/arm/mm/ioremap.c index 75952779ce19..f3ade18862aa 100644 --- a/trunk/arch/arm/mm/ioremap.c +++ b/trunk/arch/arm/mm/ioremap.c @@ -280,10 +280,7 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, if (!type) return NULL; - /* - * Page align the mapping size, taking account of any offset. - */ - size = PAGE_ALIGN(offset + size); + size = PAGE_ALIGN(size); area = get_vm_area(size, VM_IOREMAP); if (!area) @@ -328,6 +325,11 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) if (!size || last_addr < phys_addr) return NULL; + /* + * Page align the mapping size + */ + size = PAGE_ALIGN(last_addr + 1) - phys_addr; + return __arm_ioremap_pfn(pfn, offset, size, mtype); } EXPORT_SYMBOL(__arm_ioremap); diff --git a/trunk/include/asm-arm/Kbuild b/trunk/include/asm-arm/Kbuild index 73237bd130a2..c68e1680da01 100644 --- a/trunk/include/asm-arm/Kbuild +++ b/trunk/include/asm-arm/Kbuild @@ -1,3 +1 @@ include include/asm-generic/Kbuild.asm - -unifdef-y += hwcap.h diff --git a/trunk/include/asm-arm/arch-pxa/pm.h b/trunk/include/asm-arm/arch-pxa/pm.h index 7a8a1cdf430d..52243a62c4e7 100644 --- a/trunk/include/asm-arm/arch-pxa/pm.h +++ b/trunk/include/asm-arm/arch-pxa/pm.h @@ -9,4 +9,3 @@ extern int pxa_pm_prepare(suspend_state_t state); extern int pxa_pm_enter(suspend_state_t state); -extern int pxa_pm_finish(suspend_state_t state); diff --git a/trunk/include/asm-arm/elf.h b/trunk/include/asm-arm/elf.h index d7a777f05088..3679a8a8922e 100644 --- a/trunk/include/asm-arm/elf.h +++ b/trunk/include/asm-arm/elf.h @@ -7,7 +7,6 @@ */ #include #include -#include typedef unsigned long elf_greg_t; typedef unsigned long elf_freg_t[3]; @@ -40,8 +39,30 @@ typedef struct user_fp elf_fpregset_t; #endif #define ELF_ARCH EM_ARM +/* + * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP + */ +#define HWCAP_SWP 1 +#define HWCAP_HALF 2 +#define HWCAP_THUMB 4 +#define HWCAP_26BIT 8 /* Play it safe */ +#define HWCAP_FAST_MULT 16 +#define HWCAP_FPA 32 +#define HWCAP_VFP 64 +#define HWCAP_EDSP 128 +#define HWCAP_JAVA 256 +#define HWCAP_IWMMXT 512 +#define HWCAP_CRUNCH 1024 + #ifdef __KERNEL__ #ifndef __ASSEMBLY__ +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) +extern unsigned int elf_hwcap; + /* * This yields a string that ld.so will use to load implementation * specific libraries for optimization. This is more specific in diff --git a/trunk/include/asm-arm/hwcap.h b/trunk/include/asm-arm/hwcap.h deleted file mode 100644 index 01a1391d3014..000000000000 --- a/trunk/include/asm-arm/hwcap.h +++ /dev/null @@ -1,28 +0,0 @@ -#ifndef __ASMARM_HWCAP_H -#define __ASMARM_HWCAP_H - -/* - * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP - */ -#define HWCAP_SWP 1 -#define HWCAP_HALF 2 -#define HWCAP_THUMB 4 -#define HWCAP_26BIT 8 /* Play it safe */ -#define HWCAP_FAST_MULT 16 -#define HWCAP_FPA 32 -#define HWCAP_VFP 64 -#define HWCAP_EDSP 128 -#define HWCAP_JAVA 256 -#define HWCAP_IWMMXT 512 -#define HWCAP_CRUNCH 1024 - -#if defined(__KERNEL__) && !defined(__ASSEMBLY__) -/* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) -extern unsigned int elf_hwcap; -#endif - -#endif diff --git a/trunk/include/asm-arm/ptrace.h b/trunk/include/asm-arm/ptrace.h index 7aaa206cb54e..ee3d93c281d8 100644 --- a/trunk/include/asm-arm/ptrace.h +++ b/trunk/include/asm-arm/ptrace.h @@ -10,8 +10,6 @@ #ifndef __ASM_ARM_PTRACE_H #define __ASM_ARM_PTRACE_H -#include - #define PTRACE_GETREGS 12 #define PTRACE_SETREGS 13 #define PTRACE_GETFPREGS 14 @@ -47,7 +45,6 @@ #define PSR_T_BIT 0x00000020 #define PSR_F_BIT 0x00000040 #define PSR_I_BIT 0x00000080 -#define PSR_A_BIT 0x00000100 #define PSR_J_BIT 0x01000000 #define PSR_Q_BIT 0x08000000 #define PSR_V_BIT 0x10000000 @@ -106,10 +103,6 @@ struct pt_regs { #define thumb_mode(regs) (0) #endif -#define isa_mode(regs) \ - ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \ - (((regs)->ARM_cpsr & PSR_T_BIT) >> 5)) - #define processor_mode(regs) \ ((regs)->ARM_cpsr & MODE_MASK) @@ -124,17 +117,14 @@ struct pt_regs { */ static inline int valid_user_regs(struct pt_regs *regs) { - if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) { - regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT); + if (user_mode(regs) && + (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0) return 1; - } /* * Force CPSR to something logical... */ - regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT; - if (!(elf_hwcap & HWCAP_26BIT)) - regs->ARM_cpsr |= USR_MODE; + regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT; return 0; }