From 6cd54ac5351eb1095a5f5fe1f4470f815709f89a Mon Sep 17 00:00:00 2001 From: Zhenyu Wang Date: Thu, 19 Aug 2010 09:46:15 +0800 Subject: [PATCH] --- yaml --- r: 209765 b: refs/heads/master c: 3fdef0205e69b80c4219f14b834cb85eb719039f h: refs/heads/master i: 209763: d18f3335b63ff858af401d779a9e2f156154acbb v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_irq.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 4d595062c828..5857b6d2bdfb 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 877fdacf8291d7627f339885b5ae52c2f6061734 +refs/heads/master: 3fdef0205e69b80c4219f14b834cb85eb719039f diff --git a/trunk/drivers/gpu/drm/i915/i915_irq.c b/trunk/drivers/gpu/drm/i915/i915_irq.c index 69a36fc035dc..16861b800fee 100644 --- a/trunk/drivers/gpu/drm/i915/i915_irq.c +++ b/trunk/drivers/gpu/drm/i915/i915_irq.c @@ -1381,12 +1381,17 @@ static int ironlake_irq_postinstall(struct drm_device *dev) I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); (void) I915_READ(DEIER); - /* user interrupt should be enabled, but masked initial */ + /* Gen6 only needs render pipe_control now */ + if (IS_GEN6(dev)) + render_mask = GT_PIPE_NOTIFY; + dev_priv->gt_irq_mask_reg = ~render_mask; dev_priv->gt_irq_enable_reg = render_mask; I915_WRITE(GTIIR, I915_READ(GTIIR)); I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); + if (IS_GEN6(dev)) + I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); (void) I915_READ(GTIER);