From 6d084023d5ee9aed6268cefe10be7cd457063976 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Sat, 19 Mar 2011 18:14:28 -0700 Subject: [PATCH] --- yaml --- r: 250599 b: refs/heads/master c: 4a246cfc3c337ecb800d508ee5ed906534edb25c h: refs/heads/master i: 250597: e561cefdbb6e6b4ba74e005ce95390d5f28aed1c 250595: 30259aa7ccc4655842f89c05f31133a3a83f26b5 250591: fffce6aab987f259733ed013d6baa631c39126ca v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 1558d252b42f..d57f8d777386 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 96f298aa9c9fc9b7c8a2ebaf8c195d178f570e09 +refs/heads/master: 4a246cfc3c337ecb800d508ee5ed906534edb25c diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index b6f593a6d970..463f75330282 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -7325,6 +7325,19 @@ void ironlake_enable_rc6(struct drm_device *dev) OUT_RING(MI_FLUSH); ADVANCE_LP_RING(); + /* + * Wait for the command parser to advance past MI_SET_CONTEXT. The HW + * does an implicit flush, combined with MI_FLUSH above, it should be + * safe to assume that renderctx is valid + */ + ret = intel_wait_ring_idle(LP_RING(dev_priv)); + if (ret) { + DRM_ERROR("failed to enable ironlake power power savings\n"); + ironlake_teardown_rc6(dev); + mutex_unlock(&dev->struct_mutex); + return; + } + I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); mutex_unlock(&dev->struct_mutex);