From 6d8101b04727029f8415e83941080f4822145f97 Mon Sep 17 00:00:00 2001
From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Mon, 5 Nov 2012 18:22:51 +0530
Subject: [PATCH] --- yaml --- r: 339899 b: refs/heads/master c:
 e6900ddf615438edbc53df4d35a37147459d4cd8 h: refs/heads/master i:   339897:
 b088da3e9f9ad58243b78e329d687157ee1700e2   339895:
 d4be2eced02b03a0bde18cb2c12df3df50fc9dcd v: v3

---
 [refs]                             |  2 +-
 trunk/arch/arm/boot/dts/omap5.dtsi | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 9d511d2db2d0..6a70a84f7767 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 45cbe6ca07c649fef67c550a84af6fd492d77893
+refs/heads/master: e6900ddf615438edbc53df4d35a37147459d4cd8
diff --git a/trunk/arch/arm/boot/dts/omap5.dtsi b/trunk/arch/arm/boot/dts/omap5.dtsi
index ead74c85d999..790bb2a4b343 100644
--- a/trunk/arch/arm/boot/dts/omap5.dtsi
+++ b/trunk/arch/arm/boot/dts/omap5.dtsi
@@ -474,5 +474,27 @@
 			ti,hwmods = "timer11";
 			ti,timer-pwm;
 		};
+
+		emif1: emif@0x4c000000 {
+			compatible	= "ti,emif-4d5";
+			ti,hwmods	= "emif1";
+			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
+			reg = <0x4c000000 0x400>;
+			interrupts = <0 110 0x4>;
+			hw-caps-read-idle-ctrl;
+			hw-caps-ll-interface;
+			hw-caps-temp-alert;
+		};
+
+		emif2: emif@0x4d000000 {
+			compatible	= "ti,emif-4d5";
+			ti,hwmods	= "emif2";
+			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
+			reg = <0x4d000000 0x400>;
+			interrupts = <0 111 0x4>;
+			hw-caps-read-idle-ctrl;
+			hw-caps-ll-interface;
+			hw-caps-temp-alert;
+		};
 	};
 };