From 6d8d770e40b74c9b48e58db3dbe41ff0a9e4ffcd Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 5 Jul 2012 14:49:49 +0200 Subject: [PATCH] --- yaml --- r: 319622 b: refs/heads/master c: 05b8c8c1288c078f8920f5894854086f0e10f095 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/Kconfig | 2 - trunk/arch/mips/bcm63xx/Kconfig | 4 - trunk/arch/mips/bcm63xx/Makefile | 3 +- .../arch/mips/bcm63xx/boards/board_bcm963xx.c | 107 +++---- trunk/arch/mips/bcm63xx/clk.c | 26 +- trunk/arch/mips/bcm63xx/cpu.c | 63 +--- trunk/arch/mips/bcm63xx/dev-dsp.c | 2 +- trunk/arch/mips/bcm63xx/dev-flash.c | 123 -------- trunk/arch/mips/bcm63xx/dev-rng.c | 40 --- trunk/arch/mips/bcm63xx/dev-spi.c | 119 -------- trunk/arch/mips/bcm63xx/dev-wdt.c | 2 +- trunk/arch/mips/bcm63xx/irq.c | 21 -- trunk/arch/mips/bcm63xx/prom.c | 4 +- trunk/arch/mips/bcm63xx/setup.c | 13 +- .../include/asm/mach-bcm63xx/bcm63xx_cpu.h | 150 +-------- .../asm/mach-bcm63xx/bcm63xx_dev_flash.h | 12 - .../asm/mach-bcm63xx/bcm63xx_dev_spi.h | 89 ------ .../include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 - .../include/asm/mach-bcm63xx/bcm63xx_io.h | 8 - .../include/asm/mach-bcm63xx/bcm63xx_regs.h | 286 ++---------------- .../mips/include/asm/mach-bcm63xx/ioremap.h | 1 - trunk/arch/mips/pci/ops-bcm63xx.c | 61 ---- trunk/arch/mips/pci/pci-bcm63xx.c | 133 +------- trunk/arch/mips/pci/pci-bcm63xx.h | 5 - trunk/drivers/char/hw_random/Kconfig | 14 - trunk/drivers/char/hw_random/Makefile | 1 - trunk/drivers/char/hw_random/bcm63xx-rng.c | 175 ----------- 28 files changed, 104 insertions(+), 1364 deletions(-) delete mode 100644 trunk/arch/mips/bcm63xx/dev-flash.c delete mode 100644 trunk/arch/mips/bcm63xx/dev-rng.c delete mode 100644 trunk/arch/mips/bcm63xx/dev-spi.c delete mode 100644 trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h delete mode 100644 trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h delete mode 100644 trunk/drivers/char/hw_random/bcm63xx-rng.c diff --git a/[refs] b/[refs] index 2e29a79089df..f0ae1cf1ab6c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2f74b770aa6deea65415e198852c832cceedf994 +refs/heads/master: 05b8c8c1288c078f8920f5894854086f0e10f095 diff --git a/trunk/arch/mips/Kconfig b/trunk/arch/mips/Kconfig index 4ddecff78d1d..b3e10fdd3898 100644 --- a/trunk/arch/mips/Kconfig +++ b/trunk/arch/mips/Kconfig @@ -2366,8 +2366,6 @@ config PCI_DOMAINS source "drivers/pci/Kconfig" -source "drivers/pci/pcie/Kconfig" - # # ISA support is now enabled via select. Too many systems still have the one # or other ISA chip on the board that users don't know about so don't expect diff --git a/trunk/arch/mips/bcm63xx/Kconfig b/trunk/arch/mips/bcm63xx/Kconfig index d03e8799d1cf..6b1b9ad8d857 100644 --- a/trunk/arch/mips/bcm63xx/Kconfig +++ b/trunk/arch/mips/bcm63xx/Kconfig @@ -1,10 +1,6 @@ menu "CPU support" depends on BCM63XX -config BCM63XX_CPU_6328 - bool "support 6328 CPU" - select HW_HAS_PCI - config BCM63XX_CPU_6338 bool "support 6338 CPU" select HW_HAS_PCI diff --git a/trunk/arch/mips/bcm63xx/Makefile b/trunk/arch/mips/bcm63xx/Makefile index 833af72c852a..6dfdc69928ac 100644 --- a/trunk/arch/mips/bcm63xx/Makefile +++ b/trunk/arch/mips/bcm63xx/Makefile @@ -1,6 +1,5 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ - dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \ - dev-spi.o dev-uart.o dev-wdt.o + dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c index feb05258a4d1..2f1773f3fb7a 100644 --- a/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/trunk/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -11,6 +11,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -21,9 +24,7 @@ #include #include #include -#include #include -#include #include #define PFX "board_bcm963xx: " @@ -32,48 +33,6 @@ static struct bcm963xx_nvram nvram; static unsigned int mac_addr_used; static struct board_info board; -/* - * known 6328 boards - */ -#ifdef CONFIG_BCM63XX_CPU_6328 -static struct board_info __initdata board_96328avng = { - .name = "96328avng", - .expected_cpu_id = 0x6328, - - .has_uart0 = 1, - .has_pci = 1, - - .leds = { - { - .name = "96328avng::ppp-fail", - .gpio = 2, - .active_low = 1, - }, - { - .name = "96328avng::power", - .gpio = 4, - .active_low = 1, - .default_trigger = "default-on", - }, - { - .name = "96328avng::power-fail", - .gpio = 8, - .active_low = 1, - }, - { - .name = "96328avng::wps", - .gpio = 9, - .active_low = 1, - }, - { - .name = "96328avng::ppp", - .gpio = 11, - .active_low = 1, - }, - }, -}; -#endif - /* * known 6338 boards */ @@ -633,9 +592,6 @@ static struct board_info __initdata board_DWVS0 = { * all boards */ static const struct board_info __initdata *bcm963xx_boards[] = { -#ifdef CONFIG_BCM63XX_CPU_6328 - &board_96328avng, -#endif #ifdef CONFIG_BCM63XX_CPU_6338 &board_96338gw, &board_96338w, @@ -753,15 +709,9 @@ void __init board_prom_init(void) char cfe_version[32]; u32 val; - /* read base address of boot chip select (0) - * 6328 does not have MPI but boots from a fixed address - */ - if (BCMCPU_IS_6328()) - val = 0x18000000; - else { - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; - } + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; boot_addr = (u8 *)KSEG1ADDR(val); /* dump cfe version */ @@ -858,6 +808,40 @@ void __init board_setup(void) panic("unexpected CPU for bcm963xx board"); } +static struct mtd_partition mtd_partitions[] = { + { + .name = "cfe", + .offset = 0x0, + .size = 0x40000, + } +}; + +static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL }; + +static struct physmap_flash_data flash_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(mtd_partitions), + .parts = mtd_partitions, + .part_probe_types = bcm63xx_part_types, +}; + +static struct resource mtd_resources[] = { + { + .start = 0, /* filled at runtime */ + .end = 0, /* filled at runtime */ + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device mtd_dev = { + .name = "physmap-flash", + .resource = mtd_resources, + .num_resources = ARRAY_SIZE(mtd_resources), + .dev = { + .platform_data = &flash_data, + }, +}; + static struct gpio_led_platform_data bcm63xx_led_data; static struct platform_device bcm63xx_gpio_leds = { @@ -871,6 +855,8 @@ static struct platform_device bcm63xx_gpio_leds = { */ int __init board_register_devices(void) { + u32 val; + if (board.has_uart0) bcm63xx_uart_register(0); @@ -904,9 +890,14 @@ int __init board_register_devices(void) } #endif - bcm63xx_spi_register(); + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; - bcm63xx_flash_register(); + platform_device_register(&mtd_dev); bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); bcm63xx_led_data.leds = board.leds; diff --git a/trunk/arch/mips/bcm63xx/clk.c b/trunk/arch/mips/bcm63xx/clk.c index 1db48adb543a..9d57c71b7b58 100644 --- a/trunk/arch/mips/bcm63xx/clk.c +++ b/trunk/arch/mips/bcm63xx/clk.c @@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, int enable) { if (!BCMCPU_IS_6368()) return; - bcm_hwclock_set(CKCTL_6368_ROBOSW_EN | + bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN | CKCTL_6368_SWPKT_USB_EN | CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { @@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, int enable) if (BCMCPU_IS_6348()) bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); else if (BCMCPU_IS_6368()) - bcm_hwclock_set(CKCTL_6368_USBH_EN, enable); + bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable); } static struct clk clk_usbh = { @@ -181,11 +181,9 @@ static void spi_set(struct clk *clk, int enable) mask = CKCTL_6338_SPI_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_SPI_EN; - else if (BCMCPU_IS_6358()) - mask = CKCTL_6358_SPI_EN; else - /* BCMCPU_IS_6368 */ - mask = CKCTL_6368_SPI_EN; + /* BCMCPU_IS_6358 */ + mask = CKCTL_6358_SPI_EN; bcm_hwclock_set(mask, enable); } @@ -201,7 +199,7 @@ static void xtm_set(struct clk *clk, int enable) if (!BCMCPU_IS_6368()) return; - bcm_hwclock_set(CKCTL_6368_SAR_EN | + bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN | CKCTL_6368_SWPKT_SAR_EN, enable); if (enable) { @@ -223,18 +221,6 @@ static struct clk clk_xtm = { .set = xtm_set, }; -/* - * IPsec clock - */ -static void ipsec_set(struct clk *clk, int enable) -{ - bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable); -} - -static struct clk clk_ipsec = { - .set = ipsec_set, -}; - /* * Internal peripheral clock */ @@ -292,8 +278,6 @@ struct clk *clk_get(struct device *dev, const char *id) return &clk_periph; if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) return &clk_pcm; - if (BCMCPU_IS_6368() && !strcmp(id, "ipsec")) - return &clk_ipsec; return ERR_PTR(-ENOENT); } diff --git a/trunk/arch/mips/bcm63xx/cpu.c b/trunk/arch/mips/bcm63xx/cpu.c index a7afb289b15a..8f0d6c7725ea 100644 --- a/trunk/arch/mips/bcm63xx/cpu.c +++ b/trunk/arch/mips/bcm63xx/cpu.c @@ -29,14 +29,6 @@ static u16 bcm63xx_cpu_rev; static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; -static const unsigned long bcm6328_regs_base[] = { - __GEN_CPU_REGS_TABLE(6328) -}; - -static const int bcm6328_irqs[] = { - __GEN_CPU_IRQ_TABLE(6328) -}; - static const unsigned long bcm6338_regs_base[] = { __GEN_CPU_REGS_TABLE(6338) }; @@ -107,33 +99,6 @@ unsigned int bcm63xx_get_memory_size(void) static unsigned int detect_cpu_clock(void) { switch (bcm63xx_get_cpu_id()) { - case BCM6328_CPU_ID: - { - unsigned int tmp, mips_pll_fcvo; - - tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG); - mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK) - >> STRAPBUS_6328_FCVO_SHIFT; - - switch (mips_pll_fcvo) { - case 0x12: - case 0x14: - case 0x19: - return 160000000; - case 0x1c: - return 192000000; - case 0x13: - case 0x15: - return 200000000; - case 0x1a: - return 384000000; - case 0x16: - return 400000000; - default: - return 320000000; - } - - } case BCM6338_CPU_ID: /* BCM6338 has a fixed 240 Mhz frequency */ return 240000000; @@ -205,9 +170,6 @@ static unsigned int detect_memory_size(void) unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; u32 val; - if (BCMCPU_IS_6328()) - return bcm_ddr_readl(DDR_CSEND_REG) << 24; - if (BCMCPU_IS_6345()) { val = bcm_sdram_readl(SDRAM_MBASE_REG); return (val * 8 * 1024 * 1024); @@ -266,26 +228,17 @@ void __init bcm63xx_cpu_init(void) bcm63xx_irqs = bcm6345_irqs; break; case CPU_BMIPS4350: - if ((read_c0_prid() & 0xf0) == 0x10) { + switch (read_c0_prid() & 0xf0) { + case 0x10: expected_cpu_id = BCM6358_CPU_ID; bcm63xx_regs_base = bcm6358_regs_base; bcm63xx_irqs = bcm6358_irqs; - } else { - /* all newer chips have the same chip id location */ - u16 chip_id = bcm_readw(BCM_6368_PERF_BASE); - - switch (chip_id) { - case BCM6328_CPU_ID: - expected_cpu_id = BCM6328_CPU_ID; - bcm63xx_regs_base = bcm6328_regs_base; - bcm63xx_irqs = bcm6328_irqs; - break; - case BCM6368_CPU_ID: - expected_cpu_id = BCM6368_CPU_ID; - bcm63xx_regs_base = bcm6368_regs_base; - bcm63xx_irqs = bcm6368_irqs; - break; - } + break; + case 0x30: + expected_cpu_id = BCM6368_CPU_ID; + bcm63xx_regs_base = bcm6368_regs_base; + bcm63xx_irqs = bcm6368_irqs; + break; } break; } diff --git a/trunk/arch/mips/bcm63xx/dev-dsp.c b/trunk/arch/mips/bcm63xx/dev-dsp.c index 5bb5b154c9bd..da46d1d3c77c 100644 --- a/trunk/arch/mips/bcm63xx/dev-dsp.c +++ b/trunk/arch/mips/bcm63xx/dev-dsp.c @@ -31,7 +31,7 @@ static struct resource voip_dsp_resources[] = { static struct platform_device bcm63xx_voip_dsp_device = { .name = "bcm63xx-voip-dsp", - .id = -1, + .id = 0, .num_resources = ARRAY_SIZE(voip_dsp_resources), .resource = voip_dsp_resources, }; diff --git a/trunk/arch/mips/bcm63xx/dev-flash.c b/trunk/arch/mips/bcm63xx/dev-flash.c deleted file mode 100644 index 58371c7deac2..000000000000 --- a/trunk/arch/mips/bcm63xx/dev-flash.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Broadcom BCM63xx flash registration - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2008 Maxime Bizon - * Copyright (C) 2008 Florian Fainelli - * Copyright (C) 2012 Jonas Gorski - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static struct mtd_partition mtd_partitions[] = { - { - .name = "cfe", - .offset = 0x0, - .size = 0x40000, - } -}; - -static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL }; - -static struct physmap_flash_data flash_data = { - .width = 2, - .parts = mtd_partitions, - .part_probe_types = bcm63xx_part_types, -}; - -static struct resource mtd_resources[] = { - { - .start = 0, /* filled at runtime */ - .end = 0, /* filled at runtime */ - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device mtd_dev = { - .name = "physmap-flash", - .resource = mtd_resources, - .num_resources = ARRAY_SIZE(mtd_resources), - .dev = { - .platform_data = &flash_data, - }, -}; - -static int __init bcm63xx_detect_flash_type(void) -{ - u32 val; - - switch (bcm63xx_get_cpu_id()) { - case BCM6328_CPU_ID: - val = bcm_misc_readl(MISC_STRAPBUS_6328_REG); - if (val & STRAPBUS_6328_BOOT_SEL_SERIAL) - return BCM63XX_FLASH_TYPE_SERIAL; - else - return BCM63XX_FLASH_TYPE_NAND; - case BCM6338_CPU_ID: - case BCM6345_CPU_ID: - case BCM6348_CPU_ID: - /* no way to auto detect so assume parallel */ - return BCM63XX_FLASH_TYPE_PARALLEL; - case BCM6358_CPU_ID: - val = bcm_gpio_readl(GPIO_STRAPBUS_REG); - if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) - return BCM63XX_FLASH_TYPE_PARALLEL; - else - return BCM63XX_FLASH_TYPE_SERIAL; - case BCM6368_CPU_ID: - val = bcm_gpio_readl(GPIO_STRAPBUS_REG); - switch (val & STRAPBUS_6368_BOOT_SEL_MASK) { - case STRAPBUS_6368_BOOT_SEL_NAND: - return BCM63XX_FLASH_TYPE_NAND; - case STRAPBUS_6368_BOOT_SEL_SERIAL: - return BCM63XX_FLASH_TYPE_SERIAL; - case STRAPBUS_6368_BOOT_SEL_PARALLEL: - return BCM63XX_FLASH_TYPE_PARALLEL; - } - default: - return -EINVAL; - } -} - -int __init bcm63xx_flash_register(void) -{ - int flash_type; - u32 val; - - flash_type = bcm63xx_detect_flash_type(); - - switch (flash_type) { - case BCM63XX_FLASH_TYPE_PARALLEL: - /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; - - mtd_resources[0].start = val; - mtd_resources[0].end = 0x1FFFFFFF; - - return platform_device_register(&mtd_dev); - case BCM63XX_FLASH_TYPE_SERIAL: - pr_warn("unsupported serial flash detected\n"); - return -ENODEV; - case BCM63XX_FLASH_TYPE_NAND: - pr_warn("unsupported NAND flash detected\n"); - return -ENODEV; - default: - pr_err("flash detection failed for BCM%x: %d\n", - bcm63xx_get_cpu_id(), flash_type); - return -ENODEV; - } -} diff --git a/trunk/arch/mips/bcm63xx/dev-rng.c b/trunk/arch/mips/bcm63xx/dev-rng.c deleted file mode 100644 index d277b4dc6c68..000000000000 --- a/trunk/arch/mips/bcm63xx/dev-rng.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2011 Florian Fainelli - */ - -#include -#include -#include -#include - -static struct resource rng_resources[] = { - { - .start = -1, /* filled at runtime */ - .end = -1, /* filled at runtime */ - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device bcm63xx_rng_device = { - .name = "bcm63xx-rng", - .id = -1, - .num_resources = ARRAY_SIZE(rng_resources), - .resource = rng_resources, -}; - -int __init bcm63xx_rng_register(void) -{ - if (!BCMCPU_IS_6368()) - return -ENODEV; - - rng_resources[0].start = bcm63xx_regset_address(RSET_RNG); - rng_resources[0].end = rng_resources[0].start; - rng_resources[0].end += RSET_RNG_SIZE - 1; - - return platform_device_register(&bcm63xx_rng_device); -} -arch_initcall(bcm63xx_rng_register); diff --git a/trunk/arch/mips/bcm63xx/dev-spi.c b/trunk/arch/mips/bcm63xx/dev-spi.c deleted file mode 100644 index e39f73048d4f..000000000000 --- a/trunk/arch/mips/bcm63xx/dev-spi.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2009-2011 Florian Fainelli - * Copyright (C) 2010 Tanguy Bouzeloc - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#ifdef BCMCPU_RUNTIME_DETECT -/* - * register offsets - */ -static const unsigned long bcm6338_regs_spi[] = { - __GEN_SPI_REGS_TABLE(6338) -}; - -static const unsigned long bcm6348_regs_spi[] = { - __GEN_SPI_REGS_TABLE(6348) -}; - -static const unsigned long bcm6358_regs_spi[] = { - __GEN_SPI_REGS_TABLE(6358) -}; - -static const unsigned long bcm6368_regs_spi[] = { - __GEN_SPI_REGS_TABLE(6368) -}; - -const unsigned long *bcm63xx_regs_spi; -EXPORT_SYMBOL(bcm63xx_regs_spi); - -static __init void bcm63xx_spi_regs_init(void) -{ - if (BCMCPU_IS_6338()) - bcm63xx_regs_spi = bcm6338_regs_spi; - if (BCMCPU_IS_6348()) - bcm63xx_regs_spi = bcm6348_regs_spi; - if (BCMCPU_IS_6358()) - bcm63xx_regs_spi = bcm6358_regs_spi; - if (BCMCPU_IS_6368()) - bcm63xx_regs_spi = bcm6368_regs_spi; -} -#else -static __init void bcm63xx_spi_regs_init(void) { } -#endif - -static struct resource spi_resources[] = { - { - .start = -1, /* filled at runtime */ - .end = -1, /* filled at runtime */ - .flags = IORESOURCE_MEM, - }, - { - .start = -1, /* filled at runtime */ - .flags = IORESOURCE_IRQ, - }, -}; - -static struct bcm63xx_spi_pdata spi_pdata = { - .bus_num = 0, - .num_chipselect = 8, -}; - -static struct platform_device bcm63xx_spi_device = { - .name = "bcm63xx-spi", - .id = -1, - .num_resources = ARRAY_SIZE(spi_resources), - .resource = spi_resources, - .dev = { - .platform_data = &spi_pdata, - }, -}; - -int __init bcm63xx_spi_register(void) -{ - struct clk *periph_clk; - - if (BCMCPU_IS_6328() || BCMCPU_IS_6345()) - return -ENODEV; - - periph_clk = clk_get(NULL, "periph"); - if (IS_ERR(periph_clk)) { - pr_err("unable to get periph clock\n"); - return -ENODEV; - } - - /* Set bus frequency */ - spi_pdata.speed_hz = clk_get_rate(periph_clk); - - spi_resources[0].start = bcm63xx_regset_address(RSET_SPI); - spi_resources[0].end = spi_resources[0].start; - spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI); - - if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { - spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1; - spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE; - } - - if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { - spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; - spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; - } - - bcm63xx_spi_regs_init(); - - return platform_device_register(&bcm63xx_spi_device); -} diff --git a/trunk/arch/mips/bcm63xx/dev-wdt.c b/trunk/arch/mips/bcm63xx/dev-wdt.c index 2a2346a99bcb..3e6c716a4c11 100644 --- a/trunk/arch/mips/bcm63xx/dev-wdt.c +++ b/trunk/arch/mips/bcm63xx/dev-wdt.c @@ -21,7 +21,7 @@ static struct resource wdt_resources[] = { static struct platform_device bcm63xx_wdt_device = { .name = "bcm63xx-wdt", - .id = -1, + .id = 0, .num_resources = ARRAY_SIZE(wdt_resources), .resource = wdt_resources, }; diff --git a/trunk/arch/mips/bcm63xx/irq.c b/trunk/arch/mips/bcm63xx/irq.c index 18e051ad18a5..9a216a451d92 100644 --- a/trunk/arch/mips/bcm63xx/irq.c +++ b/trunk/arch/mips/bcm63xx/irq.c @@ -27,17 +27,6 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused; static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; #ifndef BCMCPU_RUNTIME_DETECT -#ifdef CONFIG_BCM63XX_CPU_6328 -#define irq_stat_reg PERF_IRQSTAT_6328_REG -#define irq_mask_reg PERF_IRQMASK_6328_REG -#define irq_bits 64 -#define is_ext_irq_cascaded 1 -#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE) -#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE) -#define ext_irq_count 4 -#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328 -#define ext_irq_cfg_reg2 0 -#endif #ifdef CONFIG_BCM63XX_CPU_6338 #define irq_stat_reg PERF_IRQSTAT_6338_REG #define irq_mask_reg PERF_IRQMASK_6338_REG @@ -129,16 +118,6 @@ static void bcm63xx_init_irq(void) irq_mask_addr = bcm63xx_regset_address(RSET_PERF); switch (bcm63xx_get_cpu_id()) { - case BCM6328_CPU_ID: - irq_stat_addr += PERF_IRQSTAT_6328_REG; - irq_mask_addr += PERF_IRQMASK_6328_REG; - irq_bits = 64; - ext_irq_count = 4; - is_ext_irq_cascaded = 1; - ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE; - ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE; - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328; - break; case BCM6338_CPU_ID: irq_stat_addr += PERF_IRQSTAT_6338_REG; irq_mask_addr += PERF_IRQMASK_6338_REG; diff --git a/trunk/arch/mips/bcm63xx/prom.c b/trunk/arch/mips/bcm63xx/prom.c index 10eaff458071..99d7f405cbeb 100644 --- a/trunk/arch/mips/bcm63xx/prom.c +++ b/trunk/arch/mips/bcm63xx/prom.c @@ -26,9 +26,7 @@ void __init prom_init(void) bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); /* disable all hardware blocks clock for now */ - if (BCMCPU_IS_6328()) - mask = CKCTL_6328_ALL_SAFE_EN; - else if (BCMCPU_IS_6338()) + if (BCMCPU_IS_6338()) mask = CKCTL_6338_ALL_SAFE_EN; else if (BCMCPU_IS_6345()) mask = CKCTL_6345_ALL_SAFE_EN; diff --git a/trunk/arch/mips/bcm63xx/setup.c b/trunk/arch/mips/bcm63xx/setup.c index 0e74a13639cd..356b05583e14 100644 --- a/trunk/arch/mips/bcm63xx/setup.c +++ b/trunk/arch/mips/bcm63xx/setup.c @@ -68,9 +68,6 @@ void bcm63xx_machine_reboot(void) /* mask and clear all external irq */ switch (bcm63xx_get_cpu_id()) { - case BCM6328_CPU_ID: - perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; - break; case BCM6338_CPU_ID: perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338; break; @@ -98,13 +95,9 @@ void bcm63xx_machine_reboot(void) bcm6348_a1_reboot(); printk(KERN_INFO "triggering watchdog soft-reset...\n"); - if (BCMCPU_IS_6328()) { - bcm_wdt_writel(1, WDT_SOFTRESET_REG); - } else { - reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); - reg |= SYS_PLL_SOFT_RESET; - bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); - } + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); + reg |= SYS_PLL_SOFT_RESET; + bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); while (1) ; } diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index e104ddb694a8..5b8d15bb5fe8 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -9,7 +9,6 @@ * compile time if only one CPU support is enabled (idea stolen from * arm mach-types) */ -#define BCM6328_CPU_ID 0x6328 #define BCM6338_CPU_ID 0x6338 #define BCM6345_CPU_ID 0x6345 #define BCM6348_CPU_ID 0x6348 @@ -21,19 +20,6 @@ u16 __bcm63xx_get_cpu_id(void); u16 bcm63xx_get_cpu_rev(void); unsigned int bcm63xx_get_cpu_freq(void); -#ifdef CONFIG_BCM63XX_CPU_6328 -# ifdef bcm63xx_get_cpu_id -# undef bcm63xx_get_cpu_id -# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() -# define BCMCPU_RUNTIME_DETECT -# else -# define bcm63xx_get_cpu_id() BCM6328_CPU_ID -# endif -# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID) -#else -# define BCMCPU_IS_6328() (0) -#endif - #ifdef CONFIG_BCM63XX_CPU_6338 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -116,13 +102,13 @@ enum bcm63xx_regs_set { RSET_UART1, RSET_GPIO, RSET_SPI, + RSET_SPI2, RSET_UDC0, RSET_OHCI0, RSET_OHCI_PRIV, RSET_USBH_PRIV, RSET_MPI, RSET_PCMCIA, - RSET_PCIE, RSET_DSL, RSET_ENET0, RSET_ENET1, @@ -144,17 +130,11 @@ enum bcm63xx_regs_set { RSET_PCMDMA, RSET_PCMDMAC, RSET_PCMDMAS, - RSET_RNG, - RSET_MISC }; #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) #define RSET_DSL_SIZE 4096 #define RSET_WDT_SIZE 12 -#define BCM_6338_RSET_SPI_SIZE 64 -#define BCM_6348_RSET_SPI_SIZE 64 -#define BCM_6358_RSET_SPI_SIZE 1804 -#define BCM_6368_RSET_SPI_SIZE 1804 #define RSET_ENET_SIZE 2048 #define RSET_ENETDMA_SIZE 2048 #define RSET_ENETSW_SIZE 65536 @@ -169,52 +149,7 @@ enum bcm63xx_regs_set { #define RSET_XTMDMA_SIZE 256 #define RSET_XTMDMAC_SIZE(chans) (16 * (chans)) #define RSET_XTMDMAS_SIZE(chans) (16 * (chans)) -#define RSET_RNG_SIZE 20 -/* - * 6328 register sets base address - */ -#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) -#define BCM_6328_PERF_BASE (0xb0000000) -#define BCM_6328_TIMER_BASE (0xb0000040) -#define BCM_6328_WDT_BASE (0xb000005c) -#define BCM_6328_UART0_BASE (0xb0000100) -#define BCM_6328_UART1_BASE (0xb0000120) -#define BCM_6328_GPIO_BASE (0xb0000080) -#define BCM_6328_SPI_BASE (0xdeadbeef) -#define BCM_6328_UDC0_BASE (0xdeadbeef) -#define BCM_6328_USBDMA_BASE (0xdeadbeef) -#define BCM_6328_OHCI0_BASE (0xdeadbeef) -#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef) -#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef) -#define BCM_6328_MPI_BASE (0xdeadbeef) -#define BCM_6328_PCMCIA_BASE (0xdeadbeef) -#define BCM_6328_PCIE_BASE (0xb0e40000) -#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef) -#define BCM_6328_DSL_BASE (0xb0001900) -#define BCM_6328_UBUS_BASE (0xdeadbeef) -#define BCM_6328_ENET0_BASE (0xdeadbeef) -#define BCM_6328_ENET1_BASE (0xdeadbeef) -#define BCM_6328_ENETDMA_BASE (0xb000d800) -#define BCM_6328_ENETDMAC_BASE (0xb000da00) -#define BCM_6328_ENETDMAS_BASE (0xb000dc00) -#define BCM_6328_ENETSW_BASE (0xb0e00000) -#define BCM_6328_EHCI0_BASE (0x10002500) -#define BCM_6328_SDRAM_BASE (0xdeadbeef) -#define BCM_6328_MEMC_BASE (0xdeadbeef) -#define BCM_6328_DDR_BASE (0xb0003000) -#define BCM_6328_M2M_BASE (0xdeadbeef) -#define BCM_6328_ATM_BASE (0xdeadbeef) -#define BCM_6328_XTM_BASE (0xdeadbeef) -#define BCM_6328_XTMDMA_BASE (0xb000b800) -#define BCM_6328_XTMDMAC_BASE (0xdeadbeef) -#define BCM_6328_XTMDMAS_BASE (0xdeadbeef) -#define BCM_6328_PCM_BASE (0xb000a800) -#define BCM_6328_PCMDMA_BASE (0xdeadbeef) -#define BCM_6328_PCMDMAC_BASE (0xdeadbeef) -#define BCM_6328_PCMDMAS_BASE (0xdeadbeef) -#define BCM_6328_RNG_BASE (0xdeadbeef) -#define BCM_6328_MISC_BASE (0xb0001800) /* * 6338 register sets base address */ @@ -227,6 +162,7 @@ enum bcm63xx_regs_set { #define BCM_6338_UART1_BASE (0xdeadbeef) #define BCM_6338_GPIO_BASE (0xfffe0400) #define BCM_6338_SPI_BASE (0xfffe0c00) +#define BCM_6338_SPI2_BASE (0xdeadbeef) #define BCM_6338_UDC0_BASE (0xdeadbeef) #define BCM_6338_USBDMA_BASE (0xfffe2400) #define BCM_6338_OHCI0_BASE (0xdeadbeef) @@ -234,7 +170,6 @@ enum bcm63xx_regs_set { #define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6338_MPI_BASE (0xfffe3160) #define BCM_6338_PCMCIA_BASE (0xdeadbeef) -#define BCM_6338_PCIE_BASE (0xdeadbeef) #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) #define BCM_6338_DSL_BASE (0xfffe1000) #define BCM_6338_UBUS_BASE (0xdeadbeef) @@ -258,8 +193,6 @@ enum bcm63xx_regs_set { #define BCM_6338_PCMDMA_BASE (0xdeadbeef) #define BCM_6338_PCMDMAC_BASE (0xdeadbeef) #define BCM_6338_PCMDMAS_BASE (0xdeadbeef) -#define BCM_6338_RNG_BASE (0xdeadbeef) -#define BCM_6338_MISC_BASE (0xdeadbeef) /* * 6345 register sets base address @@ -273,6 +206,7 @@ enum bcm63xx_regs_set { #define BCM_6345_UART1_BASE (0xdeadbeef) #define BCM_6345_GPIO_BASE (0xfffe0400) #define BCM_6345_SPI_BASE (0xdeadbeef) +#define BCM_6345_SPI2_BASE (0xdeadbeef) #define BCM_6345_UDC0_BASE (0xdeadbeef) #define BCM_6345_USBDMA_BASE (0xfffe2800) #define BCM_6345_ENET0_BASE (0xfffe1800) @@ -282,7 +216,6 @@ enum bcm63xx_regs_set { #define BCM_6345_ENETSW_BASE (0xdeadbeef) #define BCM_6345_PCMCIA_BASE (0xfffe2028) #define BCM_6345_MPI_BASE (0xfffe2000) -#define BCM_6345_PCIE_BASE (0xdeadbeef) #define BCM_6345_OHCI0_BASE (0xfffe2100) #define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) #define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) @@ -304,8 +237,6 @@ enum bcm63xx_regs_set { #define BCM_6345_PCMDMA_BASE (0xdeadbeef) #define BCM_6345_PCMDMAC_BASE (0xdeadbeef) #define BCM_6345_PCMDMAS_BASE (0xdeadbeef) -#define BCM_6345_RNG_BASE (0xdeadbeef) -#define BCM_6345_MISC_BASE (0xdeadbeef) /* * 6348 register sets base address @@ -318,13 +249,13 @@ enum bcm63xx_regs_set { #define BCM_6348_UART1_BASE (0xdeadbeef) #define BCM_6348_GPIO_BASE (0xfffe0400) #define BCM_6348_SPI_BASE (0xfffe0c00) +#define BCM_6348_SPI2_BASE (0xdeadbeef) #define BCM_6348_UDC0_BASE (0xfffe1000) #define BCM_6348_OHCI0_BASE (0xfffe1b00) #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) #define BCM_6348_MPI_BASE (0xfffe2000) #define BCM_6348_PCMCIA_BASE (0xfffe2054) -#define BCM_6348_PCIE_BASE (0xdeadbeef) #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6348_M2M_BASE (0xfffe2800) #define BCM_6348_DSL_BASE (0xfffe3000) @@ -347,8 +278,6 @@ enum bcm63xx_regs_set { #define BCM_6348_PCMDMA_BASE (0xdeadbeef) #define BCM_6348_PCMDMAC_BASE (0xdeadbeef) #define BCM_6348_PCMDMAS_BASE (0xdeadbeef) -#define BCM_6348_RNG_BASE (0xdeadbeef) -#define BCM_6348_MISC_BASE (0xdeadbeef) /* * 6358 register sets base address @@ -360,14 +289,14 @@ enum bcm63xx_regs_set { #define BCM_6358_UART0_BASE (0xfffe0100) #define BCM_6358_UART1_BASE (0xfffe0120) #define BCM_6358_GPIO_BASE (0xfffe0080) -#define BCM_6358_SPI_BASE (0xfffe0800) +#define BCM_6358_SPI_BASE (0xdeadbeef) +#define BCM_6358_SPI2_BASE (0xfffe0800) #define BCM_6358_UDC0_BASE (0xfffe0800) #define BCM_6358_OHCI0_BASE (0xfffe1400) #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6358_USBH_PRIV_BASE (0xfffe1500) #define BCM_6358_MPI_BASE (0xfffe1000) #define BCM_6358_PCMCIA_BASE (0xfffe1054) -#define BCM_6358_PCIE_BASE (0xdeadbeef) #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) #define BCM_6358_M2M_BASE (0xdeadbeef) #define BCM_6358_DSL_BASE (0xfffe3000) @@ -390,8 +319,6 @@ enum bcm63xx_regs_set { #define BCM_6358_PCMDMA_BASE (0xfffe1800) #define BCM_6358_PCMDMAC_BASE (0xfffe1900) #define BCM_6358_PCMDMAS_BASE (0xfffe1a00) -#define BCM_6358_RNG_BASE (0xdeadbeef) -#define BCM_6358_MISC_BASE (0xdeadbeef) /* @@ -404,14 +331,14 @@ enum bcm63xx_regs_set { #define BCM_6368_UART0_BASE (0xb0000100) #define BCM_6368_UART1_BASE (0xb0000120) #define BCM_6368_GPIO_BASE (0xb0000080) -#define BCM_6368_SPI_BASE (0xb0000800) +#define BCM_6368_SPI_BASE (0xdeadbeef) +#define BCM_6368_SPI2_BASE (0xb0000800) #define BCM_6368_UDC0_BASE (0xdeadbeef) #define BCM_6368_OHCI0_BASE (0xb0001600) #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef) #define BCM_6368_USBH_PRIV_BASE (0xb0001700) #define BCM_6368_MPI_BASE (0xb0001000) #define BCM_6368_PCMCIA_BASE (0xb0001054) -#define BCM_6368_PCIE_BASE (0xdeadbeef) #define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef) #define BCM_6368_M2M_BASE (0xdeadbeef) #define BCM_6368_DSL_BASE (0xdeadbeef) @@ -434,8 +361,6 @@ enum bcm63xx_regs_set { #define BCM_6368_PCMDMA_BASE (0xb0005800) #define BCM_6368_PCMDMAC_BASE (0xb0005a00) #define BCM_6368_PCMDMAS_BASE (0xb0005c00) -#define BCM_6368_RNG_BASE (0xb0004180) -#define BCM_6368_MISC_BASE (0xdeadbeef) extern const unsigned long *bcm63xx_regs_base; @@ -454,13 +379,13 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, UART1) \ __GEN_RSET_BASE(__cpu, GPIO) \ __GEN_RSET_BASE(__cpu, SPI) \ + __GEN_RSET_BASE(__cpu, SPI2) \ __GEN_RSET_BASE(__cpu, UDC0) \ __GEN_RSET_BASE(__cpu, OHCI0) \ __GEN_RSET_BASE(__cpu, OHCI_PRIV) \ __GEN_RSET_BASE(__cpu, USBH_PRIV) \ __GEN_RSET_BASE(__cpu, MPI) \ __GEN_RSET_BASE(__cpu, PCMCIA) \ - __GEN_RSET_BASE(__cpu, PCIE) \ __GEN_RSET_BASE(__cpu, DSL) \ __GEN_RSET_BASE(__cpu, ENET0) \ __GEN_RSET_BASE(__cpu, ENET1) \ @@ -482,8 +407,6 @@ extern const unsigned long *bcm63xx_regs_base; __GEN_RSET_BASE(__cpu, PCMDMA) \ __GEN_RSET_BASE(__cpu, PCMDMAC) \ __GEN_RSET_BASE(__cpu, PCMDMAS) \ - __GEN_RSET_BASE(__cpu, RNG) \ - __GEN_RSET_BASE(__cpu, MISC) \ } #define __GEN_CPU_REGS_TABLE(__cpu) \ @@ -495,13 +418,13 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \ [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \ [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \ + [RSET_SPI2] = BCM_## __cpu ##_SPI2_BASE, \ [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \ [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \ [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \ [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \ [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \ [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \ - [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \ [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \ [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \ [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \ @@ -523,8 +446,6 @@ extern const unsigned long *bcm63xx_regs_base; [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \ [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \ [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \ - [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \ - [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) @@ -532,9 +453,6 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) #ifdef BCMCPU_RUNTIME_DETECT return bcm63xx_regs_base[set]; #else -#ifdef CONFIG_BCM63XX_CPU_6328 - __GEN_RSET(6328) -#endif #ifdef CONFIG_BCM63XX_CPU_6338 __GEN_RSET(6338) #endif @@ -560,7 +478,6 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) */ enum bcm63xx_irq { IRQ_TIMER = 0, - IRQ_SPI, IRQ_UART0, IRQ_UART1, IRQ_DSL, @@ -588,52 +505,10 @@ enum bcm63xx_irq { IRQ_XTM_DMA0, }; -/* - * 6328 irqs - */ -#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) - -#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31) -#define BCM_6328_SPI_IRQ 0 -#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28) -#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) -#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4) -#define BCM_6328_UDC0_IRQ 0 -#define BCM_6328_ENET0_IRQ 0 -#define BCM_6328_ENET1_IRQ 0 -#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) -#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9) -#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) -#define BCM_6328_PCMCIA_IRQ 0 -#define BCM_6328_ENET0_RXDMA_IRQ 0 -#define BCM_6328_ENET0_TXDMA_IRQ 0 -#define BCM_6328_ENET1_RXDMA_IRQ 0 -#define BCM_6328_ENET1_TXDMA_IRQ 0 -#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23) -#define BCM_6328_ATM_IRQ 0 -#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0) -#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1) -#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2) -#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3) -#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4) -#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5) -#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6) -#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7) -#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31) -#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11) - -#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2) -#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3) -#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24) -#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25) -#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26) -#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27) - /* * 6338 irqs */ #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6338_UART1_IRQ 0 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) @@ -664,7 +539,6 @@ enum bcm63xx_irq { * 6345 irqs */ #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6345_SPI_IRQ 0 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6345_UART1_IRQ 0 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) @@ -695,7 +569,6 @@ enum bcm63xx_irq { * 6348 irqs */ #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6348_UART1_IRQ 0 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) @@ -726,7 +599,6 @@ enum bcm63xx_irq { * 6358 irqs */ #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) @@ -766,7 +638,6 @@ enum bcm63xx_irq { #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) #define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) -#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1) #define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2) #define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3) #define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4) @@ -806,7 +677,6 @@ extern const int *bcm63xx_irqs; #define __GEN_CPU_IRQ_TABLE(__cpu) \ [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \ - [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \ [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \ [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \ [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h deleted file mode 100644 index 354b8481ec4a..000000000000 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __BCM63XX_FLASH_H -#define __BCM63XX_FLASH_H - -enum { - BCM63XX_FLASH_TYPE_PARALLEL, - BCM63XX_FLASH_TYPE_SERIAL, - BCM63XX_FLASH_TYPE_NAND, -}; - -int __init bcm63xx_flash_register(void); - -#endif /* __BCM63XX_FLASH_H */ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h deleted file mode 100644 index 7d98dbe5d4b5..000000000000 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h +++ /dev/null @@ -1,89 +0,0 @@ -#ifndef BCM63XX_DEV_SPI_H -#define BCM63XX_DEV_SPI_H - -#include -#include -#include - -int __init bcm63xx_spi_register(void); - -struct bcm63xx_spi_pdata { - unsigned int fifo_size; - int bus_num; - int num_chipselect; - u32 speed_hz; -}; - -enum bcm63xx_regs_spi { - SPI_CMD, - SPI_INT_STATUS, - SPI_INT_MASK_ST, - SPI_INT_MASK, - SPI_ST, - SPI_CLK_CFG, - SPI_FILL_BYTE, - SPI_MSG_TAIL, - SPI_RX_TAIL, - SPI_MSG_CTL, - SPI_MSG_DATA, - SPI_RX_DATA, -}; - -#define __GEN_SPI_RSET_BASE(__cpu, __rset) \ - case SPI_## __rset: \ - return SPI_## __cpu ##_## __rset; - -#define __GEN_SPI_RSET(__cpu) \ - switch (reg) { \ - __GEN_SPI_RSET_BASE(__cpu, CMD) \ - __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \ - __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \ - __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \ - __GEN_SPI_RSET_BASE(__cpu, ST) \ - __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \ - __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \ - __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \ - __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \ - __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \ - __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \ - __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \ - } - -#define __GEN_SPI_REGS_TABLE(__cpu) \ - [SPI_CMD] = SPI_## __cpu ##_CMD, \ - [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \ - [SPI_INT_MASK_ST] = SPI_## __cpu ##_INT_MASK_ST, \ - [SPI_INT_MASK] = SPI_## __cpu ##_INT_MASK, \ - [SPI_ST] = SPI_## __cpu ##_ST, \ - [SPI_CLK_CFG] = SPI_## __cpu ##_CLK_CFG, \ - [SPI_FILL_BYTE] = SPI_## __cpu ##_FILL_BYTE, \ - [SPI_MSG_TAIL] = SPI_## __cpu ##_MSG_TAIL, \ - [SPI_RX_TAIL] = SPI_## __cpu ##_RX_TAIL, \ - [SPI_MSG_CTL] = SPI_## __cpu ##_MSG_CTL, \ - [SPI_MSG_DATA] = SPI_## __cpu ##_MSG_DATA, \ - [SPI_RX_DATA] = SPI_## __cpu ##_RX_DATA, - -static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg) -{ -#ifdef BCMCPU_RUNTIME_DETECT - extern const unsigned long *bcm63xx_regs_spi; - - return bcm63xx_regs_spi[reg]; -#else -#ifdef CONFIG_BCM63XX_CPU_6338 - __GEN_SPI_RSET(6338) -#endif -#ifdef CONFIG_BCM63XX_CPU_6348 - __GEN_SPI_RSET(6348) -#endif -#ifdef CONFIG_BCM63XX_CPU_6358 - __GEN_SPI_RSET(6358) -#endif -#ifdef CONFIG_BCM63XX_CPU_6368 - __GEN_SPI_RSET(6368) -#endif -#endif - return 0; -} - -#endif /* BCM63XX_DEV_SPI_H */ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 0a9891f7580d..1d7dd96aa460 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -9,8 +9,6 @@ int __init bcm63xx_gpio_init(void); static inline unsigned long bcm63xx_gpio_count(void) { switch (bcm63xx_get_cpu_id()) { - case BCM6328_CPU_ID: - return 32; case BCM6358_CPU_ID: return 40; case BCM6338_CPU_ID: diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h index 9203d90e610c..72477a6441dd 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h @@ -40,10 +40,6 @@ #define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ BCM_CB_MEM_SIZE - 1) -#define BCM_PCIE_MEM_BASE_PA 0x10f00000 -#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024) -#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \ - BCM_PCIE_MEM_SIZE - 1) /* * Internal registers are accessed through KSEG3 @@ -89,15 +85,11 @@ #define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o)) #define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) #define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) -#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o)) -#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o)) #define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) #define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o)) #define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o)) #define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o)) #define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) #define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o)) -#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o)) -#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o)) #endif /* ! BCM63XX_IO_H_ */ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 4ccc2a748aff..fdcd78ca1b03 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -15,30 +15,6 @@ /* Clock Control register */ #define PERF_CKCTL_REG 0x4 -#define CKCTL_6328_PHYMIPS_EN (1 << 0) -#define CKCTL_6328_ADSL_QPROC_EN (1 << 1) -#define CKCTL_6328_ADSL_AFE_EN (1 << 2) -#define CKCTL_6328_ADSL_EN (1 << 3) -#define CKCTL_6328_MIPS_EN (1 << 4) -#define CKCTL_6328_SAR_EN (1 << 5) -#define CKCTL_6328_PCM_EN (1 << 6) -#define CKCTL_6328_USBD_EN (1 << 7) -#define CKCTL_6328_USBH_EN (1 << 8) -#define CKCTL_6328_HSSPI_EN (1 << 9) -#define CKCTL_6328_PCIE_EN (1 << 10) -#define CKCTL_6328_ROBOSW_EN (1 << 11) - -#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \ - CKCTL_6328_ADSL_QPROC_EN | \ - CKCTL_6328_ADSL_AFE_EN | \ - CKCTL_6328_ADSL_EN | \ - CKCTL_6328_SAR_EN | \ - CKCTL_6328_PCM_EN | \ - CKCTL_6328_USBD_EN | \ - CKCTL_6328_USBH_EN | \ - CKCTL_6328_ROBOSW_EN | \ - CKCTL_6328_PCIE_EN) - #define CKCTL_6338_ADSLPHY_EN (1 << 0) #define CKCTL_6338_MPI_EN (1 << 1) #define CKCTL_6338_DRAM_EN (1 << 2) @@ -114,36 +90,35 @@ #define CKCTL_6368_PHYMIPS_EN (1 << 6) #define CKCTL_6368_SWPKT_USB_EN (1 << 7) #define CKCTL_6368_SWPKT_SAR_EN (1 << 8) -#define CKCTL_6368_SPI_EN (1 << 9) -#define CKCTL_6368_USBD_EN (1 << 10) -#define CKCTL_6368_SAR_EN (1 << 11) -#define CKCTL_6368_ROBOSW_EN (1 << 12) -#define CKCTL_6368_UTOPIA_EN (1 << 13) -#define CKCTL_6368_PCM_EN (1 << 14) -#define CKCTL_6368_USBH_EN (1 << 15) +#define CKCTL_6368_SPI_CLK_EN (1 << 9) +#define CKCTL_6368_USBD_CLK_EN (1 << 10) +#define CKCTL_6368_SAR_CLK_EN (1 << 11) +#define CKCTL_6368_ROBOSW_CLK_EN (1 << 12) +#define CKCTL_6368_UTOPIA_CLK_EN (1 << 13) +#define CKCTL_6368_PCM_CLK_EN (1 << 14) +#define CKCTL_6368_USBH_CLK_EN (1 << 15) #define CKCTL_6368_DISABLE_GLESS_EN (1 << 16) -#define CKCTL_6368_NAND_EN (1 << 17) -#define CKCTL_6368_IPSEC_EN (1 << 18) +#define CKCTL_6368_NAND_CLK_EN (1 << 17) +#define CKCTL_6368_IPSEC_CLK_EN (1 << 18) #define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \ CKCTL_6368_SWPKT_SAR_EN | \ - CKCTL_6368_SPI_EN | \ - CKCTL_6368_USBD_EN | \ - CKCTL_6368_SAR_EN | \ - CKCTL_6368_ROBOSW_EN | \ - CKCTL_6368_UTOPIA_EN | \ - CKCTL_6368_PCM_EN | \ - CKCTL_6368_USBH_EN | \ + CKCTL_6368_SPI_CLK_EN | \ + CKCTL_6368_USBD_CLK_EN | \ + CKCTL_6368_SAR_CLK_EN | \ + CKCTL_6368_ROBOSW_CLK_EN | \ + CKCTL_6368_UTOPIA_CLK_EN | \ + CKCTL_6368_PCM_CLK_EN | \ + CKCTL_6368_USBH_CLK_EN | \ CKCTL_6368_DISABLE_GLESS_EN | \ - CKCTL_6368_NAND_EN | \ - CKCTL_6368_IPSEC_EN) + CKCTL_6368_NAND_CLK_EN | \ + CKCTL_6368_IPSEC_CLK_EN) /* System PLL Control register */ #define PERF_SYS_PLL_CTL_REG 0x8 #define SYS_PLL_SOFT_RESET 0x1 /* Interrupt Mask register */ -#define PERF_IRQMASK_6328_REG 0x20 #define PERF_IRQMASK_6338_REG 0xc #define PERF_IRQMASK_6345_REG 0xc #define PERF_IRQMASK_6348_REG 0xc @@ -151,7 +126,6 @@ #define PERF_IRQMASK_6368_REG 0x20 /* Interrupt Status register */ -#define PERF_IRQSTAT_6328_REG 0x28 #define PERF_IRQSTAT_6338_REG 0x10 #define PERF_IRQSTAT_6345_REG 0x10 #define PERF_IRQSTAT_6348_REG 0x10 @@ -159,7 +133,6 @@ #define PERF_IRQSTAT_6368_REG 0x28 /* External Interrupt Configuration register */ -#define PERF_EXTIRQ_CFG_REG_6328 0x18 #define PERF_EXTIRQ_CFG_REG_6338 0x14 #define PERF_EXTIRQ_CFG_REG_6348 0x14 #define PERF_EXTIRQ_CFG_REG_6358 0x14 @@ -189,21 +162,8 @@ /* Soft Reset register */ #define PERF_SOFTRESET_REG 0x28 -#define PERF_SOFTRESET_6328_REG 0x10 #define PERF_SOFTRESET_6368_REG 0x10 -#define SOFTRESET_6328_SPI_MASK (1 << 0) -#define SOFTRESET_6328_EPHY_MASK (1 << 1) -#define SOFTRESET_6328_SAR_MASK (1 << 2) -#define SOFTRESET_6328_ENETSW_MASK (1 << 3) -#define SOFTRESET_6328_USBS_MASK (1 << 4) -#define SOFTRESET_6328_USBH_MASK (1 << 5) -#define SOFTRESET_6328_PCM_MASK (1 << 6) -#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7) -#define SOFTRESET_6328_PCIE_MASK (1 << 8) -#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9) -#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10) - #define SOFTRESET_6338_SPI_MASK (1 << 0) #define SOFTRESET_6338_ENET_MASK (1 << 2) #define SOFTRESET_6338_USBH_MASK (1 << 3) @@ -347,8 +307,6 @@ /* Watchdog reset length register */ #define WDT_RSTLEN_REG 0x8 -/* Watchdog soft reset register (BCM6328 only) */ -#define WDT_SOFTRESET_REG 0xc /************************************************************************* * _REG relative to RSET_UARTx @@ -549,15 +507,6 @@ #define GPIO_BASEMODE_6368_MASK 0x7 /* those bits must be kept as read in gpio basemode register*/ -#define GPIO_STRAPBUS_REG 0x40 -#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1) -#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1) -#define STRAPBUS_6368_BOOT_SEL_MASK 0x3 -#define STRAPBUS_6368_BOOT_SEL_NAND 0 -#define STRAPBUS_6368_BOOT_SEL_SERIAL 1 -#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3 - - /************************************************************************* * _REG relative to RSET_ENET *************************************************************************/ @@ -975,8 +924,6 @@ * _REG relative to RSET_DDR *************************************************************************/ -#define DDR_CSEND_REG 0x8 - #define DDR_DMIPSPLLCFG_REG 0x18 #define DMIPSPLLCFG_M1_SHIFT 0 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) @@ -1026,201 +973,4 @@ #define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14) #define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18) -/************************************************************************* - * _REG relative to RSET_RNG - *************************************************************************/ - -#define RNG_CTRL 0x00 -#define RNG_EN (1 << 0) - -#define RNG_STAT 0x04 -#define RNG_AVAIL_MASK (0xff000000) - -#define RNG_DATA 0x08 -#define RNG_THRES 0x0c -#define RNG_MASK 0x10 - -/************************************************************************* - * _REG relative to RSET_SPI - *************************************************************************/ - -/* BCM 6338 SPI core */ -#define SPI_6338_CMD 0x00 /* 16-bits register */ -#define SPI_6338_INT_STATUS 0x02 -#define SPI_6338_INT_MASK_ST 0x03 -#define SPI_6338_INT_MASK 0x04 -#define SPI_6338_ST 0x05 -#define SPI_6338_CLK_CFG 0x06 -#define SPI_6338_FILL_BYTE 0x07 -#define SPI_6338_MSG_TAIL 0x09 -#define SPI_6338_RX_TAIL 0x0b -#define SPI_6338_MSG_CTL 0x40 -#define SPI_6338_MSG_DATA 0x41 -#define SPI_6338_MSG_DATA_SIZE 0x3f -#define SPI_6338_RX_DATA 0x80 -#define SPI_6338_RX_DATA_SIZE 0x3f - -/* BCM 6348 SPI core */ -#define SPI_6348_CMD 0x00 /* 16-bits register */ -#define SPI_6348_INT_STATUS 0x02 -#define SPI_6348_INT_MASK_ST 0x03 -#define SPI_6348_INT_MASK 0x04 -#define SPI_6348_ST 0x05 -#define SPI_6348_CLK_CFG 0x06 -#define SPI_6348_FILL_BYTE 0x07 -#define SPI_6348_MSG_TAIL 0x09 -#define SPI_6348_RX_TAIL 0x0b -#define SPI_6348_MSG_CTL 0x40 -#define SPI_6348_MSG_DATA 0x41 -#define SPI_6348_MSG_DATA_SIZE 0x3f -#define SPI_6348_RX_DATA 0x80 -#define SPI_6348_RX_DATA_SIZE 0x3f - -/* BCM 6358 SPI core */ -#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ -#define SPI_6358_MSG_DATA 0x02 -#define SPI_6358_MSG_DATA_SIZE 0x21e -#define SPI_6358_RX_DATA 0x400 -#define SPI_6358_RX_DATA_SIZE 0x220 -#define SPI_6358_CMD 0x700 /* 16-bits register */ -#define SPI_6358_INT_STATUS 0x702 -#define SPI_6358_INT_MASK_ST 0x703 -#define SPI_6358_INT_MASK 0x704 -#define SPI_6358_ST 0x705 -#define SPI_6358_CLK_CFG 0x706 -#define SPI_6358_FILL_BYTE 0x707 -#define SPI_6358_MSG_TAIL 0x709 -#define SPI_6358_RX_TAIL 0x70B - -/* BCM 6358 SPI core */ -#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */ -#define SPI_6368_MSG_DATA 0x02 -#define SPI_6368_MSG_DATA_SIZE 0x21e -#define SPI_6368_RX_DATA 0x400 -#define SPI_6368_RX_DATA_SIZE 0x220 -#define SPI_6368_CMD 0x700 /* 16-bits register */ -#define SPI_6368_INT_STATUS 0x702 -#define SPI_6368_INT_MASK_ST 0x703 -#define SPI_6368_INT_MASK 0x704 -#define SPI_6368_ST 0x705 -#define SPI_6368_CLK_CFG 0x706 -#define SPI_6368_FILL_BYTE 0x707 -#define SPI_6368_MSG_TAIL 0x709 -#define SPI_6368_RX_TAIL 0x70B - -/* Shared SPI definitions */ - -/* Message configuration */ -#define SPI_FD_RW 0x00 -#define SPI_HD_W 0x01 -#define SPI_HD_R 0x02 -#define SPI_BYTE_CNT_SHIFT 0 -#define SPI_MSG_TYPE_SHIFT 14 - -/* Command */ -#define SPI_CMD_NOOP 0x00 -#define SPI_CMD_SOFT_RESET 0x01 -#define SPI_CMD_HARD_RESET 0x02 -#define SPI_CMD_START_IMMEDIATE 0x03 -#define SPI_CMD_COMMAND_SHIFT 0 -#define SPI_CMD_COMMAND_MASK 0x000f -#define SPI_CMD_DEVICE_ID_SHIFT 4 -#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 -#define SPI_CMD_ONE_BYTE_SHIFT 11 -#define SPI_CMD_ONE_WIRE_SHIFT 12 -#define SPI_DEV_ID_0 0 -#define SPI_DEV_ID_1 1 -#define SPI_DEV_ID_2 2 -#define SPI_DEV_ID_3 3 - -/* Interrupt mask */ -#define SPI_INTR_CMD_DONE 0x01 -#define SPI_INTR_RX_OVERFLOW 0x02 -#define SPI_INTR_TX_UNDERFLOW 0x04 -#define SPI_INTR_TX_OVERFLOW 0x08 -#define SPI_INTR_RX_UNDERFLOW 0x10 -#define SPI_INTR_CLEAR_ALL 0x1f - -/* Status */ -#define SPI_RX_EMPTY 0x02 -#define SPI_CMD_BUSY 0x04 -#define SPI_SERIAL_BUSY 0x08 - -/* Clock configuration */ -#define SPI_CLK_20MHZ 0x00 -#define SPI_CLK_0_391MHZ 0x01 -#define SPI_CLK_0_781MHZ 0x02 /* default */ -#define SPI_CLK_1_563MHZ 0x03 -#define SPI_CLK_3_125MHZ 0x04 -#define SPI_CLK_6_250MHZ 0x05 -#define SPI_CLK_12_50MHZ 0x06 -#define SPI_CLK_MASK 0x07 -#define SPI_SSOFFTIME_MASK 0x38 -#define SPI_SSOFFTIME_SHIFT 3 -#define SPI_BYTE_SWAP 0x80 - -/************************************************************************* - * _REG relative to RSET_MISC - *************************************************************************/ -#define MISC_SERDES_CTRL_REG 0x0 -#define SERDES_PCIE_EN (1 << 0) -#define SERDES_PCIE_EXD_EN (1 << 15) - -#define MISC_STRAPBUS_6328_REG 0x240 -#define STRAPBUS_6328_FCVO_SHIFT 7 -#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT) -#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28) -#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28) - -/************************************************************************* - * _REG relative to RSET_PCIE - *************************************************************************/ - -#define PCIE_CONFIG2_REG 0x408 -#define CONFIG2_BAR1_SIZE_EN 1 -#define CONFIG2_BAR1_SIZE_MASK 0xf - -#define PCIE_IDVAL3_REG 0x43c -#define IDVAL3_CLASS_CODE_MASK 0xffffff -#define IDVAL3_SUBCLASS_SHIFT 8 -#define IDVAL3_CLASS_SHIFT 16 - -#define PCIE_DLSTATUS_REG 0x1048 -#define DLSTATUS_PHYLINKUP (1 << 13) - -#define PCIE_BRIDGE_OPT1_REG 0x2820 -#define OPT1_RD_BE_OPT_EN (1 << 7) -#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9) -#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11) -#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12) - -#define PCIE_BRIDGE_OPT2_REG 0x2824 -#define OPT2_UBUS_UR_DECODE_DIS (1 << 2) -#define OPT2_TX_CREDIT_CHK_EN (1 << 4) -#define OPT2_CFG_TYPE1_BD_SEL (1 << 7) -#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16 -#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT) - -#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828 -#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830 -#define BASEMASK_REMAP_EN (1 << 0) -#define BASEMASK_SWAP_EN (1 << 1) -#define BASEMASK_MASK_SHIFT 4 -#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT) -#define BASEMASK_BASE_SHIFT 20 -#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT) - -#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c -#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834 -#define REBASE_ADDR_BASE_SHIFT 20 -#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT) - -#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854 -#define PCIE_RC_INT_A (1 << 0) -#define PCIE_RC_INT_B (1 << 1) -#define PCIE_RC_INT_C (1 << 2) -#define PCIE_RC_INT_D (1 << 3) - -#define PCIE_DEVICE_OFFSET 0x8000 - #endif /* BCM63XX_REGS_H_ */ diff --git a/trunk/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/trunk/arch/mips/include/asm/mach-bcm63xx/ioremap.h index 30931c42379d..ef94ba73646e 100644 --- a/trunk/arch/mips/include/asm/mach-bcm63xx/ioremap.h +++ b/trunk/arch/mips/include/asm/mach-bcm63xx/ioremap.h @@ -18,7 +18,6 @@ static inline int is_bcm63xx_internal_registers(phys_t offset) if (offset >= 0xfff00000) return 1; break; - case BCM6328_CPU_ID: case BCM6368_CPU_ID: if (offset >= 0xb0000000 && offset < 0xb1000000) return 1; diff --git a/trunk/arch/mips/pci/ops-bcm63xx.c b/trunk/arch/mips/pci/ops-bcm63xx.c index 4a156629e958..822ae179bc56 100644 --- a/trunk/arch/mips/pci/ops-bcm63xx.c +++ b/trunk/arch/mips/pci/ops-bcm63xx.c @@ -465,64 +465,3 @@ static void bcm63xx_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup); #endif - -static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn) -{ - switch (bus->number) { - case PCIE_BUS_BRIDGE: - return (PCI_SLOT(devfn) == 0); - case PCIE_BUS_DEVICE: - if (PCI_SLOT(devfn) == 0) - return bcm_pcie_readl(PCIE_DLSTATUS_REG) - & DLSTATUS_PHYLINKUP; - default: - return false; - } -} - -static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data; - u32 reg = where & ~3; - - if (!bcm63xx_pcie_can_access(bus, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (bus->number == PCIE_BUS_DEVICE) - reg += PCIE_DEVICE_OFFSET; - - data = bcm_pcie_readl(reg); - - *val = postprocess_read(data, where, size); - - return PCIBIOS_SUCCESSFUL; - -} - -static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data; - u32 reg = where & ~3; - - if (!bcm63xx_pcie_can_access(bus, devfn)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (bus->number == PCIE_BUS_DEVICE) - reg += PCIE_DEVICE_OFFSET; - - - data = bcm_pcie_readl(reg); - - data = preprocess_write(data, val, where, size); - bcm_pcie_writel(data, reg); - - return PCIBIOS_SUCCESSFUL; -} - - -struct pci_ops bcm63xx_pcie_ops = { - .read = bcm63xx_pcie_read, - .write = bcm63xx_pcie_write -}; diff --git a/trunk/arch/mips/pci/pci-bcm63xx.c b/trunk/arch/mips/pci/pci-bcm63xx.c index 8a48139d219c..39eb7c417e2f 100644 --- a/trunk/arch/mips/pci/pci-bcm63xx.c +++ b/trunk/arch/mips/pci/pci-bcm63xx.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include "pci-bcm63xx.h" @@ -72,26 +71,6 @@ struct pci_controller bcm63xx_cb_controller = { }; #endif -static struct resource bcm_pcie_mem_resource = { - .name = "bcm63xx PCIe memory space", - .start = BCM_PCIE_MEM_BASE_PA, - .end = BCM_PCIE_MEM_END_PA, - .flags = IORESOURCE_MEM, -}; - -static struct resource bcm_pcie_io_resource = { - .name = "bcm63xx PCIe IO space", - .start = 0, - .end = 0, - .flags = 0, -}; - -struct pci_controller bcm63xx_pcie_controller = { - .pci_ops = &bcm63xx_pcie_ops, - .io_resource = &bcm_pcie_io_resource, - .mem_resource = &bcm_pcie_mem_resource, -}; - static u32 bcm63xx_int_cfg_readl(u32 reg) { u32 tmp; @@ -115,99 +94,17 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg) void __iomem *pci_iospace_start; -static void __init bcm63xx_reset_pcie(void) -{ - u32 val; - - /* enable clock */ - val = bcm_perf_readl(PERF_CKCTL_REG); - val |= CKCTL_6328_PCIE_EN; - bcm_perf_writel(val, PERF_CKCTL_REG); - - /* enable SERDES */ - val = bcm_misc_readl(MISC_SERDES_CTRL_REG); - val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; - bcm_misc_writel(val, MISC_SERDES_CTRL_REG); - - /* reset the PCIe core */ - val = bcm_perf_readl(PERF_SOFTRESET_6328_REG); - - val &= ~SOFTRESET_6328_PCIE_MASK; - val &= ~SOFTRESET_6328_PCIE_CORE_MASK; - val &= ~SOFTRESET_6328_PCIE_HARD_MASK; - val &= ~SOFTRESET_6328_PCIE_EXT_MASK; - bcm_perf_writel(val, PERF_SOFTRESET_6328_REG); - mdelay(10); - - val |= SOFTRESET_6328_PCIE_MASK; - val |= SOFTRESET_6328_PCIE_CORE_MASK; - val |= SOFTRESET_6328_PCIE_HARD_MASK; - bcm_perf_writel(val, PERF_SOFTRESET_6328_REG); - mdelay(10); - - val |= SOFTRESET_6328_PCIE_EXT_MASK; - bcm_perf_writel(val, PERF_SOFTRESET_6328_REG); - mdelay(200); -} - -static int __init bcm63xx_register_pcie(void) +static int __init bcm63xx_pci_init(void) { + unsigned int mem_size; u32 val; - bcm63xx_reset_pcie(); - - /* configure the PCIe bridge */ - val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); - val |= OPT1_RD_BE_OPT_EN; - val |= OPT1_RD_REPLY_BE_FIX_EN; - val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN; - val |= OPT1_L1_INT_STATUS_MASK_POL; - bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG); - - /* setup the interrupts */ - val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG); - val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D; - bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG); - - val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG); - /* enable credit checking and error checking */ - val |= OPT2_TX_CREDIT_CHK_EN; - val |= OPT2_UBUS_UR_DECODE_DIS; - - /* set device bus/func for the pcie device */ - val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT); - val |= OPT2_CFG_TYPE1_BD_SEL; - bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); - - /* setup class code as bridge */ - val = bcm_pcie_readl(PCIE_IDVAL3_REG); - val &= ~IDVAL3_CLASS_CODE_MASK; - val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT); - bcm_pcie_writel(val, PCIE_IDVAL3_REG); - - /* disable bar1 size */ - val = bcm_pcie_readl(PCIE_CONFIG2_REG); - val &= ~CONFIG2_BAR1_SIZE_MASK; - bcm_pcie_writel(val, PCIE_CONFIG2_REG); - - /* set bar0 to little endian */ - val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; - val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; - val |= BASEMASK_REMAP_EN; - bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); - - val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; - bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); - - register_pci_controller(&bcm63xx_pcie_controller); + if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368()) + return -ENODEV; - return 0; -} + if (!bcm63xx_pci_enabled) + return -ENODEV; -static int __init bcm63xx_register_pci(void) -{ - unsigned int mem_size; - u32 val; /* * configuration access are done through IO space, remap 4 * first bytes to access it from CPU. @@ -324,22 +221,4 @@ static int __init bcm63xx_register_pci(void) return 0; } - -static int __init bcm63xx_pci_init(void) -{ - if (!bcm63xx_pci_enabled) - return -ENODEV; - - switch (bcm63xx_get_cpu_id()) { - case BCM6328_CPU_ID: - return bcm63xx_register_pcie(); - case BCM6348_CPU_ID: - case BCM6358_CPU_ID: - case BCM6368_CPU_ID: - return bcm63xx_register_pci(); - default: - return -ENODEV; - } -} - arch_initcall(bcm63xx_pci_init); diff --git a/trunk/arch/mips/pci/pci-bcm63xx.h b/trunk/arch/mips/pci/pci-bcm63xx.h index e6736d558ac7..a6e594ef3d6a 100644 --- a/trunk/arch/mips/pci/pci-bcm63xx.h +++ b/trunk/arch/mips/pci/pci-bcm63xx.h @@ -13,16 +13,11 @@ */ #define CARDBUS_PCI_IDSEL 0x8 - -#define PCIE_BUS_BRIDGE 0 -#define PCIE_BUS_DEVICE 1 - /* * defined in ops-bcm63xx.c */ extern struct pci_ops bcm63xx_pci_ops; extern struct pci_ops bcm63xx_cb_ops; -extern struct pci_ops bcm63xx_pcie_ops; /* * defined in pci-bcm63xx.c diff --git a/trunk/drivers/char/hw_random/Kconfig b/trunk/drivers/char/hw_random/Kconfig index 6640311ff1c9..f45dad39a18b 100644 --- a/trunk/drivers/char/hw_random/Kconfig +++ b/trunk/drivers/char/hw_random/Kconfig @@ -73,20 +73,6 @@ config HW_RANDOM_ATMEL If unsure, say Y. -config HW_RANDOM_BCM63XX - tristate "Broadcom BCM63xx Random Number Generator support" - depends on HW_RANDOM && BCM63XX - default HW_RANDOM - ---help--- - This driver provides kernel-side support for the Random Number - Generator hardware found on the Broadcom BCM63xx SoCs. - - To compile this driver as a module, choose M here: the - module will be called bcm63xx-rng - - If unusure, say Y. - - config HW_RANDOM_GEODE tristate "AMD Geode HW Random Number Generator support" depends on HW_RANDOM && X86_32 && PCI diff --git a/trunk/drivers/char/hw_random/Makefile b/trunk/drivers/char/hw_random/Makefile index 67f57bf239e4..d901dfa30321 100644 --- a/trunk/drivers/char/hw_random/Makefile +++ b/trunk/drivers/char/hw_random/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o -obj-$(CONFIG_HW_RANDOM_BCM63XX) += bcm63xx-rng.o obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o n2-rng-y := n2-drv.o n2-asm.o diff --git a/trunk/drivers/char/hw_random/bcm63xx-rng.c b/trunk/drivers/char/hw_random/bcm63xx-rng.c deleted file mode 100644 index aec6a4277caa..000000000000 --- a/trunk/drivers/char/hw_random/bcm63xx-rng.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Broadcom BCM63xx Random Number Generator support - * - * Copyright (C) 2011, Florian Fainelli - * Copyright (C) 2009, Broadcom Corporation - * - */ -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -struct bcm63xx_rng_priv { - struct clk *clk; - void __iomem *regs; -}; - -#define to_rng_priv(rng) ((struct bcm63xx_rng_priv *)rng->priv) - -static int bcm63xx_rng_init(struct hwrng *rng) -{ - struct bcm63xx_rng_priv *priv = to_rng_priv(rng); - u32 val; - - val = bcm_readl(priv->regs + RNG_CTRL); - val |= RNG_EN; - bcm_writel(val, priv->regs + RNG_CTRL); - - return 0; -} - -static void bcm63xx_rng_cleanup(struct hwrng *rng) -{ - struct bcm63xx_rng_priv *priv = to_rng_priv(rng); - u32 val; - - val = bcm_readl(priv->regs + RNG_CTRL); - val &= ~RNG_EN; - bcm_writel(val, priv->regs + RNG_CTRL); -} - -static int bcm63xx_rng_data_present(struct hwrng *rng, int wait) -{ - struct bcm63xx_rng_priv *priv = to_rng_priv(rng); - - return bcm_readl(priv->regs + RNG_STAT) & RNG_AVAIL_MASK; -} - -static int bcm63xx_rng_data_read(struct hwrng *rng, u32 *data) -{ - struct bcm63xx_rng_priv *priv = to_rng_priv(rng); - - *data = bcm_readl(priv->regs + RNG_DATA); - - return 4; -} - -static int __devinit bcm63xx_rng_probe(struct platform_device *pdev) -{ - struct resource *r; - struct clk *clk; - int ret; - struct bcm63xx_rng_priv *priv; - struct hwrng *rng; - - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!r) { - dev_err(&pdev->dev, "no iomem resource\n"); - ret = -ENXIO; - goto out; - } - - priv = kzalloc(sizeof(*priv), GFP_KERNEL); - if (!priv) { - dev_err(&pdev->dev, "no memory for private structure\n"); - ret = -ENOMEM; - goto out; - } - - rng = kzalloc(sizeof(*rng), GFP_KERNEL); - if (!rng) { - dev_err(&pdev->dev, "no memory for rng structure\n"); - ret = -ENOMEM; - goto out_free_priv; - } - - platform_set_drvdata(pdev, rng); - rng->priv = (unsigned long)priv; - rng->name = pdev->name; - rng->init = bcm63xx_rng_init; - rng->cleanup = bcm63xx_rng_cleanup; - rng->data_present = bcm63xx_rng_data_present; - rng->data_read = bcm63xx_rng_data_read; - - clk = clk_get(&pdev->dev, "ipsec"); - if (IS_ERR(clk)) { - dev_err(&pdev->dev, "no clock for device\n"); - ret = PTR_ERR(clk); - goto out_free_rng; - } - - priv->clk = clk; - - if (!devm_request_mem_region(&pdev->dev, r->start, - resource_size(r), pdev->name)) { - dev_err(&pdev->dev, "request mem failed"); - ret = -ENOMEM; - goto out_free_rng; - } - - priv->regs = devm_ioremap_nocache(&pdev->dev, r->start, - resource_size(r)); - if (!priv->regs) { - dev_err(&pdev->dev, "ioremap failed"); - ret = -ENOMEM; - goto out_free_rng; - } - - clk_enable(clk); - - ret = hwrng_register(rng); - if (ret) { - dev_err(&pdev->dev, "failed to register rng device\n"); - goto out_clk_disable; - } - - dev_info(&pdev->dev, "registered RNG driver\n"); - - return 0; - -out_clk_disable: - clk_disable(clk); -out_free_rng: - platform_set_drvdata(pdev, NULL); - kfree(rng); -out_free_priv: - kfree(priv); -out: - return ret; -} - -static int __devexit bcm63xx_rng_remove(struct platform_device *pdev) -{ - struct hwrng *rng = platform_get_drvdata(pdev); - struct bcm63xx_rng_priv *priv = to_rng_priv(rng); - - hwrng_unregister(rng); - clk_disable(priv->clk); - kfree(priv); - kfree(rng); - platform_set_drvdata(pdev, NULL); - - return 0; -} - -static struct platform_driver bcm63xx_rng_driver = { - .probe = bcm63xx_rng_probe, - .remove = __devexit_p(bcm63xx_rng_remove), - .driver = { - .name = "bcm63xx-rng", - .owner = THIS_MODULE, - }, -}; - -module_platform_driver(bcm63xx_rng_driver); - -MODULE_AUTHOR("Florian Fainelli "); -MODULE_DESCRIPTION("Broadcom BCM63xx RNG driver"); -MODULE_LICENSE("GPL");