From 6dfba86be1dce55f819fa4c172d6992035ff13b8 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Wed, 10 Oct 2012 18:09:59 -0300 Subject: [PATCH] --- yaml --- r: 345105 b: refs/heads/master c: 27c6f0a5897c06417e39f2d20a783f84a54cb0b3 h: refs/heads/master i: 345103: a9a9b73d09a046f1d7569ca42d850975be55eb6c v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_pm.c | 4 ---- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/[refs] b/[refs] index a5a53ff5640d..48855ec5c192 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1e6210f45d95f1db7831072b7be64f9562280df1 +refs/heads/master: 27c6f0a5897c06417e39f2d20a783f84a54cb0b3 diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c index eb757e5f2d87..07da990eb77d 100644 --- a/trunk/drivers/gpu/drm/i915/intel_pm.c +++ b/trunk/drivers/gpu/drm/i915/intel_pm.c @@ -3470,10 +3470,6 @@ static void haswell_init_clock_gating(struct drm_device *dev) */ I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - /* WaDisableEarlyCull */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); - /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);