From 6e05620b8360eeea3da3f7338532b25d3ed7ce91 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Thu, 27 May 2010 13:18:15 +0100 Subject: [PATCH] --- yaml --- r: 199603 b: refs/heads/master c: 808b24d6ed8b155aac17007788390ebfde263f30 h: refs/heads/master i: 199601: 7dc8580fe097a19f3f2c2be46e60d551011d71ed 199599: cc5a86fe9b9385f9a1289c574c41c83e6f0677ec v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_gem.c | 10 +++++++--- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 5a686c56c408..527b4083ea14 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b118c1e363befe3d74469f4a014ce6353097f08a +refs/heads/master: 808b24d6ed8b155aac17007788390ebfde263f30 diff --git a/trunk/drivers/gpu/drm/i915/i915_gem.c b/trunk/drivers/gpu/drm/i915/i915_gem.c index 1c65f0b591fc..6425c2a4b11f 100644 --- a/trunk/drivers/gpu/drm/i915/i915_gem.c +++ b/trunk/drivers/gpu/drm/i915/i915_gem.c @@ -3307,9 +3307,13 @@ i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, obj_priv->tiling_mode != I915_TILING_NONE; /* Check fence reg constraints and rebind if necessary */ - if (need_fence && !i915_gem_object_fence_offset_ok(obj, - obj_priv->tiling_mode)) - i915_gem_object_unbind(obj); + if (need_fence && + !i915_gem_object_fence_offset_ok(obj, + obj_priv->tiling_mode)) { + ret = i915_gem_object_unbind(obj); + if (ret) + return ret; + } /* Choose the GTT offset for our buffer and put it there. */ ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);