From 6e9bbcc54e9d932f7cc99de109373b2cd1a8f76f Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Fri, 5 Dec 2008 19:59:13 +0300 Subject: [PATCH] --- yaml --- r: 127655 b: refs/heads/master c: be11d3b354847bbc41353448dd2b34a2821ddb36 h: refs/heads/master i: 127653: a07c7ab20dc0b610a03a22e45d9fab86cef951ed 127651: abc812587d92002139044b55420df50b993edd48 127647: 7a366ac090d69235a7194531da1655e5e60edaf3 v: v3 --- [refs] | 2 +- trunk/arch/powerpc/include/asm/qe.h | 16 ++++++++++++++-- trunk/arch/powerpc/include/asm/qe_ic.h | 21 +++++++++++++++++---- 3 files changed, 32 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index b99b4e143376..231928afc176 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 20cfb41ba82d9dfc7f09451ab26e826a68a4c896 +refs/heads/master: be11d3b354847bbc41353448dd2b34a2821ddb36 diff --git a/trunk/arch/powerpc/include/asm/qe.h b/trunk/arch/powerpc/include/asm/qe.h index 32274407b93a..a0a15311d0d8 100644 --- a/trunk/arch/powerpc/include/asm/qe.h +++ b/trunk/arch/powerpc/include/asm/qe.h @@ -86,7 +86,11 @@ static inline bool qe_clock_is_brg(enum qe_clock clk) extern spinlock_t cmxgcr_lock; /* Export QE common operations */ +#ifdef CONFIG_QUICC_ENGINE extern void __init qe_reset(void); +#else +static inline void qe_reset(void) {} +#endif /* QE PIO */ #define QE_PIO_PINS 32 @@ -103,16 +107,24 @@ struct qe_pio_regs { #endif }; -extern int par_io_init(struct device_node *np); -extern int par_io_of_config(struct device_node *np); #define QE_PIO_DIR_IN 2 #define QE_PIO_DIR_OUT 1 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir, int open_drain, int assignment, int has_irq); +#ifdef CONFIG_QUICC_ENGINE +extern int par_io_init(struct device_node *np); +extern int par_io_of_config(struct device_node *np); extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, int assignment, int has_irq); extern int par_io_data_set(u8 port, u8 pin, u8 val); +#else +static inline int par_io_init(struct device_node *np) { return -ENOSYS; } +static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } +static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, + int assignment, int has_irq) { return -ENOSYS; } +static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } +#endif /* CONFIG_QUICC_ENGINE */ /* * Pin multiplexing functions. diff --git a/trunk/arch/powerpc/include/asm/qe_ic.h b/trunk/arch/powerpc/include/asm/qe_ic.h index 56a7745ca343..cf519663a791 100644 --- a/trunk/arch/powerpc/include/asm/qe_ic.h +++ b/trunk/arch/powerpc/include/asm/qe_ic.h @@ -17,6 +17,9 @@ #include +struct device_node; +struct qe_ic; + #define NUM_OF_QE_IC_GROUPS 6 /* Flags when we init the QE IC */ @@ -54,17 +57,27 @@ enum qe_ic_grp_id { QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */ }; +#ifdef CONFIG_QUICC_ENGINE void qe_ic_init(struct device_node *node, unsigned int flags, void (*low_handler)(unsigned int irq, struct irq_desc *desc), void (*high_handler)(unsigned int irq, struct irq_desc *desc)); +unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic); +unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic); +#else +static inline void qe_ic_init(struct device_node *node, unsigned int flags, + void (*low_handler)(unsigned int irq, struct irq_desc *desc), + void (*high_handler)(unsigned int irq, struct irq_desc *desc)) +{} +static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) +{ return 0; } +static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) +{ return 0; } +#endif /* CONFIG_QUICC_ENGINE */ + void qe_ic_set_highest_priority(unsigned int virq, int high); int qe_ic_set_priority(unsigned int virq, unsigned int priority); int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); -struct qe_ic; -unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic); -unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic); - static inline void qe_ic_cascade_low_ipic(unsigned int irq, struct irq_desc *desc) {