diff --git a/[refs] b/[refs] index d157e1ebd6aa..8020e1169599 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 478e1a141c6c5d6c060ff0af9dfcf88aa6f59ac3 +refs/heads/master: ef5911966d2312478a74e93d993cd623a869ab10 diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/emc.txt similarity index 99% rename from trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt rename to trunk/Documentation/devicetree/bindings/arm/tegra/emc.txt index 4c33b29dc660..09335f8eee00 100644 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-emc.txt +++ b/trunk/Documentation/devicetree/bindings/arm/tegra/emc.txt @@ -15,7 +15,7 @@ Child device nodes describe the memory settings for different configurations and Example: - memory-controller@7000f400 { + emc@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt index 866d93421eba..c25a0a55151d 100644 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt +++ b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-mc.txt @@ -8,7 +8,7 @@ Required properties: - interrupts : Should contain MC General interrupt. Example: - memory-controller@0x7000f000 { + mc { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt index bdf1a612422b..e47e73f612f4 100644 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt +++ b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt @@ -8,7 +8,7 @@ Required properties: - interrupts : Should contain MC General interrupt. Example: - memory-controller { + mc { compatible = "nvidia,tegra30-mc"; reg = <0x7000f000 0x010 0x7000f03c 0x1b4 diff --git a/trunk/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/gpio/nvidia,tegra20-gpio.txt rename to trunk/Documentation/devicetree/bindings/gpio/gpio_nvidia.txt diff --git a/trunk/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt b/trunk/Documentation/devicetree/bindings/input/tegra-kbc.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/input/nvidia,tegra20-kbc.txt rename to trunk/Documentation/devicetree/bindings/input/tegra-kbc.txt diff --git a/trunk/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/trunk/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt rename to trunk/Documentation/devicetree/bindings/mmc/nvidia-sdhci.txt diff --git a/trunk/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt b/trunk/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/nvec/nvidia,nvec.txt rename to trunk/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt b/trunk/Documentation/devicetree/bindings/sound/tegra-audio-alc5632.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-alc5632.txt rename to trunk/Documentation/devicetree/bindings/sound/tegra-audio-alc5632.txt diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt b/trunk/Documentation/devicetree/bindings/sound/tegra-audio-trimslice.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-trimslice.txt rename to trunk/Documentation/devicetree/bindings/sound/tegra-audio-trimslice.txt diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt b/trunk/Documentation/devicetree/bindings/sound/tegra-audio-wm8753.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8753.txt rename to trunk/Documentation/devicetree/bindings/sound/tegra-audio-wm8753.txt diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt b/trunk/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-wm8903.txt rename to trunk/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt b/trunk/Documentation/devicetree/bindings/sound/tegra20-das.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/sound/nvidia,tegra20-das.txt rename to trunk/Documentation/devicetree/bindings/sound/tegra20-das.txt diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt b/trunk/Documentation/devicetree/bindings/sound/tegra20-i2s.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/sound/nvidia,tegra20-i2s.txt rename to trunk/Documentation/devicetree/bindings/sound/tegra20-i2s.txt diff --git a/trunk/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt b/trunk/Documentation/devicetree/bindings/spi/spi_nvidia.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/spi/nvidia,tegra20-spi.txt rename to trunk/Documentation/devicetree/bindings/spi/spi_nvidia.txt diff --git a/trunk/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt b/trunk/Documentation/devicetree/bindings/usb/tegra-usb.txt similarity index 100% rename from trunk/Documentation/devicetree/bindings/usb/nvidia,tegra20-ehci.txt rename to trunk/Documentation/devicetree/bindings/usb/tegra-usb.txt diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 8b0b743b4fb1..a91009c61870 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -913,7 +913,7 @@ config ARCH_NOMADIK select ARM_AMBA select ARM_VIC select CPU_ARM926T - select COMMON_CLK + select CLKDEV_LOOKUP select GENERIC_CLOCKEVENTS select PINCTRL select MIGHT_HAVE_CACHE_L2X0 @@ -1021,6 +1021,8 @@ source "arch/arm/mach-kirkwood/Kconfig" source "arch/arm/mach-ks8695/Kconfig" +source "arch/arm/mach-lpc32xx/Kconfig" + source "arch/arm/mach-msm/Kconfig" source "arch/arm/mach-mv78xx0/Kconfig" diff --git a/trunk/arch/arm/boot/dts/ea3250.dts b/trunk/arch/arm/boot/dts/ea3250.dts deleted file mode 100644 index c07ba8c2cc0d..000000000000 --- a/trunk/arch/arm/boot/dts/ea3250.dts +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Embedded Artists LPC3250 board - * - * Copyright 2012 Roland Stigge - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -/include/ "lpc32xx.dtsi" - -/ { - model = "Embedded Artists LPC3250 board based on NXP LPC3250"; - compatible = "ea,ea3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0 0x4000000>; - }; - - ahb { - mac: ethernet@31060000 { - phy-mode = "rmii"; - use-iram; - }; - - /* Here, choose exactly one from: ohci, usbd */ - ohci@31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; - -/* - usbd@31020000 { - transceiver = <&isp1301>; - status = "okay"; - }; -*/ - - /* 128MB Flash via SLC NAND controller */ - slc: flash@20020000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <260000000>; - nxp,whold = <104000000>; - nxp,wsetup = <200000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <34666666>; - nxp,rhold = <104000000>; - nxp,rsetup = <200000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - mtd1@00080000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; - - mtd2@00140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; - - mtd3@00540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; - }; - }; - - apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - - uart6: serial@40098000 { - status = "okay"; - }; - - i2c1: i2c@400A0000 { - clock-frequency = <100000>; - - eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; - - eeprom@57 { - compatible = "at,24c64"; - reg = <0x57>; - }; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; - dac-clk = "wspll"; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x60>; - }; - }; - - i2c2: i2c@400A8000 { - clock-frequency = <100000>; - }; - - i2cusb: i2c@31020300 { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2d { - compatible = "nxp,isp1301"; - reg = <0x2d>; - }; - }; - - sd@20098000 { - wp-gpios = <&pca9532 5 0>; - cd-gpios = <&pca9532 4 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; - }; - }; - - fab { - uart1: serial@40014000 { - status = "okay"; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/lpc32xx.dtsi b/trunk/arch/arm/boot/dts/lpc32xx.dtsi index c5f37fbd33e6..3f5dad801a98 100644 --- a/trunk/arch/arm/boot/dts/lpc32xx.dtsi +++ b/trunk/arch/arm/boot/dts/lpc32xx.dtsi @@ -35,14 +35,13 @@ slc: flash@20020000 { compatible = "nxp,lpc3220-slc"; reg = <0x20020000 0x1000>; - status = "disabled"; + status = "disable"; }; - mlc: flash@200a8000 { + mlc: flash@200B0000 { compatible = "nxp,lpc3220-mlc"; - reg = <0x200a8000 0x11000>; - interrupts = <11 0>; - status = "disabled"; + reg = <0x200B0000 0x1000>; + status = "disable"; }; dma@31000000 { @@ -58,21 +57,21 @@ compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x31020000 0x300>; interrupts = <0x3b 0>; - status = "disabled"; + status = "disable"; }; usbd@31020000 { compatible = "nxp,lpc3220-udc"; reg = <0x31020000 0x300>; interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; - status = "disabled"; + status = "disable"; }; clcd@31040000 { compatible = "arm,pl110", "arm,primecell"; reg = <0x31040000 0x1000>; interrupts = <0x0e 0>; - status = "disabled"; + status = "disable"; }; mac: ethernet@31060000 { @@ -115,10 +114,9 @@ }; sd@20098000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl180", "arm,primecell"; reg = <0x20098000 0x1000>; interrupts = <0x0f 0>, <0x0d 0>; - status = "disabled"; }; i2s1: i2s@2009C000 { @@ -126,42 +124,24 @@ reg = <0x2009C000 0x1000>; }; - /* UART5 first since it is the default console, ttyS0 */ - uart5: serial@40090000 { - /* actually, ns16550a w/ 64 byte fifos! */ - compatible = "nxp,lpc3220-uart"; - reg = <0x40090000 0x1000>; - interrupts = <9 0>; - clock-frequency = <13000000>; - reg-shift = <2>; - status = "disabled"; - }; - uart3: serial@40080000 { - compatible = "nxp,lpc3220-uart"; + compatible = "nxp,serial"; reg = <0x40080000 0x1000>; - interrupts = <7 0>; - clock-frequency = <13000000>; - reg-shift = <2>; - status = "disabled"; }; uart4: serial@40088000 { - compatible = "nxp,lpc3220-uart"; + compatible = "nxp,serial"; reg = <0x40088000 0x1000>; - interrupts = <8 0>; - clock-frequency = <13000000>; - reg-shift = <2>; - status = "disabled"; + }; + + uart5: serial@40090000 { + compatible = "nxp,serial"; + reg = <0x40090000 0x1000>; }; uart6: serial@40098000 { - compatible = "nxp,lpc3220-uart"; + compatible = "nxp,serial"; reg = <0x40098000 0x1000>; - interrupts = <10 0>; - clock-frequency = <13000000>; - reg-shift = <2>; - status = "disabled"; }; i2c1: i2c@400A0000 { @@ -212,24 +192,18 @@ }; uart1: serial@40014000 { - compatible = "nxp,lpc3220-hsuart"; + compatible = "nxp,serial"; reg = <0x40014000 0x1000>; - interrupts = <26 0>; - status = "disabled"; }; uart2: serial@40018000 { - compatible = "nxp,lpc3220-hsuart"; + compatible = "nxp,serial"; reg = <0x40018000 0x1000>; - interrupts = <25 0>; - status = "disabled"; }; - uart7: serial@4001c000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x4001c000 0x1000>; - interrupts = <24 0>; - status = "disabled"; + uart7: serial@4001C000 { + compatible = "nxp,serial"; + reg = <0x4001C000 0x1000>; }; rtc@40024000 { @@ -261,21 +235,19 @@ compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; - status = "disabled"; + status = "disable"; }; tsc@40048000 { compatible = "nxp,lpc3220-tsc"; reg = <0x40048000 0x1000>; interrupts = <0x27 0>; - status = "disabled"; + status = "disable"; }; key@40050000 { compatible = "nxp,lpc3220-key"; reg = <0x40050000 0x1000>; - interrupts = <54 0>; - status = "disabled"; }; }; diff --git a/trunk/arch/arm/boot/dts/phy3250.dts b/trunk/arch/arm/boot/dts/phy3250.dts index 802ec5b2fd00..c4ff6d1a018b 100644 --- a/trunk/arch/arm/boot/dts/phy3250.dts +++ b/trunk/arch/arm/boot/dts/phy3250.dts @@ -54,17 +54,6 @@ #address-cells = <1>; #size-cells = <1>; - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - mtd0@00000000 { label = "phy3250-boot"; reg = <0x00000000 0x00064000>; @@ -94,14 +83,6 @@ }; apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - i2c1: i2c@400A0000 { clock-frequency = <100000>; @@ -133,58 +114,16 @@ }; ssp0: ssp@20084000 { - #address-cells = <1>; - #size-cells = <0>; - pl022,num-chipselects = <1>; - cs-gpios = <&gpio 3 5 0>; - eeprom: at25@0 { - pl022,hierarchy = <0>; - pl022,interface = <0>; - pl022,slave-tx-disable = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; }; }; - - sd@20098000 { - wp-gpios = <&gpio 3 0 0>; - cd-gpios = <&gpio 3 1 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; - }; }; fab { - uart2: serial@40018000 { - status = "okay"; - }; - tsc@40048000 { status = "okay"; }; - - key@40050000 { - status = "okay"; - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dts b/trunk/arch/arm/boot/dts/tegra-cardhu.dts similarity index 99% rename from trunk/arch/arm/boot/dts/tegra30-cardhu.dts rename to trunk/arch/arm/boot/dts/tegra-cardhu.dts index c169bced131e..36321bceec46 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu.dts +++ b/trunk/arch/arm/boot/dts/tegra-cardhu.dts @@ -144,6 +144,7 @@ sdhci@78000600 { status = "okay"; + support-8bit; bus-width = <8>; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra-harmony.dts similarity index 99% rename from trunk/arch/arm/boot/dts/tegra20-harmony.dts rename to trunk/arch/arm/boot/dts/tegra-harmony.dts index f146dbf6f7f8..7de701365fce 100644 --- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra-harmony.dts @@ -307,6 +307,7 @@ cd-gpios = <&gpio 58 0>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ + support-8bit; bus-width = <8>; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-paz00.dts b/trunk/arch/arm/boot/dts/tegra-paz00.dts similarity index 99% rename from trunk/arch/arm/boot/dts/tegra20-paz00.dts rename to trunk/arch/arm/boot/dts/tegra-paz00.dts index 684a9e1ff7e9..bfeb117d5aea 100644 --- a/trunk/arch/arm/boot/dts/tegra20-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra-paz00.dts @@ -301,6 +301,7 @@ sdhci@c8000600 { status = "okay"; + support-8bit; bus-width = <8>; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts b/trunk/arch/arm/boot/dts/tegra-seaboard.dts similarity index 99% rename from trunk/arch/arm/boot/dts/tegra20-seaboard.dts rename to trunk/arch/arm/boot/dts/tegra-seaboard.dts index b797901d040d..89cb7f2acd92 100644 --- a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra-seaboard.dts @@ -334,7 +334,7 @@ }; }; - memory-controller@0x7000f400 { + emc { emc-table@190000 { reg = <190000>; compatible = "nvidia,tegra20-emc-table"; @@ -397,6 +397,7 @@ sdhci@c8000600 { status = "okay"; + support-8bit; bus-width = <8>; }; diff --git a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts b/trunk/arch/arm/boot/dts/tegra-trimslice.dts similarity index 100% rename from trunk/arch/arm/boot/dts/tegra20-trimslice.dts rename to trunk/arch/arm/boot/dts/tegra-trimslice.dts diff --git a/trunk/arch/arm/boot/dts/tegra20-ventana.dts b/trunk/arch/arm/boot/dts/tegra-ventana.dts similarity index 99% rename from trunk/arch/arm/boot/dts/tegra20-ventana.dts rename to trunk/arch/arm/boot/dts/tegra-ventana.dts index be90544e6b59..445343b0fbdd 100644 --- a/trunk/arch/arm/boot/dts/tegra20-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra-ventana.dts @@ -314,6 +314,7 @@ sdhci@c8000600 { status = "okay"; + support-8bit; bus-width = <8>; }; diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index 59116b852434..c417d67e9027 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -164,7 +164,7 @@ reg = <0x7000e400 0x400>; }; - memory-controller@0x7000f000 { + mc { compatible = "nvidia,tegra20-mc"; reg = <0x7000f000 0x024 0x7000f03c 0x3c4>; @@ -177,7 +177,7 @@ 0x58000000 0x02000000>; /* GART aperture */ }; - memory-controller@0x7000f400 { + emc { compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x200>; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index 19479393842e..2dcc09e784b5 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -167,7 +167,7 @@ reg = <0x7000e400 0x400>; }; - memory-controller { + mc { compatible = "nvidia,tegra30-mc"; reg = <0x7000f000 0x010 0x7000f03c 0x1b4 diff --git a/trunk/arch/arm/configs/lpc32xx_defconfig b/trunk/arch/arm/configs/lpc32xx_defconfig index eceed186a3c1..4fa60547494a 100644 --- a/trunk/arch/arm/configs/lpc32xx_defconfig +++ b/trunk/arch/arm/configs/lpc32xx_defconfig @@ -1,7 +1,5 @@ CONFIG_EXPERIMENTAL=y CONFIG_SYSVIPC=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 @@ -18,6 +16,8 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set CONFIG_PARTITION_ADVANCED=y CONFIG_ARCH_LPC32XX=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -52,17 +52,13 @@ CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_CHAR=y CONFIG_MTD_BLOCK=y -CONFIG_MTD_M25P80=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_MUSEUM_IDS=y -CONFIG_MTD_NAND_SLC_LPC32XX=y -CONFIG_MTD_NAND_MLC_LPC32XX=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=1 CONFIG_BLK_DEV_RAM_SIZE=16384 -CONFIG_EEPROM_AT24=y CONFIG_EEPROM_AT25=y CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y @@ -83,22 +79,16 @@ CONFIG_LPC_ENET=y # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_SMSC_PHY=y # CONFIG_WLAN is not set -CONFIG_INPUT_MATRIXKMAP=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_LPC32XX=y # CONFIG_INPUT_MOUSE is not set CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_LPC32XX=y -CONFIG_SERIO_LIBPS2=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_HS_LPC32XX=y -CONFIG_SERIAL_OF_PLATFORM=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y CONFIG_I2C_CHARDEV=y @@ -106,8 +96,7 @@ CONFIG_I2C_PNX=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_DS620=y -CONFIG_SENSORS_MAX6639=y +# CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_PNX4008_WATCHDOG=y CONFIG_FB=y @@ -144,8 +133,6 @@ CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -CONFIG_LEDS_PCA9532=y -CONFIG_LEDS_PCA9532_GPIO=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y @@ -159,10 +146,10 @@ CONFIG_RTC_DRV_DS1374=y CONFIG_RTC_DRV_PCF8563=y CONFIG_RTC_DRV_LPC32XX=y CONFIG_DMADEVICES=y +CONFIG_AMBA_PL08X=y CONFIG_STAGING=y -CONFIG_LPC32XX_ADC=y -CONFIG_MAX517=y CONFIG_IIO=y +CONFIG_LPC32XX_ADC=y CONFIG_EXT2_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y @@ -172,6 +159,7 @@ CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_WBUF_VERIFY=y CONFIG_CRAMFS=y CONFIG_NFS_FS=y +CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y diff --git a/trunk/arch/arm/mach-davinci/Kconfig b/trunk/arch/arm/mach-davinci/Kconfig index 2ce1ef07c13d..32d837d8eab9 100644 --- a/trunk/arch/arm/mach-davinci/Kconfig +++ b/trunk/arch/arm/mach-davinci/Kconfig @@ -4,7 +4,6 @@ config AINTC bool config CP_INTC - select IRQ_DOMAIN bool config ARCH_DAVINCI_DMx diff --git a/trunk/arch/arm/mach-davinci/Makefile b/trunk/arch/arm/mach-davinci/Makefile index 2227effcb0e9..2db78bd5c835 100644 --- a/trunk/arch/arm/mach-davinci/Makefile +++ b/trunk/arch/arm/mach-davinci/Makefile @@ -39,4 +39,3 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_SUSPEND) += pm.o sleep.o -obj-$(CONFIG_HAVE_CLK) += pm_domain.o diff --git a/trunk/arch/arm/mach-davinci/cp_intc.c b/trunk/arch/arm/mach-davinci/cp_intc.c index 45d52567ced7..f83152d643c5 100644 --- a/trunk/arch/arm/mach-davinci/cp_intc.c +++ b/trunk/arch/arm/mach-davinci/cp_intc.c @@ -9,10 +9,8 @@ * kind, whether express or implied. */ -#include #include #include -#include #include #include @@ -30,7 +28,7 @@ static inline void cp_intc_write(unsigned long value, unsigned offset) static void cp_intc_ack_irq(struct irq_data *d) { - cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR); + cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR); } /* Disable interrupt */ @@ -38,20 +36,20 @@ static void cp_intc_mask_irq(struct irq_data *d) { /* XXX don't know why we need to disable nIRQ here... */ cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR); - cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR); + cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR); cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); } /* Enable interrupt */ static void cp_intc_unmask_irq(struct irq_data *d) { - cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET); + cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET); } static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type) { - unsigned reg = BIT_WORD(d->hwirq); - unsigned mask = BIT_MASK(d->hwirq); + unsigned reg = BIT_WORD(d->irq); + unsigned mask = BIT_MASK(d->irq); unsigned polarity = cp_intc_read(CP_INTC_SYS_POLARITY(reg)); unsigned type = cp_intc_read(CP_INTC_SYS_TYPE(reg)); @@ -101,36 +99,18 @@ static struct irq_chip cp_intc_irq_chip = { .irq_set_wake = cp_intc_set_wake, }; -static struct irq_domain *cp_intc_domain; - -static int cp_intc_host_map(struct irq_domain *h, unsigned int virq, - irq_hw_number_t hw) -{ - pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw); - - irq_set_chip(virq, &cp_intc_irq_chip); - set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); - irq_set_handler(virq, handle_edge_irq); - return 0; -} - -static const struct irq_domain_ops cp_intc_host_ops = { - .map = cp_intc_host_map, - .xlate = irq_domain_xlate_onetwocell, -}; - -int __init __cp_intc_init(struct device_node *node) +void __init cp_intc_init(void) { - u32 num_irq = davinci_soc_info.intc_irq_num; + unsigned long num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; u32 *host_map = davinci_soc_info.intc_host_map; unsigned num_reg = BITS_TO_LONGS(num_irq); - int i, irq_base; + int i; davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); if (WARN_ON(!davinci_intc_base)) - return -EINVAL; + return; cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); @@ -185,28 +165,13 @@ int __init __cp_intc_init(struct device_node *node) for (i = 0; host_map[i] != -1; i++) cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i)); - irq_base = irq_alloc_descs(-1, 0, num_irq, 0); - if (irq_base < 0) { - pr_warn("Couldn't allocate IRQ numbers\n"); - irq_base = 0; - } - - /* create a legacy host */ - cp_intc_domain = irq_domain_add_legacy(node, num_irq, - irq_base, 0, &cp_intc_host_ops, NULL); - - if (!cp_intc_domain) { - pr_err("cp_intc: failed to allocate irq host!\n"); - return -EINVAL; + /* Set up genirq dispatching for cp_intc */ + for (i = 0; i < num_irq; i++) { + irq_set_chip(i, &cp_intc_irq_chip); + set_irq_flags(i, IRQF_VALID | IRQF_PROBE); + irq_set_handler(i, handle_edge_irq); } /* Enable global interrupt */ cp_intc_write(1, CP_INTC_GLOBAL_ENABLE); - - return 0; -} - -void __init cp_intc_init(void) -{ - __cp_intc_init(NULL); } diff --git a/trunk/arch/arm/mach-davinci/pm_domain.c b/trunk/arch/arm/mach-davinci/pm_domain.c deleted file mode 100644 index 00946e23c1ee..000000000000 --- a/trunk/arch/arm/mach-davinci/pm_domain.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Runtime PM support code for DaVinci - * - * Author: Kevin Hilman - * - * Copyright (C) 2012 Texas Instruments, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include -#include -#include -#include - -#ifdef CONFIG_PM_RUNTIME -static int davinci_pm_runtime_suspend(struct device *dev) -{ - int ret; - - dev_dbg(dev, "%s\n", __func__); - - ret = pm_generic_runtime_suspend(dev); - if (ret) - return ret; - - ret = pm_clk_suspend(dev); - if (ret) { - pm_generic_runtime_resume(dev); - return ret; - } - - return 0; -} - -static int davinci_pm_runtime_resume(struct device *dev) -{ - dev_dbg(dev, "%s\n", __func__); - - pm_clk_resume(dev); - return pm_generic_runtime_resume(dev); -} -#endif - -static struct dev_pm_domain davinci_pm_domain = { - .ops = { - SET_RUNTIME_PM_OPS(davinci_pm_runtime_suspend, - davinci_pm_runtime_resume, NULL) - USE_PLATFORM_PM_SLEEP_OPS - }, -}; - -static struct pm_clk_notifier_block platform_bus_notifier = { - .pm_domain = &davinci_pm_domain, -}; - -static int __init davinci_pm_runtime_init(void) -{ - pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier); - - return 0; -} -core_initcall(davinci_pm_runtime_init); diff --git a/trunk/arch/arm/mach-imx/Kconfig b/trunk/arch/arm/mach-imx/Kconfig index 5a7d235902c7..eff4db5de0dd 100644 --- a/trunk/arch/arm/mach-imx/Kconfig +++ b/trunk/arch/arm/mach-imx/Kconfig @@ -73,7 +73,7 @@ config SOC_IMX31 config SOC_IMX35 bool - select CPU_V6K + select CPU_V6 select ARCH_MXC_IOMUX_V3 select COMMON_CLK select HAVE_EPIT @@ -589,7 +589,6 @@ config MACH_MX35_3DS select IMX_HAVE_PLATFORM_IPU_CORE select IMX_HAVE_PLATFORM_MXC_EHCI select IMX_HAVE_PLATFORM_MXC_NAND - select IMX_HAVE_PLATFORM_MXC_RTC select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX help Include support for MX35PDK platform. This includes specific diff --git a/trunk/arch/arm/mach-imx/devices-imx35.h b/trunk/arch/arm/mach-imx/devices-imx35.h index e55d1cbd293f..7b99ef0bb501 100644 --- a/trunk/arch/arm/mach-imx/devices-imx35.h +++ b/trunk/arch/arm/mach-imx/devices-imx35.h @@ -68,10 +68,6 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data; #define imx35_add_mxc_nand(pdata) \ imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) -extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data; -#define imx35_add_mxc_rtc() \ - imx_add_mxc_rtc(&imx35_mxc_rtc_data) - extern const struct imx_mxc_w1_data imx35_mxc_w1_data; #define imx35_add_mxc_w1(pdata) \ imx_add_mxc_w1(&imx35_mxc_w1_data) diff --git a/trunk/arch/arm/mach-imx/ehci-imx25.c b/trunk/arch/arm/mach-imx/ehci-imx25.c index 05bb41d99728..865daf0b09e9 100644 --- a/trunk/arch/arm/mach-imx/ehci-imx25.c +++ b/trunk/arch/arm/mach-imx/ehci-imx25.c @@ -24,18 +24,14 @@ #define MX25_OTG_SIC_SHIFT 29 #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) #define MX25_OTG_PM_BIT (1 << 24) -#define MX25_OTG_PP_BIT (1 << 11) -#define MX25_OTG_OCPOL_BIT (1 << 3) #define MX25_H1_SIC_SHIFT 21 #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) -#define MX25_H1_PP_BIT (1 << 18) #define MX25_H1_PM_BIT (1 << 8) #define MX25_H1_IPPUE_UP_BIT (1 << 7) #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) #define MX25_H1_TLL_BIT (1 << 5) #define MX25_H1_USBTE_BIT (1 << 4) -#define MX25_H1_OCPOL_BIT (1 << 2) int mx25_initialize_usb_hw(int port, unsigned int flags) { @@ -45,35 +41,21 @@ int mx25_initialize_usb_hw(int port, unsigned int flags) switch (port) { case 0: /* OTG port */ - v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | - MX25_OTG_OCPOL_BIT); + v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX25_OTG_PM_BIT; - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_OTG_OCPOL_BIT; - break; case 1: /* H1 port */ - v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | - MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT | - MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); + v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT | + MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX25_H1_PM_BIT; - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX25_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX25_H1_OCPOL_BIT; - if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX25_H1_TLL_BIT; diff --git a/trunk/arch/arm/mach-imx/ehci-imx35.c b/trunk/arch/arm/mach-imx/ehci-imx35.c index 73574c30cf50..001ec3971f5d 100644 --- a/trunk/arch/arm/mach-imx/ehci-imx35.c +++ b/trunk/arch/arm/mach-imx/ehci-imx35.c @@ -24,18 +24,14 @@ #define MX35_OTG_SIC_SHIFT 29 #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) #define MX35_OTG_PM_BIT (1 << 24) -#define MX35_OTG_PP_BIT (1 << 11) -#define MX35_OTG_OCPOL_BIT (1 << 3) #define MX35_H1_SIC_SHIFT 21 #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) -#define MX35_H1_PP_BIT (1 << 18) #define MX35_H1_PM_BIT (1 << 8) #define MX35_H1_IPPUE_UP_BIT (1 << 7) #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) #define MX35_H1_TLL_BIT (1 << 5) #define MX35_H1_USBTE_BIT (1 << 4) -#define MX35_H1_OCPOL_BIT (1 << 2) int mx35_initialize_usb_hw(int port, unsigned int flags) { @@ -45,35 +41,21 @@ int mx35_initialize_usb_hw(int port, unsigned int flags) switch (port) { case 0: /* OTG port */ - v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | - MX35_OTG_OCPOL_BIT); + v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX35_OTG_PM_BIT; - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_OTG_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_OTG_OCPOL_BIT; - break; case 1: /* H1 port */ - v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | - MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | - MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); + v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | + MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX35_H1_PM_BIT; - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MX35_H1_PP_BIT; - - if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) - v |= MX35_H1_OCPOL_BIT; - if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX35_H1_TLL_BIT; diff --git a/trunk/arch/arm/mach-imx/ehci-imx5.c b/trunk/arch/arm/mach-imx/ehci-imx5.c index a6a4afb0ad62..c17fa131728b 100644 --- a/trunk/arch/arm/mach-imx/ehci-imx5.c +++ b/trunk/arch/arm/mach-imx/ehci-imx5.c @@ -28,14 +28,11 @@ #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ -#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ +#define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ /* USB_PHY_CTRL_FUNC */ -#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ -#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ -#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ /* USBH2CTRL */ #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) @@ -83,21 +80,13 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) - v |= MXC_OTG_PHYCTRL_OC_POL_BIT; - else - v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) { - /* OC/USBPWR is used */ - v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; - } else { /* OC/USBPWR is not used */ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; + } else { + /* OC/USBPWR is used */ + v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; } - if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) - v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; - else - v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); @@ -106,9 +95,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) else v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_OTG_UCTRL_OPM_BIT; - else v |= MXC_OTG_UCTRL_OPM_BIT; + else + v &= ~MXC_OTG_UCTRL_OPM_BIT; __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; @@ -124,16 +113,12 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) } if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/ + v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ else v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); - if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) - v |= MXC_H1_OC_POL_BIT; - else - v &= ~MXC_H1_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ else @@ -157,7 +142,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) } if (flags & MXC_EHCI_POWER_PINS_ENABLED) - v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/ + v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ else v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/ __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); diff --git a/trunk/arch/arm/mach-imx/mach-mx35_3ds.c b/trunk/arch/arm/mach-imx/mach-mx35_3ds.c index 85568ba43640..28aa19476de7 100644 --- a/trunk/arch/arm/mach-imx/mach-mx35_3ds.c +++ b/trunk/arch/arm/mach-imx/mach-mx35_3ds.c @@ -572,7 +572,6 @@ static void __init mx35_3ds_init(void) imx35_add_fec(NULL); imx35_add_imx2_wdt(NULL); - imx35_add_mxc_rtc(); platform_add_devices(devices, ARRAY_SIZE(devices)); imx35_add_imx_uart0(&uart_pdata); diff --git a/trunk/arch/arm/mach-lpc32xx/Kconfig b/trunk/arch/arm/mach-lpc32xx/Kconfig new file mode 100644 index 000000000000..e0b3eee83834 --- /dev/null +++ b/trunk/arch/arm/mach-lpc32xx/Kconfig @@ -0,0 +1,32 @@ +if ARCH_LPC32XX + +menu "Individual UART enable selections" + +config ARCH_LPC32XX_UART3_SELECT + bool "Add support for standard UART3" + help + Adds support for standard UART 3 when the 8250 serial support + is enabled. + +config ARCH_LPC32XX_UART4_SELECT + bool "Add support for standard UART4" + help + Adds support for standard UART 4 when the 8250 serial support + is enabled. + +config ARCH_LPC32XX_UART5_SELECT + bool "Add support for standard UART5" + default y + help + Adds support for standard UART 5 when the 8250 serial support + is enabled. + +config ARCH_LPC32XX_UART6_SELECT + bool "Add support for standard UART6" + help + Adds support for standard UART 6 when the 8250 serial support + is enabled. + +endmenu + +endif diff --git a/trunk/arch/arm/mach-lpc32xx/Makefile.boot b/trunk/arch/arm/mach-lpc32xx/Makefile.boot index 697323b5f92d..2cfe0ee635c5 100644 --- a/trunk/arch/arm/mach-lpc32xx/Makefile.boot +++ b/trunk/arch/arm/mach-lpc32xx/Makefile.boot @@ -2,4 +2,3 @@ params_phys-y := 0x80000100 initrd_phys-y := 0x82000000 -dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb diff --git a/trunk/arch/arm/mach-lpc32xx/clock.c b/trunk/arch/arm/mach-lpc32xx/clock.c index 8a4e7cb74ae1..f6a3ffec1f4b 100644 --- a/trunk/arch/arm/mach-lpc32xx/clock.c +++ b/trunk/arch/arm/mach-lpc32xx/clock.c @@ -691,21 +691,10 @@ static struct clk clk_nand = { .parent = &clk_hclk, .enable = local_onoff_enable, .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN | - LPC32XX_CLKPWR_NANDCLK_SEL_SLC, + .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN, .get_rate = local_return_parent_rate, }; -static struct clk clk_nand_mlc = { - .parent = &clk_hclk, - .enable = local_onoff_enable, - .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN | - LPC32XX_CLKPWR_NANDCLK_DMA_INT | - LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC, - .get_rate = local_return_parent_rate, -}; - static struct clk clk_i2s0 = { .parent = &clk_hclk, .enable = local_onoff_enable, @@ -718,8 +707,7 @@ static struct clk clk_i2s1 = { .parent = &clk_hclk, .enable = local_onoff_enable, .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, - .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN | - LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA, + .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN, .get_rate = local_return_parent_rate, }; @@ -739,77 +727,14 @@ static struct clk clk_rtc = { .get_rate = local_return_parent_rate, }; -static int local_usb_enable(struct clk *clk, int enable) -{ - u32 tmp; - - if (enable) { - /* Set up I2C pull levels */ - tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); - tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE; - __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); - } - - return local_onoff_enable(clk, enable); -} - static struct clk clk_usbd = { .parent = &clk_usbpll, - .enable = local_usb_enable, + .enable = local_onoff_enable, .enable_reg = LPC32XX_CLKPWR_USB_CTRL, .enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN, .get_rate = local_return_parent_rate, }; -#define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \ - LPC32XX_USB_OTG_I2C_CLOCK_ON) - -static int local_usb_otg_enable(struct clk *clk, int enable) -{ - int to = 1000; - - if (enable) { - __raw_writel(clk->enable_mask, clk->enable_reg); - - while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & - clk->enable_mask) != clk->enable_mask) && (to > 0)) - to--; - } else { - __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg); - - while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) & - OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0)) - to--; - } - - if (to) - return 0; - else - return -1; -} - -static struct clk clk_usb_otg_dev = { - .parent = &clk_usbpll, - .enable = local_usb_otg_enable, - .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, - .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | - LPC32XX_USB_OTG_OTG_CLOCK_ON | - LPC32XX_USB_OTG_DEV_CLOCK_ON | - LPC32XX_USB_OTG_I2C_CLOCK_ON, - .get_rate = local_return_parent_rate, -}; - -static struct clk clk_usb_otg_host = { - .parent = &clk_usbpll, - .enable = local_usb_otg_enable, - .enable_reg = LPC32XX_USB_OTG_CLK_CTRL, - .enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON | - LPC32XX_USB_OTG_OTG_CLOCK_ON | - LPC32XX_USB_OTG_HOST_CLOCK_ON | - LPC32XX_USB_OTG_I2C_CLOCK_ON, - .get_rate = local_return_parent_rate, -}; - static int tsc_onoff_enable(struct clk *clk, int enable) { u32 tmp; @@ -875,17 +800,11 @@ static int mmc_onoff_enable(struct clk *clk, int enable) u32 tmp; tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & - ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN | - LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN | - LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS | - LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS | - LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS | - LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS); + ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN; /* If rate is 0, disable clock */ if (enable != 0) - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN | - LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN; + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN; __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); @@ -934,7 +853,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) static int mmc_set_rate(struct clk *clk, unsigned long rate) { - u32 tmp; + u32 oldclk, tmp; unsigned long prate, div, crate = mmc_round_rate(clk, rate); prate = clk->parent->get_rate(clk->parent); @@ -942,12 +861,16 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate) div = prate / crate; /* The MMC clock must be on when accessing an MMC register */ + oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL); + __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN, + LPC32XX_CLKPWR_MS_CTRL); tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) & ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf); - tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) | - LPC32XX_CLKPWR_MSCARD_SDCARD_EN; + tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div); __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL); + __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL); + return 0; } @@ -1197,9 +1120,8 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2), CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), - CLKDEV_INIT("40050000.key", NULL, &clk_kscan), - CLKDEV_INIT("20020000.flash", NULL, &clk_nand), - CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc), + CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), + CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand), CLKDEV_INIT("40048000.adc", NULL, &clk_adc), CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), @@ -1208,9 +1130,6 @@ static struct clk_lookup lookups[] = { CLKDEV_INIT("31060000.ethernet", NULL, &clk_net), CLKDEV_INIT("dev:clcd", NULL, &clk_lcd), CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd), - CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd), - CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev), - CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host), CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc), }; diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/gpio.h b/trunk/arch/arm/mach-lpc32xx/include/mach/gpio.h index 0052e7a76179..2ba6ca412bef 100644 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/gpio.h +++ b/trunk/arch/arm/mach-lpc32xx/include/mach/gpio.h @@ -3,4 +3,6 @@ #include "gpio-lpc32xx.h" +#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX) + #endif /* __MACH_GPIO_H */ diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/platform.h b/trunk/arch/arm/mach-lpc32xx/include/mach/platform.h index acc4aabf1c7b..c584f5bb164f 100644 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/platform.h +++ b/trunk/arch/arm/mach-lpc32xx/include/mach/platform.h @@ -694,18 +694,4 @@ #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) -/* - * USB Otg Registers - */ -#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) -#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) -#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) - -/* USB OTG CLK CTRL bit defines */ -#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) -#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) -#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) -#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) -#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) - #endif diff --git a/trunk/arch/arm/mach-lpc32xx/phy3250.c b/trunk/arch/arm/mach-lpc32xx/phy3250.c index b07dcc90829d..540106cdb9ec 100644 --- a/trunk/arch/arm/mach-lpc32xx/phy3250.c +++ b/trunk/arch/arm/mach-lpc32xx/phy3250.c @@ -30,13 +30,12 @@ #include #include #include -#include -#include #include #include #include #include #include +#include #include #include @@ -51,9 +50,9 @@ /* * Mapped GPIOLIB GPIOs */ -#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) -#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) -#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5) +#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) +#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) +#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) /* * AMBA LCD controller @@ -159,6 +158,24 @@ static struct clcd_board lpc32xx_clcd_data = { /* * AMBA SSP (SPI) */ +static void phy3250_spi_cs_set(u32 control) +{ + gpio_set_value(SPI0_CS_GPIO, (int) control); +} + +static struct pl022_config_chip spi0_chip_info = { + .com_mode = INTERRUPT_TRANSFER, + .iface = SSP_INTERFACE_MOTOROLA_SPI, + .hierarchy = SSP_MASTER, + .slave_tx_disable = 0, + .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM, + .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC, + .ctrl_len = SSP_BITS_8, + .wait_state = SSP_MWIRE_WAIT_ZERO, + .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, + .cs_control = phy3250_spi_cs_set, +}; + static struct pl022_ssp_controller lpc32xx_ssp0_data = { .bus_id = 0, .num_chipselect = 1, @@ -171,56 +188,45 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = { .enable_dma = 0, }; -static struct pl08x_channel_data pl08x_slave_channels[] = { - { - .bus_id = "nand-slc", - .min_signal = 1, /* SLC NAND Flash */ - .max_signal = 1, - .periph_buses = PL08X_AHB1, - }, - { - .bus_id = "nand-mlc", - .min_signal = 12, /* MLC NAND Flash */ - .max_signal = 12, - .periph_buses = PL08X_AHB1, - }, -}; - -static int pl08x_get_signal(const struct pl08x_channel_data *cd) -{ - return cd->min_signal; -} - -static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch) +/* AT25 driver registration */ +static int __init phy3250_spi_board_register(void) { +#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) + static struct spi_board_info info[] = { + { + .modalias = "spidev", + .max_speed_hz = 5000000, + .bus_num = 0, + .chip_select = 0, + .controller_data = &spi0_chip_info, + }, + }; + +#else + static struct spi_eeprom eeprom = { + .name = "at25256a", + .byte_len = 0x8000, + .page_size = 64, + .flags = EE_ADDR2, + }; + + static struct spi_board_info info[] = { + { + .modalias = "at25", + .max_speed_hz = 5000000, + .bus_num = 0, + .chip_select = 0, + .mode = SPI_MODE_0, + .platform_data = &eeprom, + .controller_data = &spi0_chip_info, + }, + }; +#endif + return spi_register_board_info(info, ARRAY_SIZE(info)); } +arch_initcall(phy3250_spi_board_register); static struct pl08x_platform_data pl08x_pd = { - .slave_channels = &pl08x_slave_channels[0], - .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels), - .get_signal = pl08x_get_signal, - .put_signal = pl08x_put_signal, - .lli_buses = PL08X_AHB1, - .mem_buses = PL08X_AHB1, -}; - -static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios) -{ - /* Only on and off are supported */ - if (ios->power_mode == MMC_POWER_OFF) - gpio_set_value(MMC_PWR_ENABLE_GPIO, 0); - else - gpio_set_value(MMC_PWR_ENABLE_GPIO, 1); - return 0; -} - -static struct mmci_platform_data lpc32xx_mmci_data = { - .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 | - MMC_VDD_32_33 | MMC_VDD_33_34, - .ios_handler = mmc_handle_ios, - .dma_filter = NULL, - /* No DMA for now since AMBA PL080 dmaengine driver only does scatter - * gather, and the MMCI driver doesn't do it this way */ }; static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { @@ -228,8 +234,6 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), - OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd", - &lpc32xx_mmci_data), { } }; @@ -237,6 +241,10 @@ static void __init lpc3250_machine_init(void) { u32 tmp; + /* Setup SLC NAND controller muxing */ + __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC, + LPC32XX_CLKPWR_NAND_CLK_CTRL); + /* Setup LCD muxing to RGB565 */ tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | @@ -244,8 +252,47 @@ static void __init lpc3250_machine_init(void) tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16; __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL); + /* Set up USB power */ + tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); + tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN | + LPC32XX_CLKPWR_USBCTRL_USBI2C_EN; + __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL); + + /* Set up I2C pull levels */ + tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL); + tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE | + LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; + __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); + + /* Disable IrDA pulsing support on UART6 */ + tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); + tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; + __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); + + /* Enable DMA for I2S1 channel */ + tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL); + tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA; + __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL); + lpc32xx_serial_init(); + /* + * AMBA peripheral clocks need to be enabled prior to AMBA device + * detection or a data fault will occur, so enable the clocks + * here. + */ + tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL); + __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN), + LPC32XX_CLKPWR_LCDCLK_CTRL); + + tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL); + __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN), + LPC32XX_CLKPWR_SSP_CLK_CTRL); + + tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL); + __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN), + LPC32XX_CLKPWR_DMA_CLK_CTRL); + /* Test clock needed for UDA1380 initial init */ __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN, @@ -255,10 +302,12 @@ static void __init lpc3250_machine_init(void) lpc32xx_auxdata_lookup, NULL); /* Register GPIOs used on this board */ - if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en")) - pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO); - else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1)) - pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO); + if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) + printk(KERN_ERR "Error requesting gpio %u", + SPI0_CS_GPIO); + else if (gpio_direction_output(SPI0_CS_GPIO, 1)) + printk(KERN_ERR "Error setting gpio %u to output", + SPI0_CS_GPIO); } static char const *lpc32xx_dt_compat[] __initdata = { diff --git a/trunk/arch/arm/mach-lpc32xx/serial.c b/trunk/arch/arm/mach-lpc32xx/serial.c index 05621a29fba2..f2735281616a 100644 --- a/trunk/arch/arm/mach-lpc32xx/serial.c +++ b/trunk/arch/arm/mach-lpc32xx/serial.c @@ -31,6 +31,59 @@ #define LPC32XX_SUART_FIFO_SIZE 64 +/* Standard 8250/16550 compatible serial ports */ +static struct plat_serial8250_port serial_std_platform_data[] = { +#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT + { + .membase = io_p2v(LPC32XX_UART5_BASE), + .mapbase = LPC32XX_UART5_BASE, + .irq = IRQ_LPC32XX_UART_IIR5, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT + { + .membase = io_p2v(LPC32XX_UART3_BASE), + .mapbase = LPC32XX_UART3_BASE, + .irq = IRQ_LPC32XX_UART_IIR3, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT + { + .membase = io_p2v(LPC32XX_UART4_BASE), + .mapbase = LPC32XX_UART4_BASE, + .irq = IRQ_LPC32XX_UART_IIR4, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT + { + .membase = io_p2v(LPC32XX_UART6_BASE), + .mapbase = LPC32XX_UART6_BASE, + .irq = IRQ_LPC32XX_UART_IIR6, + .uartclk = LPC32XX_MAIN_OSC_FREQ, + .regshift = 2, + .iotype = UPIO_MEM32, + .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | + UPF_SKIP_TEST, + }, +#endif + { }, +}; + struct uartinit { char *uart_ck_name; u32 ck_mode_mask; @@ -39,6 +92,7 @@ struct uartinit { }; static struct uartinit uartinit_data[] __initdata = { +#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT { .uart_ck_name = "uart5_ck", .ck_mode_mask = @@ -46,6 +100,8 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, .mapbase = LPC32XX_UART5_BASE, }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT { .uart_ck_name = "uart3_ck", .ck_mode_mask = @@ -53,6 +109,8 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, .mapbase = LPC32XX_UART3_BASE, }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT { .uart_ck_name = "uart4_ck", .ck_mode_mask = @@ -60,6 +118,8 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, .mapbase = LPC32XX_UART4_BASE, }, +#endif +#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT { .uart_ck_name = "uart6_ck", .ck_mode_mask = @@ -67,6 +127,19 @@ static struct uartinit uartinit_data[] __initdata = { .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, .mapbase = LPC32XX_UART6_BASE, }, +#endif +}; + +static struct platform_device serial_std_platform_device = { + .name = "serial8250", + .id = 0, + .dev = { + .platform_data = serial_std_platform_data, + }, +}; + +static struct platform_device *lpc32xx_serial_devs[] __initdata = { + &serial_std_platform_device, }; void __init lpc32xx_serial_init(void) @@ -83,8 +156,15 @@ void __init lpc32xx_serial_init(void) clk = clk_get(NULL, uartinit_data[i].uart_ck_name); if (!IS_ERR(clk)) { clk_enable(clk); + serial_std_platform_data[i].uartclk = + clk_get_rate(clk); } + /* Fall back on main osc rate if clock rate return fails */ + if (serial_std_platform_data[i].uartclk == 0) + serial_std_platform_data[i].uartclk = + LPC32XX_MAIN_OSC_FREQ; + /* Setup UART clock modes for all UARTs, disable autoclock */ clkmodes |= uartinit_data[i].ck_mode_mask; @@ -109,7 +189,7 @@ void __init lpc32xx_serial_init(void) __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { /* Force a flush of the RX FIFOs to work around a HW bug */ - puart = uartinit_data[i].mapbase; + puart = serial_std_platform_data[i].mapbase; __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); j = LPC32XX_SUART_FIFO_SIZE; @@ -118,13 +198,11 @@ void __init lpc32xx_serial_init(void) __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); } - /* Disable IrDA pulsing support on UART6 */ - tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); - tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS; - __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); - /* Disable UART5->USB transparent mode or USB won't work */ tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); + + platform_add_devices(lpc32xx_serial_devs, + ARRAY_SIZE(lpc32xx_serial_devs)); } diff --git a/trunk/arch/arm/mach-nomadik/Makefile b/trunk/arch/arm/mach-nomadik/Makefile index a42c9a33d3bf..a6bbd1a7b4e7 100644 --- a/trunk/arch/arm/mach-nomadik/Makefile +++ b/trunk/arch/arm/mach-nomadik/Makefile @@ -7,6 +7,8 @@ # Object file lists. +obj-y += clock.o + # Cpu revision obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o diff --git a/trunk/arch/arm/mach-nomadik/board-nhk8815.c b/trunk/arch/arm/mach-nomadik/board-nhk8815.c index f4535a7dadf5..2e8d3e176bc7 100644 --- a/trunk/arch/arm/mach-nomadik/board-nhk8815.c +++ b/trunk/arch/arm/mach-nomadik/board-nhk8815.c @@ -14,14 +14,12 @@ #include #include #include -#include #include #include #include #include #include #include -#include #include #include #include @@ -187,28 +185,16 @@ static void __init nhk8815_onenand_init(void) #endif } -static struct mmci_platform_data mmcsd_plat_data = { - .ocr_mask = MMC_VDD_29_30, - .f_max = 48000000, - .gpio_wp = -1, - .gpio_cd = 111, - .cd_invert = true, - .capabilities = MMC_CAP_MMC_HIGHSPEED | - MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA, -}; +static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE, + { IRQ_UART0 }, NULL); -static int __init nhk8815_mmcsd_init(void) -{ - int ret; +static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE, + { IRQ_UART1 }, NULL); - ret = gpio_request(112, "card detect bias"); - if (ret) - return ret; - gpio_direction_output(112, 0); - amba_apb_device_add(NULL, "mmci", NOMADIK_SDI_BASE, SZ_4K, IRQ_SDMMC, 0, &mmcsd_plat_data, 0x10180180); - return 0; -} -module_init(nhk8815_mmcsd_init); +static struct amba_device *amba_devs[] __initdata = { + &uart0_device, + &uart1_device, +}; static struct resource nhk8815_eth_resources[] = { { @@ -267,46 +253,17 @@ static struct sys_timer nomadik_timer = { .init = nomadik_timer_init, }; -static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = { - { - I2C_BOARD_INFO("stw4811", 0x2d), - }, -}; - -static struct i2c_board_info __initdata nhk8815_i2c1_devices[] = { - { - I2C_BOARD_INFO("camera", 0x10), - }, - { - I2C_BOARD_INFO("stw5095", 0x1a), - }, - { - I2C_BOARD_INFO("lis3lv02dl", 0x1d), - }, -}; - -static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = { - { - I2C_BOARD_INFO("stw4811-usb", 0x2d), - }, -}; - static void __init nhk8815_platform_init(void) { + int i; + cpu8815_platform_init(); nhk8815_onenand_init(); platform_add_devices(nhk8815_platform_devices, ARRAY_SIZE(nhk8815_platform_devices)); - amba_apb_device_add(NULL, "uart0", NOMADIK_UART0_BASE, SZ_4K, IRQ_UART0, 0, NULL, 0); - amba_apb_device_add(NULL, "uart1", NOMADIK_UART1_BASE, SZ_4K, IRQ_UART1, 0, NULL, 0); - - i2c_register_board_info(0, nhk8815_i2c0_devices, - ARRAY_SIZE(nhk8815_i2c0_devices)); - i2c_register_board_info(1, nhk8815_i2c1_devices, - ARRAY_SIZE(nhk8815_i2c1_devices)); - i2c_register_board_info(2, nhk8815_i2c2_devices, - ARRAY_SIZE(nhk8815_i2c2_devices)); + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); } MACHINE_START(NOMADIK, "NHK8815") diff --git a/trunk/arch/arm/mach-nomadik/clock.c b/trunk/arch/arm/mach-nomadik/clock.c new file mode 100644 index 000000000000..48a59f24e10c --- /dev/null +++ b/trunk/arch/arm/mach-nomadik/clock.c @@ -0,0 +1,75 @@ +/* + * linux/arch/arm/mach-nomadik/clock.c + * + * Copyright (C) 2009 Alessandro Rubini + */ +#include +#include +#include +#include +#include +#include "clock.h" + +/* + * The nomadik board uses generic clocks, but the serial pl011 file + * calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them + */ +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} +EXPORT_SYMBOL(clk_get_rate); + +/* enable and disable do nothing */ +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + +static struct clk clk_24 = { + .rate = 2400000, +}; + +static struct clk clk_48 = { + .rate = 48 * 1000 * 1000, +}; + +/* + * Catch-all default clock to satisfy drivers using the clk API. We don't + * model the actual hardware clocks yet. + */ +static struct clk clk_default; + +#define CLK(_clk, dev) \ + { \ + .clk = _clk, \ + .dev_id = dev, \ + } + +static struct clk_lookup lookups[] = { + { + .con_id = "apb_pclk", + .clk = &clk_default, + }, + CLK(&clk_24, "mtu0"), + CLK(&clk_24, "mtu1"), + CLK(&clk_48, "uart0"), + CLK(&clk_48, "uart1"), + CLK(&clk_default, "gpio.0"), + CLK(&clk_default, "gpio.1"), + CLK(&clk_default, "gpio.2"), + CLK(&clk_default, "gpio.3"), + CLK(&clk_default, "rng"), +}; + +int __init clk_init(void) +{ + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); + return 0; +} diff --git a/trunk/arch/arm/mach-nomadik/clock.h b/trunk/arch/arm/mach-nomadik/clock.h new file mode 100644 index 000000000000..78da2e7c3985 --- /dev/null +++ b/trunk/arch/arm/mach-nomadik/clock.h @@ -0,0 +1,15 @@ + +/* + * linux/arch/arm/mach-nomadik/clock.h + * + * Copyright (C) 2009 Alessandro Rubini + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +struct clk { + unsigned long rate; +}; + +int __init clk_init(void); diff --git a/trunk/arch/arm/mach-nomadik/cpu-8815.c b/trunk/arch/arm/mach-nomadik/cpu-8815.c index 6fd8e46567a4..27f43a46985e 100644 --- a/trunk/arch/arm/mach-nomadik/cpu-8815.c +++ b/trunk/arch/arm/mach-nomadik/cpu-8815.c @@ -22,10 +22,6 @@ #include #include #include -#include -#include -#include -#include #include #include @@ -36,63 +32,91 @@ #include #include +#include "clock.h" #include "cpu-8815.h" +#define __MEM_4K_RESOURCE(x) \ + .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM} + /* The 8815 has 4 GPIO blocks, let's register them immediately */ -static resource_size_t __initdata cpu8815_gpio_base[] = { - NOMADIK_GPIO0_BASE, - NOMADIK_GPIO1_BASE, - NOMADIK_GPIO2_BASE, - NOMADIK_GPIO3_BASE, + +#define GPIO_RESOURCE(block) \ + { \ + .start = NOMADIK_GPIO##block##_BASE, \ + .end = NOMADIK_GPIO##block##_BASE + SZ_4K - 1, \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = IRQ_GPIO##block, \ + .end = IRQ_GPIO##block, \ + .flags = IORESOURCE_IRQ, \ + } + +#define GPIO_DEVICE(block) \ + { \ + .name = "gpio", \ + .id = block, \ + .num_resources = 2, \ + .resource = &cpu8815_gpio_resources[block * 2], \ + .dev = { \ + .platform_data = &cpu8815_gpio[block], \ + }, \ + } + +static struct nmk_gpio_platform_data cpu8815_gpio[] = { + { + .name = "GPIO-0-31", + .first_gpio = 0, + .first_irq = NOMADIK_GPIO_TO_IRQ(0), + }, { + .name = "GPIO-32-63", + .first_gpio = 32, + .first_irq = NOMADIK_GPIO_TO_IRQ(32), + }, { + .name = "GPIO-64-95", + .first_gpio = 64, + .first_irq = NOMADIK_GPIO_TO_IRQ(64), + }, { + .name = "GPIO-96-127", /* 124..127 not routed to pin */ + .first_gpio = 96, + .first_irq = NOMADIK_GPIO_TO_IRQ(96), + } }; -static struct platform_device * -cpu8815_add_gpio(int id, resource_size_t addr, int irq, - struct nmk_gpio_platform_data *pdata) -{ - struct resource resources[] = { - { - .start = addr, - .end = addr + 127, - .flags = IORESOURCE_MEM, - }, - { - .start = irq, - .end = irq, - .flags = IORESOURCE_IRQ, - } - }; - - return platform_device_register_resndata(NULL, "gpio", id, - resources, ARRAY_SIZE(resources), - pdata, sizeof(*pdata)); -} +static struct resource cpu8815_gpio_resources[] = { + GPIO_RESOURCE(0), + GPIO_RESOURCE(1), + GPIO_RESOURCE(2), + GPIO_RESOURCE(3), +}; -void cpu8815_add_gpios(resource_size_t *base, int num, int irq, - struct nmk_gpio_platform_data *pdata) -{ - int first = 0; - int i; +static struct platform_device cpu8815_platform_gpio[] = { + GPIO_DEVICE(0), + GPIO_DEVICE(1), + GPIO_DEVICE(2), + GPIO_DEVICE(3), +}; - for (i = 0; i < num; i++, first += 32, irq++) { - pdata->first_gpio = first; - pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first); - pdata->num_gpio = 32; +static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL); - cpu8815_add_gpio(i, base[i], irq, pdata); - } -} +static struct platform_device *platform_devs[] __initdata = { + cpu8815_platform_gpio + 0, + cpu8815_platform_gpio + 1, + cpu8815_platform_gpio + 2, + cpu8815_platform_gpio + 3, +}; + +static struct amba_device *amba_devs[] __initdata = { + &cpu8815_amba_rng_device +}; static int __init cpu8815_init(void) { - struct nmk_gpio_platform_data pdata = { - /* No custom data yet */ - }; - - cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base), - IRQ_GPIO0, &pdata); - amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0); - amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0); + int i; + + platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) + amba_device_register(amba_devs[i], &iomem_resource); return 0; } arch_initcall(cpu8815_init); @@ -123,7 +147,7 @@ void __init cpu8815_init_irq(void) * Init clocks here so that they are available for system timer * initialization. */ - nomadik_clk_init(); + clk_init(); } /* diff --git a/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c b/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c index 6d14454d4609..0fc2f6f1cc97 100644 --- a/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c +++ b/trunk/arch/arm/mach-nomadik/i2c-8815nhk.c @@ -5,7 +5,6 @@ #include #include #include -#include /* * There are two busses in the 8815NHK. @@ -13,27 +12,19 @@ * use bit-bang through GPIO by now, to keep things simple */ -/* I2C0 connected to the STw4811 power management chip */ static struct i2c_gpio_platform_data nhk8815_i2c_data0 = { /* keep defaults for timeouts; pins are push-pull bidirectional */ .scl_pin = 62, .sda_pin = 63, }; -/* I2C1 connected to various sensors */ static struct i2c_gpio_platform_data nhk8815_i2c_data1 = { /* keep defaults for timeouts; pins are push-pull bidirectional */ .scl_pin = 53, .sda_pin = 54, }; -/* I2C2 connected to the USB portions of the STw4811 only */ -static struct i2c_gpio_platform_data nhk8815_i2c_data2 = { - /* keep defaults for timeouts; pins are push-pull bidirectional */ - .scl_pin = 73, - .sda_pin = 74, -}; - +/* first bus: GPIO XX and YY */ static struct platform_device nhk8815_i2c_dev0 = { .name = "i2c-gpio", .id = 0, @@ -41,7 +32,7 @@ static struct platform_device nhk8815_i2c_dev0 = { .platform_data = &nhk8815_i2c_data0, }, }; - +/* second bus: GPIO XX and YY */ static struct platform_device nhk8815_i2c_dev1 = { .name = "i2c-gpio", .id = 1, @@ -50,29 +41,15 @@ static struct platform_device nhk8815_i2c_dev1 = { }, }; -static struct platform_device nhk8815_i2c_dev2 = { - .name = "i2c-gpio", - .id = 2, - .dev = { - .platform_data = &nhk8815_i2c_data2, - }, -}; - -static pin_cfg_t cpu8815_pins_i2c[] = { - PIN_CFG_INPUT(62, GPIO, PULLUP), - PIN_CFG_INPUT(63, GPIO, PULLUP), - PIN_CFG_INPUT(53, GPIO, PULLUP), - PIN_CFG_INPUT(54, GPIO, PULLUP), - PIN_CFG_INPUT(73, GPIO, PULLUP), - PIN_CFG_INPUT(74, GPIO, PULLUP), -}; - static int __init nhk8815_i2c_init(void) { - nmk_config_pins(cpu8815_pins_i2c, ARRAY_SIZE(cpu8815_pins_i2c)); + nmk_gpio_set_mode(nhk8815_i2c_data0.scl_pin, NMK_GPIO_ALT_GPIO); + nmk_gpio_set_mode(nhk8815_i2c_data0.sda_pin, NMK_GPIO_ALT_GPIO); platform_device_register(&nhk8815_i2c_dev0); + + nmk_gpio_set_mode(nhk8815_i2c_data1.scl_pin, NMK_GPIO_ALT_GPIO); + nmk_gpio_set_mode(nhk8815_i2c_data1.sda_pin, NMK_GPIO_ALT_GPIO); platform_device_register(&nhk8815_i2c_dev1); - platform_device_register(&nhk8815_i2c_dev2); return 0; } @@ -81,7 +58,6 @@ static void __exit nhk8815_i2c_exit(void) { platform_device_unregister(&nhk8815_i2c_dev0); platform_device_unregister(&nhk8815_i2c_dev1); - platform_device_unregister(&nhk8815_i2c_dev2); return; } diff --git a/trunk/arch/arm/mach-nomadik/include/mach/irqs.h b/trunk/arch/arm/mach-nomadik/include/mach/irqs.h index a118e615f865..8faabc560398 100644 --- a/trunk/arch/arm/mach-nomadik/include/mach/irqs.h +++ b/trunk/arch/arm/mach-nomadik/include/mach/irqs.h @@ -22,56 +22,56 @@ #include -#define IRQ_VIC_START 1 /* first VIC interrupt is 1 */ +#define IRQ_VIC_START 0 /* first VIC interrupt is 0 */ /* * Interrupt numbers generic for all Nomadik Chip cuts */ -#define IRQ_WATCHDOG 1 -#define IRQ_SOFTINT 2 -#define IRQ_CRYPTO 3 -#define IRQ_OWM 4 -#define IRQ_MTU0 5 -#define IRQ_MTU1 6 -#define IRQ_GPIO0 7 -#define IRQ_GPIO1 8 -#define IRQ_GPIO2 9 -#define IRQ_GPIO3 10 -#define IRQ_RTC_RTT 11 -#define IRQ_SSP 12 -#define IRQ_UART0 13 -#define IRQ_DMA1 14 -#define IRQ_CLCD_MDIF 15 -#define IRQ_DMA0 16 -#define IRQ_PWRFAIL 17 -#define IRQ_UART1 18 -#define IRQ_FIRDA 19 -#define IRQ_MSP0 20 -#define IRQ_I2C0 21 -#define IRQ_I2C1 22 -#define IRQ_SDMMC 23 -#define IRQ_USBOTG 24 -#define IRQ_SVA_IT0 25 -#define IRQ_SVA_IT1 26 -#define IRQ_SAA_IT0 27 -#define IRQ_SAA_IT1 28 -#define IRQ_UART2 29 -#define IRQ_MSP2 30 -#define IRQ_L2CC 49 -#define IRQ_HPI 50 -#define IRQ_SKE 51 -#define IRQ_KP 52 -#define IRQ_MEMST 55 -#define IRQ_SGA_IT 59 -#define IRQ_USBM 61 -#define IRQ_MSP1 63 +#define IRQ_WATCHDOG 0 +#define IRQ_SOFTINT 1 +#define IRQ_CRYPTO 2 +#define IRQ_OWM 3 +#define IRQ_MTU0 4 +#define IRQ_MTU1 5 +#define IRQ_GPIO0 6 +#define IRQ_GPIO1 7 +#define IRQ_GPIO2 8 +#define IRQ_GPIO3 9 +#define IRQ_RTC_RTT 10 +#define IRQ_SSP 11 +#define IRQ_UART0 12 +#define IRQ_DMA1 13 +#define IRQ_CLCD_MDIF 14 +#define IRQ_DMA0 15 +#define IRQ_PWRFAIL 16 +#define IRQ_UART1 17 +#define IRQ_FIRDA 18 +#define IRQ_MSP0 19 +#define IRQ_I2C0 20 +#define IRQ_I2C1 21 +#define IRQ_SDMMC 22 +#define IRQ_USBOTG 23 +#define IRQ_SVA_IT0 24 +#define IRQ_SVA_IT1 25 +#define IRQ_SAA_IT0 26 +#define IRQ_SAA_IT1 27 +#define IRQ_UART2 28 +#define IRQ_MSP2 31 +#define IRQ_L2CC 48 +#define IRQ_HPI 49 +#define IRQ_SKE 50 +#define IRQ_KP 51 +#define IRQ_MEMST 54 +#define IRQ_SGA_IT 58 +#define IRQ_USBM 60 +#define IRQ_MSP1 62 -#define NOMADIK_GPIO_OFFSET (IRQ_VIC_START+64) +#define NOMADIK_SOC_NR_IRQS 64 /* After chip-specific IRQ numbers we have the GPIO ones */ #define NOMADIK_NR_GPIO 128 /* last 4 not wired to pins */ -#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_GPIO_OFFSET) -#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_GPIO_OFFSET) +#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + NOMADIK_SOC_NR_IRQS) +#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - NOMADIK_SOC_NR_IRQS) #define NR_IRQS NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO) /* Following two are used by entry_macro.S, to access our dual-vic */ @@ -79,3 +79,4 @@ #define VIC_REG_IRQSR1 0x20 #endif /* __ASM_ARCH_IRQS_H */ + diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index a4cf93242b0b..fa742f3c2629 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -90,7 +90,6 @@ obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += prcm.o cminst44xx.o cm44xx.o obj-$(CONFIG_ARCH_OMAP4) += prcm_mpu44xx.o prminst44xx.o obj-$(CONFIG_ARCH_OMAP4) += vc44xx_data.o vp44xx_data.o prm44xx.o -obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -100,7 +99,6 @@ obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o @@ -115,8 +113,6 @@ obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o -obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -133,8 +129,6 @@ obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o -obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o diff --git a/trunk/arch/arm/mach-omap2/board-generic.c b/trunk/arch/arm/mach-omap2/board-generic.c index 2f2abfb82d84..202934657867 100644 --- a/trunk/arch/arm/mach-omap2/board-generic.c +++ b/trunk/arch/arm/mach-omap2/board-generic.c @@ -112,24 +112,6 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") MACHINE_END #endif -#ifdef CONFIG_SOC_AM33XX -static const char *am33xx_boards_compat[] __initdata = { - "ti,am33xx", - NULL, -}; - -DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)") - .reserve = omap_reserve, - .map_io = am33xx_map_io, - .init_early = am33xx_init_early, - .init_irq = omap_init_irq, - .handle_irq = omap3_intc_handle_irq, - .init_machine = omap_generic_init, - .timer = &omap3_am33xx_timer, - .dt_compat = am33xx_boards_compat, -MACHINE_END -#endif - #ifdef CONFIG_ARCH_OMAP4 static const char *omap4_boards_compat[] __initdata = { "ti,omap4", diff --git a/trunk/arch/arm/mach-omap2/clockdomain.h b/trunk/arch/arm/mach-omap2/clockdomain.h index 72cb12bbb9c3..f7b58609bad8 100644 --- a/trunk/arch/arm/mach-omap2/clockdomain.h +++ b/trunk/arch/arm/mach-omap2/clockdomain.h @@ -195,7 +195,6 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); extern void __init omap3xxx_clockdomains_init(void); -extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void _clkdm_add_autodeps(struct clockdomain *clkdm); extern void _clkdm_del_autodeps(struct clockdomain *clkdm); @@ -203,7 +202,6 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm); extern struct clkdm_ops omap2_clkdm_operations; extern struct clkdm_ops omap3_clkdm_operations; extern struct clkdm_ops omap4_clkdm_operations; -extern struct clkdm_ops am33xx_clkdm_operations; extern struct clkdm_dep gfx_24xx_wkdeps[]; extern struct clkdm_dep dsp_24xx_wkdeps[]; diff --git a/trunk/arch/arm/mach-omap2/clockdomain33xx.c b/trunk/arch/arm/mach-omap2/clockdomain33xx.c deleted file mode 100644 index aca6388fad76..000000000000 --- a/trunk/arch/arm/mach-omap2/clockdomain33xx.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * AM33XX clockdomain control - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath - * - * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include "clockdomain.h" -#include "cm33xx.h" - - -static int am33xx_clkdm_sleep(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs); - return 0; -} - -static int am33xx_clkdm_wakeup(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs); - return 0; -} - -static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); -} - -static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm) -{ - am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); -} - -static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm) -{ - if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) - return am33xx_clkdm_wakeup(clkdm); - - return 0; -} - -static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) -{ - bool hwsup = false; - - hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs); - - if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) - am33xx_clkdm_sleep(clkdm); - - return 0; -} - -struct clkdm_ops am33xx_clkdm_operations = { - .clkdm_sleep = am33xx_clkdm_sleep, - .clkdm_wakeup = am33xx_clkdm_wakeup, - .clkdm_allow_idle = am33xx_clkdm_allow_idle, - .clkdm_deny_idle = am33xx_clkdm_deny_idle, - .clkdm_clk_enable = am33xx_clkdm_clk_enable, - .clkdm_clk_disable = am33xx_clkdm_clk_disable, -}; diff --git a/trunk/arch/arm/mach-omap2/clockdomains33xx_data.c b/trunk/arch/arm/mach-omap2/clockdomains33xx_data.c deleted file mode 100644 index 32c90fd9eba2..000000000000 --- a/trunk/arch/arm/mach-omap2/clockdomains33xx_data.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * AM33XX Clock Domain data. - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "clockdomain.h" -#include "cm.h" -#include "cm33xx.h" -#include "cm-regbits-33xx.h" - -static struct clockdomain l4ls_am33xx_clkdm = { - .name = "l4ls_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l3s_am33xx_clkdm = { - .name = "l3s_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4fw_am33xx_clkdm = { - .name = "l4fw_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l3_am33xx_clkdm = { - .name = "l3_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4hs_am33xx_clkdm = { - .name = "l4hs_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain ocpwp_l3_am33xx_clkdm = { - .name = "ocpwp_l3_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain pruss_ocp_am33xx_clkdm = { - .name = "pruss_ocp_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain cpsw_125mhz_am33xx_clkdm = { - .name = "cpsw_125mhz_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain lcdc_am33xx_clkdm = { - .name = "lcdc_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain clk_24mhz_am33xx_clkdm = { - .name = "clk_24mhz_clkdm", - .pwrdm = { .name = "per_pwrdm" }, - .cm_inst = AM33XX_CM_PER_MOD, - .clkdm_offs = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4_wkup_am33xx_clkdm = { - .name = "l4_wkup_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .cm_inst = AM33XX_CM_WKUP_MOD, - .clkdm_offs = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l3_aon_am33xx_clkdm = { - .name = "l3_aon_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .cm_inst = AM33XX_CM_WKUP_MOD, - .clkdm_offs = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4_wkup_aon_am33xx_clkdm = { - .name = "l4_wkup_aon_clkdm", - .pwrdm = { .name = "wkup_pwrdm" }, - .cm_inst = AM33XX_CM_WKUP_MOD, - .clkdm_offs = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain mpu_am33xx_clkdm = { - .name = "mpu_clkdm", - .pwrdm = { .name = "mpu_pwrdm" }, - .cm_inst = AM33XX_CM_MPU_MOD, - .clkdm_offs = AM33XX_CM_MPU_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4_rtc_am33xx_clkdm = { - .name = "l4_rtc_clkdm", - .pwrdm = { .name = "rtc_pwrdm" }, - .cm_inst = AM33XX_CM_RTC_MOD, - .clkdm_offs = AM33XX_CM_RTC_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain gfx_l3_am33xx_clkdm = { - .name = "gfx_l3_clkdm", - .pwrdm = { .name = "gfx_pwrdm" }, - .cm_inst = AM33XX_CM_GFX_MOD, - .clkdm_offs = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = { - .name = "gfx_l4ls_gfx_clkdm", - .pwrdm = { .name = "gfx_pwrdm" }, - .cm_inst = AM33XX_CM_GFX_MOD, - .clkdm_offs = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain l4_cefuse_am33xx_clkdm = { - .name = "l4_cefuse_clkdm", - .pwrdm = { .name = "cefuse_pwrdm" }, - .cm_inst = AM33XX_CM_CEFUSE_MOD, - .clkdm_offs = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET, - .flags = CLKDM_CAN_SWSUP, -}; - -static struct clockdomain *clockdomains_am33xx[] __initdata = { - &l4ls_am33xx_clkdm, - &l3s_am33xx_clkdm, - &l4fw_am33xx_clkdm, - &l3_am33xx_clkdm, - &l4hs_am33xx_clkdm, - &ocpwp_l3_am33xx_clkdm, - &pruss_ocp_am33xx_clkdm, - &cpsw_125mhz_am33xx_clkdm, - &lcdc_am33xx_clkdm, - &clk_24mhz_am33xx_clkdm, - &l4_wkup_am33xx_clkdm, - &l3_aon_am33xx_clkdm, - &l4_wkup_aon_am33xx_clkdm, - &mpu_am33xx_clkdm, - &l4_rtc_am33xx_clkdm, - &gfx_l3_am33xx_clkdm, - &gfx_l4ls_gfx_am33xx_clkdm, - &l4_cefuse_am33xx_clkdm, - NULL, -}; - -void __init am33xx_clockdomains_init(void) -{ - clkdm_register_platform_funcs(&am33xx_clkdm_operations); - clkdm_register_clkdms(clockdomains_am33xx); - clkdm_complete_init(); -} diff --git a/trunk/arch/arm/mach-omap2/cm-regbits-33xx.h b/trunk/arch/arm/mach-omap2/cm-regbits-33xx.h deleted file mode 100644 index 532027ee3d8d..000000000000 --- a/trunk/arch/arm/mach-omap2/cm-regbits-33xx.h +++ /dev/null @@ -1,687 +0,0 @@ -/* - * AM33XX Power Management register bits - * - * This file is automatically generated from the AM33XX hardware databases. - * Vaibhav Hiremath - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H -#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H - -/* - * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, - * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER - */ -#define AM33XX_AUTO_DPLL_MODE_SHIFT 0 -#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) - -/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_CPSW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 -#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3S_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4FW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) - -/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) - -/* Used by CM_L4_WKUP_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 -#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 -#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) - -/* Used by CM_MPU_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 -#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 -#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 -#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) - -/* Used by CM_CLKOUT_CTRL */ -#define AM33XX_CLKOUT2DIV_SHIFT 3 -#define AM33XX_CLKOUT2DIV_MASK (0x05 << 3) - -/* Used by CM_CLKOUT_CTRL */ -#define AM33XX_CLKOUT2EN_SHIFT 7 -#define AM33XX_CLKOUT2EN_MASK (1 << 7) - -/* Used by CM_CLKOUT_CTRL */ -#define AM33XX_CLKOUT2SOURCE_SHIFT 0 -#define AM33XX_CLKOUT2SOURCE_MASK (0x02 << 0) - -/* - * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, - * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, - * CLKSEL_TIMER7_CLK - */ -#define AM33XX_CLKSEL_SHIFT 0 -#define AM33XX_CLKSEL_MASK (0x01 << 0) - -/* - * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, - * CM_CPTS_RFT_CLKSEL - */ -#define AM33XX_CLKSEL_0_0_SHIFT 0 -#define AM33XX_CLKSEL_0_0_MASK (1 << 0) - -#define AM33XX_CLKSEL_0_1_SHIFT 0 -#define AM33XX_CLKSEL_0_1_MASK (3 << 0) - -/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ -#define AM33XX_CLKSEL_0_2_SHIFT 0 -#define AM33XX_CLKSEL_0_2_MASK (7 << 0) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 -#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) - -/* - * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, - * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, - * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, - * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, - * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, - * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL - */ -#define AM33XX_CLKTRCTRL_SHIFT 0 -#define AM33XX_CLKTRCTRL_MASK (0x3 << 0) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, - * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, - * CM_SSC_DELTAMSTEP_DPLL_PER - */ -#define AM33XX_DELTAMSTEP_SHIFT 0 -#define AM33XX_DELTAMSTEP_MASK (0x19 << 0) - -/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ -#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 -#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 -#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ -#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 -#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x06 << 0) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) - -/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) - -/* - * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER - */ -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) - -/* - * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, - * CM_CLKSEL_DPLL_MPU - */ -#define AM33XX_DPLL_DIV_SHIFT 0 -#define AM33XX_DPLL_DIV_MASK (0x7f << 0) - -#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) - -/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_DIV_0_7_SHIFT 0 -#define AM33XX_DPLL_DIV_0_7_MASK (0x07 << 0) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_EN_SHIFT 0 -#define AM33XX_DPLL_EN_MASK (0x7 << 0) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_LPMODE_EN_SHIFT 10 -#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) - -/* - * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, - * CM_CLKSEL_DPLL_MPU - */ -#define AM33XX_DPLL_MULT_SHIFT 8 -#define AM33XX_DPLL_MULT_MASK (0x7ff << 8) - -/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 -#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_REGM4XEN_SHIFT 11 -#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_SD_DIV_SHIFT 24 -#define AM33XX_DPLL_SD_DIV_MASK (24, 31) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_ACK_SHIFT 13 -#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_EN_SHIFT 12 -#define AM33XX_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 -#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 -#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x04 << 0) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, - * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, - * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, - * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, - * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, - * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, - * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, - * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, - * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, - * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, - * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, - * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, - * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, - * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, - * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, - * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, - * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, - * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, - * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, - * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, - * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, - * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, - * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, - * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL - */ -#define AM33XX_IDLEST_SHIFT 16 -#define AM33XX_IDLEST_MASK (0x3 << 16) -#define AM33XX_IDLEST_VAL 0x3 - -/* Used by CM_MAC_CLKSEL */ -#define AM33XX_MII_CLK_SEL_SHIFT 2 -#define AM33XX_MII_CLK_SEL_MASK (1 << 2) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, - * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER - */ -#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x10 << 8) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, - * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER - */ -#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x06 << 0) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, - * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, - * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, - * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, - * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, - * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, - * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, - * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, - * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, - * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, - * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, - * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, - * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, - * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, - * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, - * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, - * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, - * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, - * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, - * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, - * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, - * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, - * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, - * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, - * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, - * CM_CEFUSE_CEFUSE_CLKCTRL - */ -#define AM33XX_MODULEMODE_SHIFT 0 -#define AM33XX_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 -#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 -#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) - -/* Used by CM_WKUP_GPIO0_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO1_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO2_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO3_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO4_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO5_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO6_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, - * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, - * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, - * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL - */ -#define AM33XX_STBYST_SHIFT 18 -#define AM33XX_STBYST_MASK (1 << 18) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 -#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x29 << 27) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_STM_PMD_CLKSEL_SHIFT 22 -#define AM33XX_STM_PMD_CLKSEL_MASK (0x23 << 22) - -/* - * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER - */ -#define AM33XX_ST_DPLL_CLK_SHIFT 0 -#define AM33XX_ST_DPLL_CLK_MASK (1 << 0) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 -#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) - -/* - * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER - */ -#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 -#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER - */ -#define AM33XX_ST_MN_BYPASS_SHIFT 8 -#define AM33XX_ST_MN_BYPASS_MASK (1 << 8) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 -#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x26 << 24) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ -#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 -#define AM33XX_TRC_PMD_CLKSEL_MASK (0x21 << 20) - -/* Used by CONTROL_SEC_CLK_CTRL */ -#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) -#endif diff --git a/trunk/arch/arm/mach-omap2/cm33xx.c b/trunk/arch/arm/mach-omap2/cm33xx.c deleted file mode 100644 index 13f56eafef03..000000000000 --- a/trunk/arch/arm/mach-omap2/cm33xx.c +++ /dev/null @@ -1,313 +0,0 @@ -/* - * AM33XX CM functions - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath - * - * Reference taken from from OMAP4 cminst44xx.c - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -#include "cm.h" -#include "cm33xx.h" -#include "cm-regbits-34xx.h" -#include "cm-regbits-33xx.h" -#include "prm33xx.h" - -/* - * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield: - * - * 0x0 func: Module is fully functional, including OCP - * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep - * abortion - * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if - * using separate functional clock - * 0x3 disabled: Module is disabled and cannot be accessed - * - */ -#define CLKCTRL_IDLEST_FUNCTIONAL 0x0 -#define CLKCTRL_IDLEST_INTRANSITION 0x1 -#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2 -#define CLKCTRL_IDLEST_DISABLED 0x3 - -/* Private functions */ - -/* Read a register in a CM instance */ -static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx) -{ - return __raw_readl(cm_base + inst + idx); -} - -/* Write into a register in a CM */ -static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx) -{ - __raw_writel(val, cm_base + inst + idx); -} - -/* Read-modify-write a register in CM */ -static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) -{ - u32 v; - - v = am33xx_cm_read_reg(inst, idx); - v &= ~mask; - v |= bits; - am33xx_cm_write_reg(v, inst, idx); - - return v; -} - -static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx) -{ - return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx); -} - -static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx) -{ - return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx); -} - -static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask) -{ - u32 v; - - v = am33xx_cm_read_reg(inst, idx); - v &= mask; - v >>= __ffs(mask); - - return v; -} - -/** - * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) - * - * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to - * bit 0. - */ -static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs) -{ - u32 v = am33xx_cm_read_reg(inst, clkctrl_offs); - v &= AM33XX_IDLEST_MASK; - v >>= AM33XX_IDLEST_SHIFT; - return v; -} - -/** - * _is_module_ready - can module registers be accessed without causing an abort? - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) - * - * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either - * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise. - */ -static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) -{ - u32 v; - - v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs); - - return (v == CLKCTRL_IDLEST_FUNCTIONAL || - v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false; -} - -/** - * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield - * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted) - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * - * @c must be the unshifted value for CLKTRCTRL - i.e., this function - * will handle the shift itself. - */ -static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs) -{ - u32 v; - - v = am33xx_cm_read_reg(inst, cdoffs); - v &= ~AM33XX_CLKTRCTRL_MASK; - v |= c << AM33XX_CLKTRCTRL_SHIFT; - am33xx_cm_write_reg(v, inst, cdoffs); -} - -/* Public functions */ - -/** - * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode? - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * - * Returns true if the clockdomain referred to by (@inst, @cdoffs) - * is in hardware-supervised idle mode, or 0 otherwise. - */ -bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs) -{ - u32 v; - - v = am33xx_cm_read_reg(inst, cdoffs); - v &= AM33XX_CLKTRCTRL_MASK; - v >>= AM33XX_CLKTRCTRL_SHIFT; - - return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false; -} - -/** - * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * - * Put a clockdomain referred to by (@inst, @cdoffs) into - * hardware-supervised idle mode. No return value. - */ -void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs) -{ - _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs); -} - -/** - * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * - * Put a clockdomain referred to by (@inst, @cdoffs) into - * software-supervised idle mode, i.e., controlled manually by the - * Linux OMAP clockdomain code. No return value. - */ -void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs) -{ - _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs); -} - -/** - * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * - * Put a clockdomain referred to by (@inst, @cdoffs) into idle - * No return value. - */ -void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs) -{ - _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs); -} - -/** - * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * - * Take a clockdomain referred to by (@inst, @cdoffs) out of idle, - * waking it up. No return value. - */ -void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs) -{ - _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs); -} - -/* - * - */ - -/** - * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) - * - * Wait for the module IDLEST to be functional. If the idle state is in any - * the non functional state (trans, idle or disabled), module and thus the - * sysconfig cannot be accessed and will probably lead to an "imprecise - * external abort" - */ -int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs) -{ - int i = 0; - - if (!clkctrl_offs) - return 0; - - omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), - MAX_MODULE_READY_TIME, i); - - return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; -} - -/** - * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled' - * state - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) - * - * Wait for the module IDLEST to be disabled. Some PRCM transition, - * like reset assertion or parent clock de-activation must wait the - * module to be fully disabled. - */ -int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs) -{ - int i = 0; - - if (!clkctrl_offs) - return 0; - - omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) == - CLKCTRL_IDLEST_DISABLED), - MAX_MODULE_READY_TIME, i); - - return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; -} - -/** - * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL - * @mode: Module mode (SW or HW) - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) - * - * No return value. - */ -void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs) -{ - u32 v; - - v = am33xx_cm_read_reg(inst, clkctrl_offs); - v &= ~AM33XX_MODULEMODE_MASK; - v |= mode << AM33XX_MODULEMODE_SHIFT; - am33xx_cm_write_reg(v, inst, clkctrl_offs); -} - -/** - * am33xx_cm_module_disable - Disable the module inside CLKCTRL - * @inst: CM instance register offset (*_INST macro) - * @cdoffs: Clockdomain register offset (*_CDOFFS macro) - * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro) - * - * No return value. - */ -void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs) -{ - u32 v; - - v = am33xx_cm_read_reg(inst, clkctrl_offs); - v &= ~AM33XX_MODULEMODE_MASK; - am33xx_cm_write_reg(v, inst, clkctrl_offs); -} diff --git a/trunk/arch/arm/mach-omap2/cm33xx.h b/trunk/arch/arm/mach-omap2/cm33xx.h deleted file mode 100644 index 5fa0b62e1a79..000000000000 --- a/trunk/arch/arm/mach-omap2/cm33xx.h +++ /dev/null @@ -1,420 +0,0 @@ -/* - * AM33XX CM offset macros - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * Vaibhav Hiremath - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H -#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H - -#include -#include -#include -#include - -#include "common.h" - -#include "cm.h" -#include "cm-regbits-33xx.h" -#include "cm33xx.h" - -/* CM base address */ -#define AM33XX_CM_BASE 0x44e00000 - -#define AM33XX_CM_REGADDR(inst, reg) \ - AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg)) - -/* CM instances */ -#define AM33XX_CM_PER_MOD 0x0000 -#define AM33XX_CM_WKUP_MOD 0x0400 -#define AM33XX_CM_DPLL_MOD 0x0500 -#define AM33XX_CM_MPU_MOD 0x0600 -#define AM33XX_CM_DEVICE_MOD 0x0700 -#define AM33XX_CM_RTC_MOD 0x0800 -#define AM33XX_CM_GFX_MOD 0x0900 -#define AM33XX_CM_CEFUSE_MOD 0x0A00 - -/* CM */ - -/* CM.PER_CM register offsets */ -#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 -#define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) -#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET 0x0004 -#define AM33XX_CM_PER_L3S_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004) -#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET 0x0008 -#define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) -#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c -#define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) -#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 -#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) -#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 -#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) -#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c -#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) -#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 -#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) -#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 -#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) -#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 -#define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) -#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c -#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) -#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 -#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) -#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 -#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) -#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 -#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) -#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c -#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) -#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 -#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) -#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 -#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) -#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 -#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) -#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c -#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) -#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 -#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) -#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 -#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) -#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 -#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) -#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 -#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) -#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 -#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) -#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 -#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) -#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c -#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) -#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 -#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) -#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 -#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) -#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 -#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) -#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c -#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) -#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 -#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) -#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 -#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) -#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 -#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) -#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c -#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) -#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 -#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) -#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 -#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) -#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 -#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) -#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c -#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) -#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 -#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) -#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 -#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) -#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 -#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) -#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac -#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) -#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 -#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) -#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 -#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) -#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 -#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) -#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc -#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) -#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 -#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) -#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 -#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) -#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc -#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) -#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 -#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) -#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 -#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) -#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 -#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) -#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc -#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) -#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 -#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) -#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 -#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) -#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 -#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) -#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec -#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) -#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 -#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) -#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 -#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) -#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 -#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) -#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc -#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) -#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 -#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) -#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 -#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) -#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c -#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) -#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 -#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) -#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c -#define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) -#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 -#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) -#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 -#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) -#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 -#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) -#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c -#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) -#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 -#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) -#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 -#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) -#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 -#define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) -#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 -#define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) -#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 -#define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) -#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c -#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) -#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 -#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) - -/* CM.WKUP_CM register offsets */ -#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 -#define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) -#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 -#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) -#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 -#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) -#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c -#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) -#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 -#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) -#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 -#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) -#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 -#define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) -#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c -#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) -#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 -#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) -#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c -#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) -#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 -#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) -#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 -#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) -#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 -#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) -#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 -#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) -#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 -#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) -#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 -#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) -#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 -#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) -#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c -#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) -#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 -#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) -#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c -#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) -#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 -#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) -#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c -#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) -#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 -#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) -#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 -#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) -#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 -#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) -#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c -#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) -#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 -#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) -#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 -#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) -#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 -#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) -#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c -#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) -#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 -#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) -#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 -#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) -#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 -#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) -#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac -#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) -#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 -#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) -#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 -#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) -#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 -#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) -#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc -#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) -#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 -#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) -#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 -#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) -#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 -#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) -#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc -#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) -#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 -#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) -#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 -#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) -#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 -#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) - -/* CM.DPLL_CM register offsets */ -#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 -#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) -#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 -#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) -#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c -#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) -#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 -#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) -#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 -#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) -#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 -#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) -#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c -#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) -#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 -#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) -#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 -#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) -#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c -#define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) -#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 -#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) -#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 -#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) -#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 -#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) -#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c -#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) - -/* CM.MPU_CM register offsets */ -#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 -#define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) -#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 -#define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) - -/* CM.DEVICE_CM register offsets */ -#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 -#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) - -/* CM.RTC_CM register offsets */ -#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 -#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) -#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 -#define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) - -/* CM.GFX_CM register offsets */ -#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 -#define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) -#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 -#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) -#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 -#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) -#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c -#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) -#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 -#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) -#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 -#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) - -/* CM.CEFUSE_CM register offsets */ -#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 -#define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) -#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 -#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) - - -extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); -extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); -extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); -extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs); -extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs); - -#ifdef CONFIG_SOC_AM33XX -extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, - u16 clkctrl_offs); -extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, - u16 clkctrl_offs); -extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs, - u16 clkctrl_offs); -extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, - u16 clkctrl_offs); -#else -static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, - u16 clkctrl_offs) -{ - return 0; -} -static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, - u16 clkctrl_offs) -{ -} -static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs, - u16 clkctrl_offs) -{ -} -static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, - u16 clkctrl_offs) -{ - return 0; -} -#endif - -#endif diff --git a/trunk/arch/arm/mach-omap2/common.h b/trunk/arch/arm/mach-omap2/common.h index 5d99c1b2cb48..be9dfd1abe60 100644 --- a/trunk/arch/arm/mach-omap2/common.h +++ b/trunk/arch/arm/mach-omap2/common.h @@ -120,7 +120,6 @@ extern void omap2_init_common_infrastructure(void); extern struct sys_timer omap2_timer; extern struct sys_timer omap3_timer; extern struct sys_timer omap3_secure_timer; -extern struct sys_timer omap3_am33xx_timer; extern struct sys_timer omap4_timer; void omap2420_init_early(void); @@ -129,10 +128,8 @@ void omap3430_init_early(void); void omap35xx_init_early(void); void omap3630_init_early(void); void omap3_init_early(void); /* Do not use this one */ -void am33xx_init_early(void); void am35xx_init_early(void); void ti81xx_init_early(void); -void am33xx_init_early(void); void omap4430_init_early(void); void omap3_init_late(void); /* Do not use this one */ void omap4430_init_late(void); diff --git a/trunk/arch/arm/mach-omap2/control.h b/trunk/arch/arm/mach-omap2/control.h index c43f03cbefc5..a406fd045ce1 100644 --- a/trunk/arch/arm/mach-omap2/control.h +++ b/trunk/arch/arm/mach-omap2/control.h @@ -21,8 +21,6 @@ #include #include -#include - #ifndef __ASSEMBLY__ #define OMAP242X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) @@ -30,8 +28,6 @@ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) #define OMAP343X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -#define AM33XX_CTRL_REGADDR(reg) \ - AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) #else #define OMAP242X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) @@ -39,8 +35,6 @@ OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) #define OMAP343X_CTRL_REGADDR(reg) \ OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) -#define AM33XX_CTRL_REGADDR(reg) \ - AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg)) #endif /* __ASSEMBLY__ */ /* @@ -318,15 +312,15 @@ OMAP343X_SCRATCHPAD + reg) /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */ -#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 -#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 -#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 -#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 -#define AM35XX_USBOTG_FCLK_SHIFT 8 -#define AM35XX_CPGMAC_FCLK_SHIFT 9 -#define AM35XX_VPFE_FCLK_SHIFT 10 - -/* AM35XX CONTROL_LVL_INTR_CLEAR bits */ +#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0 +#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT 1 +#define AM35XX_VPFE_VBUSP_CLK_SHIFT 2 +#define AM35XX_HECC_VBUSP_CLK_SHIFT 3 +#define AM35XX_USBOTG_FCLK_SHIFT 8 +#define AM35XX_CPGMAC_FCLK_SHIFT 9 +#define AM35XX_VPFE_FCLK_SHIFT 10 + +/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/ #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0) #define AM35XX_CPGMAC_C0_RX_PULSE_CLR BIT(1) #define AM35XX_CPGMAC_C0_RX_THRESH_CLR BIT(2) @@ -336,22 +330,21 @@ #define AM35XX_VPFE_CCDC_VD1_INT_CLR BIT(6) #define AM35XX_VPFE_CCDC_VD2_INT_CLR BIT(7) -/* AM35XX CONTROL_IP_SW_RESET bits */ +/*AM35XX CONTROL_IP_SW_RESET bits*/ #define AM35XX_USBOTGSS_SW_RST BIT(0) #define AM35XX_CPGMACSS_SW_RST BIT(1) #define AM35XX_VPFE_VBUSP_SW_RST BIT(2) #define AM35XX_HECC_SW_RST BIT(3) #define AM35XX_VPFE_PCLK_SW_RST BIT(4) -/* AM33XX CONTROL_STATUS register */ +/* + * CONTROL AM33XX STATUS register + */ #define AM33XX_CONTROL_STATUS 0x040 -#define AM33XX_CONTROL_SEC_CLK_CTRL 0x1bc -/* AM33XX CONTROL_STATUS bitfields (partial) */ -#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT 22 -#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK (0x3 << 22) - -/* CONTROL OMAP STATUS register to identify OMAP3 features */ +/* + * CONTROL OMAP STATUS register to identify OMAP3 features + */ #define OMAP3_CONTROL_OMAP_STATUS 0x044c #define OMAP3_SGX_SHIFT 13 diff --git a/trunk/arch/arm/mach-omap2/include/mach/debug-macro.S b/trunk/arch/arm/mach-omap2/include/mach/debug-macro.S index d7f844a99a7b..cdfc2a1f0e75 100644 --- a/trunk/arch/arm/mach-omap2/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-omap2/include/mach/debug-macro.S @@ -72,8 +72,6 @@ omap_uart_lsr: .word 0 beq 82f @ configure UART2 cmp \rp, #TI81XXUART3 @ ti81Xx UART offsets different beq 83f @ configure UART3 - cmp \rp, #AM33XXUART1 @ AM33XX UART offsets different - beq 84f @ configure UART1 cmp \rp, #ZOOM_UART @ only on zoom2/3 beq 95f @ configure ZOOM_UART @@ -102,9 +100,7 @@ omap_uart_lsr: .word 0 b 98f 83: mov \rp, #UART_OFFSET(TI81XX_UART3_BASE) b 98f -84: ldr \rp, =AM33XX_UART1_BASE - and \rp, \rp, #0x00ffffff - b 97f + 95: ldr \rp, =ZOOM_UART_BASE str \rp, [\tmp, #0] @ omap_uart_phys ldr \rp, =ZOOM_UART_VIRT @@ -113,17 +109,6 @@ omap_uart_lsr: .word 0 str \rp, [\tmp, #8] @ omap_uart_lsr b 10b - /* AM33XX: Store both phys and virt address for the uart */ -97: add \rp, \rp, #0x44000000 @ phys base - str \rp, [\tmp, #0] @ omap_uart_phys - sub \rp, \rp, #0x44000000 @ phys base - add \rp, \rp, #0xf9000000 @ virt base - str \rp, [\tmp, #4] @ omap_uart_virt - mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) - str \rp, [\tmp, #8] @ omap_uart_lsr - - b 10b - /* Store both phys and virt address for the uart */ 98: add \rp, \rp, #0x48000000 @ phys base str \rp, [\tmp, #0] @ omap_uart_phys diff --git a/trunk/arch/arm/mach-omap2/io.c b/trunk/arch/arm/mach-omap2/io.c index cb6c11cd8df9..8d014ba04abc 100644 --- a/trunk/arch/arm/mach-omap2/io.c +++ b/trunk/arch/arm/mach-omap2/io.c @@ -477,19 +477,6 @@ void __init ti81xx_init_late(void) } #endif -#ifdef CONFIG_SOC_AM33XX -void __init am33xx_init_early(void) -{ - omap2_set_globals_am33xx(); - omap3xxx_check_revision(); - ti81xx_check_features(); - omap_common_init_early(); - am33xx_voltagedomains_init(); - am33xx_powerdomains_init(); - am33xx_clockdomains_init(); -} -#endif - #ifdef CONFIG_ARCH_OMAP4 void __init omap4430_init_early(void) { diff --git a/trunk/arch/arm/mach-omap2/irq.c b/trunk/arch/arm/mach-omap2/irq.c index d5b34febd82d..6038a8c84b74 100644 --- a/trunk/arch/arm/mach-omap2/irq.c +++ b/trunk/arch/arm/mach-omap2/irq.c @@ -280,7 +280,7 @@ int __init omap_intc_of_init(struct device_node *node, return 0; } -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) +#ifdef CONFIG_ARCH_OMAP3 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)]; void omap_intc_save_context(void) diff --git a/trunk/arch/arm/mach-omap2/powerdomain.h b/trunk/arch/arm/mach-omap2/powerdomain.h index a8a95184243d..8f88d65c46ea 100644 --- a/trunk/arch/arm/mach-omap2/powerdomain.h +++ b/trunk/arch/arm/mach-omap2/powerdomain.h @@ -67,9 +67,9 @@ /* * Maximum number of clockdomains that can be associated with a powerdomain. - * PER powerdomain on AM33XX is the worst case + * CORE powerdomain on OMAP4 is the worst case */ -#define PWRDM_MAX_CLKDMS 11 +#define PWRDM_MAX_CLKDMS 9 /* XXX A completely arbitrary number. What is reasonable here? */ #define PWRDM_TRANSITION_BAILOUT 100000 @@ -92,15 +92,6 @@ struct powerdomain; * @pwrdm_clkdms: Clockdomains in this powerdomain * @node: list_head linking all powerdomains * @voltdm_node: list_head linking all powerdomains in a voltagedomain - * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs - * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs - * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield - * in @pwrstctrl_offs - * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs - * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs - * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs - * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield - * in @pwrstctrl_offs * @state: * @state_counter: * @timer: @@ -130,14 +121,6 @@ struct powerdomain { unsigned ret_logic_off_counter; unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; - const u8 pwrstctrl_offs; - const u8 pwrstst_offs; - const u32 logicretstate_mask; - const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS]; - const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS]; - const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS]; - const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS]; - #ifdef CONFIG_PM_DEBUG s64 timer; s64 state_timer[PWRDM_MAX_PWRSTS]; @@ -239,12 +222,10 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm); extern void omap242x_powerdomains_init(void); extern void omap243x_powerdomains_init(void); extern void omap3xxx_powerdomains_init(void); -extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; -extern struct pwrdm_ops am33xx_pwrdm_operations; extern struct pwrdm_ops omap4_pwrdm_operations; /* Common Internal functions used across OMAP rev's */ diff --git a/trunk/arch/arm/mach-omap2/powerdomain33xx.c b/trunk/arch/arm/mach-omap2/powerdomain33xx.c deleted file mode 100644 index 67c5663899b6..000000000000 --- a/trunk/arch/arm/mach-omap2/powerdomain33xx.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * AM33XX Powerdomain control - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#include - -#include "powerdomain.h" -#include "prm33xx.h" -#include "prm-regbits-33xx.h" - - -static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) -{ - am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK, - (pwrst << OMAP_POWERSTATE_SHIFT), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - return 0; -} - -static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= OMAP_POWERSTATE_MASK; - v >>= OMAP_POWERSTATE_SHIFT; - - return v; -} - -static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= OMAP_POWERSTATEST_MASK; - v >>= OMAP_POWERSTATEST_SHIFT; - - return v; -} - -static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= AM33XX_LASTPOWERSTATEENTERED_MASK; - v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT; - - return v; -} - -static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) -{ - am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK, - (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - return 0; -} - -static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) -{ - am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK, - AM33XX_LASTPOWERSTATEENTERED_MASK, - pwrdm->prcm_offs, pwrdm->pwrstst_offs); - return 0; -} - -static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) -{ - u32 m; - - m = pwrdm->logicretstate_mask; - if (!m) - return -EINVAL; - - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - - return 0; -} - -static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) -{ - u32 v; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= AM33XX_LOGICSTATEST_MASK; - v >>= AM33XX_LOGICSTATEST_SHIFT; - - return v; -} - -static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm) -{ - u32 v, m; - - m = pwrdm->logicretstate_mask; - if (!m) - return -EINVAL; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= m; - v >>= __ffs(m); - - return v; -} - -static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = pwrdm->mem_on_mask[bank]; - if (!m) - return -EINVAL; - - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - - return 0; -} - -static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, - u8 pwrst) -{ - u32 m; - - m = pwrdm->mem_ret_mask[bank]; - if (!m) - return -EINVAL; - - am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)), - pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - - return 0; -} - -static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m, v; - - m = pwrdm->mem_pwrst_mask[bank]; - if (!m) - return -EINVAL; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs); - v &= m; - v >>= __ffs(m); - - return v; -} - -static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) -{ - u32 m, v; - - m = pwrdm->mem_retst_mask[bank]; - if (!m) - return -EINVAL; - - v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs); - v &= m; - v >>= __ffs(m); - - return v; -} - -static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm) -{ - u32 c = 0; - - /* - * REVISIT: pwrdm_wait_transition() may be better implemented - * via a callback and a periodic timer check -- how long do we expect - * powerdomain transitions to take? - */ - - /* XXX Is this udelay() value meaningful? */ - while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs) - & OMAP_INTRANSITION_MASK) && - (c++ < PWRDM_TRANSITION_BAILOUT)) - udelay(1); - - if (c > PWRDM_TRANSITION_BAILOUT) { - pr_err("powerdomain: %s: waited too long to complete transition\n", - pwrdm->name); - return -EAGAIN; - } - - pr_debug("powerdomain: completed transition in %d loops\n", c); - - return 0; -} - -struct pwrdm_ops am33xx_pwrdm_operations = { - .pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst, - .pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst, - .pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst, - .pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst, - .pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst, - .pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst, - .pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst, - .pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst, - .pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange, - .pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst, - .pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst, - .pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst, - .pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst, - .pwrdm_wait_transition = am33xx_pwrdm_wait_transition, -}; diff --git a/trunk/arch/arm/mach-omap2/powerdomains33xx_data.c b/trunk/arch/arm/mach-omap2/powerdomains33xx_data.c deleted file mode 100644 index 869adb82569e..000000000000 --- a/trunk/arch/arm/mach-omap2/powerdomains33xx_data.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * AM33XX Power domain data - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "powerdomain.h" -#include "prcm-common.h" -#include "prm-regbits-33xx.h" -#include "prm33xx.h" - -static struct powerdomain gfx_33xx_pwrdm = { - .name = "gfx_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM33XX_PRM_GFX_MOD, - .pwrstctrl_offs = AM33XX_PM_GFX_PWRSTCTRL_OFFSET, - .pwrstst_offs = AM33XX_PM_GFX_PWRSTST_OFFSET, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, - .banks = 1, - .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, - .mem_on_mask = { - [0] = AM33XX_GFX_MEM_ONSTATE_MASK, /* gfx_mem */ - }, - .mem_ret_mask = { - [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ - }, - .mem_pwrst_mask = { - [0] = AM33XX_GFX_MEM_STATEST_MASK, /* gfx_mem */ - }, - .mem_retst_mask = { - [0] = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */ - }, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* gfx_mem */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_ON, /* gfx_mem */ - }, -}; - -static struct powerdomain rtc_33xx_pwrdm = { - .name = "rtc_pwrdm", - .voltdm = { .name = "rtc" }, - .prcm_offs = AM33XX_PRM_RTC_MOD, - .pwrstctrl_offs = AM33XX_PM_RTC_PWRSTCTRL_OFFSET, - .pwrstst_offs = AM33XX_PM_RTC_PWRSTST_OFFSET, - .pwrsts = PWRSTS_ON, - .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, -}; - -static struct powerdomain wkup_33xx_pwrdm = { - .name = "wkup_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM33XX_PRM_WKUP_MOD, - .pwrstctrl_offs = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET, - .pwrstst_offs = AM33XX_PM_WKUP_PWRSTST_OFFSET, - .pwrsts = PWRSTS_ON, - .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, -}; - -static struct powerdomain per_33xx_pwrdm = { - .name = "per_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM33XX_PRM_PER_MOD, - .pwrstctrl_offs = AM33XX_PM_PER_PWRSTCTRL_OFFSET, - .pwrstst_offs = AM33XX_PM_PER_PWRSTST_OFFSET, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, - .banks = 3, - .logicretstate_mask = AM33XX_LOGICRETSTATE_3_3_MASK, - .mem_on_mask = { - [0] = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */ - [1] = AM33XX_PER_MEM_ONSTATE_MASK, /* per_mem */ - [2] = AM33XX_RAM_MEM_ONSTATE_MASK, /* ram_mem */ - }, - .mem_ret_mask = { - [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ - [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ - [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ - }, - .mem_pwrst_mask = { - [0] = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */ - [1] = AM33XX_PER_MEM_STATEST_MASK, /* per_mem */ - [2] = AM33XX_RAM_MEM_STATEST_MASK, /* ram_mem */ - }, - .mem_retst_mask = { - [0] = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */ - [1] = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */ - [2] = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */ - }, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* pruss_mem */ - [1] = PWRSTS_OFF_RET, /* per_mem */ - [2] = PWRSTS_OFF_RET, /* ram_mem */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_ON, /* pruss_mem */ - [1] = PWRSTS_ON, /* per_mem */ - [2] = PWRSTS_ON, /* ram_mem */ - }, -}; - -static struct powerdomain mpu_33xx_pwrdm = { - .name = "mpu_pwrdm", - .voltdm = { .name = "mpu" }, - .prcm_offs = AM33XX_PRM_MPU_MOD, - .pwrstctrl_offs = AM33XX_PM_MPU_PWRSTCTRL_OFFSET, - .pwrstst_offs = AM33XX_PM_MPU_PWRSTST_OFFSET, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, - .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, - .banks = 3, - .logicretstate_mask = AM33XX_LOGICRETSTATE_MASK, - .mem_on_mask = { - [0] = AM33XX_MPU_L1_ONSTATE_MASK, /* mpu_l1 */ - [1] = AM33XX_MPU_L2_ONSTATE_MASK, /* mpu_l2 */ - [2] = AM33XX_MPU_RAM_ONSTATE_MASK, /* mpu_ram */ - }, - .mem_ret_mask = { - [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ - [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ - [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ - }, - .mem_pwrst_mask = { - [0] = AM33XX_MPU_L1_STATEST_MASK, /* mpu_l1 */ - [1] = AM33XX_MPU_L2_STATEST_MASK, /* mpu_l2 */ - [2] = AM33XX_MPU_RAM_STATEST_MASK, /* mpu_ram */ - }, - .mem_retst_mask = { - [0] = AM33XX_MPU_L1_RETSTATE_MASK, /* mpu_l1 */ - [1] = AM33XX_MPU_L2_RETSTATE_MASK, /* mpu_l2 */ - [2] = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */ - }, - .pwrsts_mem_ret = { - [0] = PWRSTS_OFF_RET, /* mpu_l1 */ - [1] = PWRSTS_OFF_RET, /* mpu_l2 */ - [2] = PWRSTS_OFF_RET, /* mpu_ram */ - }, - .pwrsts_mem_on = { - [0] = PWRSTS_ON, /* mpu_l1 */ - [1] = PWRSTS_ON, /* mpu_l2 */ - [2] = PWRSTS_ON, /* mpu_ram */ - }, -}; - -static struct powerdomain cefuse_33xx_pwrdm = { - .name = "cefuse_pwrdm", - .voltdm = { .name = "core" }, - .prcm_offs = AM33XX_PRM_CEFUSE_MOD, - .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET, - .pwrstst_offs = AM33XX_PM_CEFUSE_PWRSTST_OFFSET, - .pwrsts = PWRSTS_OFF_ON, -}; - -static struct powerdomain *powerdomains_am33xx[] __initdata = { - &gfx_33xx_pwrdm, - &rtc_33xx_pwrdm, - &wkup_33xx_pwrdm, - &per_33xx_pwrdm, - &mpu_33xx_pwrdm, - &cefuse_33xx_pwrdm, - NULL, -}; - -void __init am33xx_powerdomains_init(void) -{ - pwrdm_register_platform_funcs(&am33xx_pwrdm_operations); - pwrdm_register_pwrdms(powerdomains_am33xx); - pwrdm_complete_init(); -} diff --git a/trunk/arch/arm/mach-omap2/prm-regbits-33xx.h b/trunk/arch/arm/mach-omap2/prm-regbits-33xx.h deleted file mode 100644 index 0221b5c20e87..000000000000 --- a/trunk/arch/arm/mach-omap2/prm-regbits-33xx.h +++ /dev/null @@ -1,357 +0,0 @@ -/* - * AM33XX PRM_XXX register bits - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H - -#include "prm.h" - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 -#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_AIPOFF_SHIFT 8 -#define AM33XX_AIPOFF_MASK (1 << 8) - -/* Used by PM_WKUP_PWRSTST */ -#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 -#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 -#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 -#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 -#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 -#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 -#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 -#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 -#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 -#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 -#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 -#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 -#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) - -/* Used by RM_WKUP_RSTST */ -#define AM33XX_EMULATION_M3_RST_SHIFT 6 -#define AM33XX_EMULATION_M3_RST_MASK (1 << 6) - -/* Used by RM_MPU_RSTST */ -#define AM33XX_EMULATION_MPU_RST_SHIFT 5 -#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC1_EXPORT_SHIFT 3 -#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC3_EXPORT_SHIFT 5 -#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC4_SHIFT 6 -#define AM33XX_ENFUNC4_MASK (1 << 6) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC5_SHIFT 7 -#define AM33XX_ENFUNC5_MASK (1 << 7) - -/* Used by PRM_RSTST */ -#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 -#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_FORCEWKUP_EN_SHIFT 10 -#define AM33XX_FORCEWKUP_EN_MASK (1 << 10) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_FORCEWKUP_ST_SHIFT 10 -#define AM33XX_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by PM_GFX_PWRSTCTRL */ -#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 -#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) - -/* Used by PM_GFX_PWRSTCTRL */ -#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 -#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) - -/* Used by PM_GFX_PWRSTST */ -#define AM33XX_GFX_MEM_STATEST_SHIFT 4 -#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) - -/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ -#define AM33XX_GFX_RST_SHIFT 0 -#define AM33XX_GFX_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define AM33XX_GLOBAL_COLD_RST_SHIFT 0 -#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 -#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) - -/* Used by RM_WKUP_RSTST */ -#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 -#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) - -/* Used by RM_MPU_RSTST */ -#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 -#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) - -/* Used by PRM_RSTST */ -#define AM33XX_ICEPICK_RST_SHIFT 9 -#define AM33XX_ICEPICK_RST_MASK (1 << 9) - -/* Used by RM_PER_RSTCTRL */ -#define AM33XX_PRUSS_LRST_SHIFT 1 -#define AM33XX_PRUSS_LRST_MASK (1 << 1) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 -#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 -#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 -#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) - -/* - * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, - * PM_WKUP_PWRSTST, PM_RTC_PWRSTST - */ -#define AM33XX_INTRANSITION_SHIFT 20 -#define AM33XX_INTRANSITION_MASK (1 << 20) - -/* Used by PM_CEFUSE_PWRSTST */ -#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 -#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) - -/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ -#define AM33XX_LOGICRETSTATE_SHIFT 2 -#define AM33XX_LOGICRETSTATE_MASK (1 << 2) - -/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ -#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 -#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) - -/* - * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, - * PM_WKUP_PWRSTST, PM_RTC_PWRSTST - */ -#define AM33XX_LOGICSTATEST_SHIFT 2 -#define AM33XX_LOGICSTATEST_MASK (1 << 2) - -/* - * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL - */ -#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 -#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L1_ONSTATE_SHIFT 18 -#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L1_RETSTATE_SHIFT 22 -#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_L1_STATEST_SHIFT 6 -#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L2_ONSTATE_SHIFT 20 -#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L2_RETSTATE_SHIFT 23 -#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_L2_STATEST_SHIFT 8 -#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 -#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 -#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_RAM_STATEST_SHIFT 4 -#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_RSTST */ -#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_PCHARGECNT_VALUE_SHIFT 0 -#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) - -/* Used by RM_PER_RSTCTRL */ -#define AM33XX_PCI_LRST_SHIFT 0 -#define AM33XX_PCI_LRST_MASK (1 << 0) - -/* Renamed from PCI_LRST Used by RM_PER_RSTST */ -#define AM33XX_PCI_LRST_5_5_SHIFT 5 -#define AM33XX_PCI_LRST_5_5_MASK (1 << 5) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PER_MEM_ONSTATE_SHIFT 25 -#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PER_MEM_RETSTATE_SHIFT 29 -#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_PER_MEM_STATEST_SHIFT 17 -#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) - -/* - * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL - */ -#define AM33XX_POWERSTATE_SHIFT 0 -#define AM33XX_POWERSTATE_MASK (0x3 << 0) - -/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ -#define AM33XX_POWERSTATEST_SHIFT 0 -#define AM33XX_POWERSTATEST_MASK (0x3 << 0) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 -#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 -#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_RAM_MEM_STATEST_SHIFT 21 -#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_RETMODE_ENABLE_SHIFT 0 -#define AM33XX_RETMODE_ENABLE_MASK (1 << 0) - -/* Used by REVISION_PRM */ -#define AM33XX_REV_SHIFT 0 -#define AM33XX_REV_MASK (0xff << 0) - -/* Used by PRM_RSTTIME */ -#define AM33XX_RSTTIME1_SHIFT 0 -#define AM33XX_RSTTIME1_MASK (0xff << 0) - -/* Used by PRM_RSTTIME */ -#define AM33XX_RSTTIME2_SHIFT 8 -#define AM33XX_RSTTIME2_MASK (0x1f << 8) - -/* Used by PRM_RSTCTRL */ -#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 -#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) - -/* Used by PRM_RSTCTRL */ -#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 -#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_SLPCNT_VALUE_SHIFT 16 -#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_SRAMLDO_STATUS_SHIFT 8 -#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 -#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_STARTUP_COUNT_SHIFT 24 -#define AM33XX_STARTUP_COUNT_MASK (0xff << 24) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_TRANSITION_EN_SHIFT 8 -#define AM33XX_TRANSITION_EN_MASK (1 << 8) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_TRANSITION_ST_SHIFT 8 -#define AM33XX_TRANSITION_ST_MASK (1 << 8) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_VSETUPCNT_VALUE_SHIFT 8 -#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_RSTST */ -#define AM33XX_WDT0_RST_SHIFT 3 -#define AM33XX_WDT0_RST_MASK (1 << 3) - -/* Used by PRM_RSTST */ -#define AM33XX_WDT1_RST_SHIFT 4 -#define AM33XX_WDT1_RST_MASK (1 << 4) - -/* Used by RM_WKUP_RSTCTRL */ -#define AM33XX_WKUP_M3_LRST_SHIFT 3 -#define AM33XX_WKUP_M3_LRST_MASK (1 << 3) - -/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ -#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 -#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) - -#endif diff --git a/trunk/arch/arm/mach-omap2/prm33xx.c b/trunk/arch/arm/mach-omap2/prm33xx.c deleted file mode 100644 index e7dbb6cf1255..000000000000 --- a/trunk/arch/arm/mach-omap2/prm33xx.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * AM33XX PRM functions - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "prm33xx.h" -#include "prm-regbits-33xx.h" - -/* Read a register in a PRM instance */ -u32 am33xx_prm_read_reg(s16 inst, u16 idx) -{ - return __raw_readl(prm_base + inst + idx); -} - -/* Write into a register in a PRM instance */ -void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx) -{ - __raw_writel(val, prm_base + inst + idx); -} - -/* Read-modify-write a register in PRM. Caller must lock */ -u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx) -{ - u32 v; - - v = am33xx_prm_read_reg(inst, idx); - v &= ~mask; - v |= bits; - am33xx_prm_write_reg(v, inst, idx); - - return v; -} - -/** - * am33xx_prm_is_hardreset_asserted - read the HW reset line state of - * submodules contained in the hwmod module - * @shift: register bit shift corresponding to the reset line to check - * @inst: CM instance register offset (*_INST macro) - * @rstctrl_offs: RM_RSTCTRL register address offset for this module - * - * Returns 1 if the (sub)module hardreset line is currently asserted, - * 0 if the (sub)module hardreset line is not currently asserted, or - * -EINVAL upon parameter error. - */ -int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs) -{ - u32 v; - - v = am33xx_prm_read_reg(inst, rstctrl_offs); - v &= 1 << shift; - v >>= shift; - - return v; -} - -/** - * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule - * @shift: register bit shift corresponding to the reset line to assert - * @inst: CM instance register offset (*_INST macro) - * @rstctrl_reg: RM_RSTCTRL register address for this module - * - * Some IPs like dsp, ipu or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * place the submodule into reset. Returns 0 upon success or -EINVAL - * upon an argument error. - */ -int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs) -{ - u32 mask = 1 << shift; - - am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs); - - return 0; -} - -/** - * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and - * wait - * @shift: register bit shift corresponding to the reset line to deassert - * @inst: CM instance register offset (*_INST macro) - * @rstctrl_reg: RM_RSTCTRL register address for this module - * @rstst_reg: RM_RSTST register address for this module - * - * Some IPs like dsp, ipu or iva contain processors that require an HW - * reset line to be asserted / deasserted in order to fully enable the - * IP. These modules may have multiple hard-reset lines that reset - * different 'submodules' inside the IP block. This function will - * take the submodule out of reset and wait until the PRCM indicates - * that the reset has completed before returning. Returns 0 upon success or - * -EINVAL upon an argument error, -EEXIST if the submodule was already out - * of reset, or -EBUSY if the submodule did not exit reset promptly. - */ -int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, - u16 rstctrl_offs, u16 rstst_offs) -{ - int c; - u32 mask = 1 << shift; - - /* Check the current status to avoid de-asserting the line twice */ - if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) - return -EEXIST; - - /* Clear the reset status by writing 1 to the status bit */ - am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); - /* de-assert the reset control line */ - am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); - /* wait the status to be set */ - - omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst, - rstst_offs), - MAX_MODULE_HARDRESET_WAIT, c); - - return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; -} diff --git a/trunk/arch/arm/mach-omap2/prm33xx.h b/trunk/arch/arm/mach-omap2/prm33xx.h deleted file mode 100644 index 3f25c563a821..000000000000 --- a/trunk/arch/arm/mach-omap2/prm33xx.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * AM33XX PRM instance offset macros - * - * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H - -#include "prcm-common.h" -#include "prm.h" - -#define AM33XX_PRM_BASE 0x44E00000 - -#define AM33XX_PRM_REGADDR(inst, reg) \ - AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg)) - - -/* PRM instances */ -#define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00 -#define AM33XX_PRM_PER_MOD 0x0C00 -#define AM33XX_PRM_WKUP_MOD 0x0D00 -#define AM33XX_PRM_MPU_MOD 0x0E00 -#define AM33XX_PRM_DEVICE_MOD 0x0F00 -#define AM33XX_PRM_RTC_MOD 0x1000 -#define AM33XX_PRM_GFX_MOD 0x1100 -#define AM33XX_PRM_CEFUSE_MOD 0x1200 - -/* PRM */ - -/* PRM.OCP_SOCKET_PRM register offsets */ -#define AM33XX_REVISION_PRM_OFFSET 0x0000 -#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) -#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 -#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) -#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 -#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) -#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c -#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) -#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 -#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) - -/* PRM.PER_PRM register offsets */ -#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 -#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) -#define AM33XX_RM_PER_RSTST_OFFSET 0x0004 -#define AM33XX_RM_PER_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004) -#define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 -#define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) -#define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c -#define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) - -/* PRM.WKUP_PRM register offsets */ -#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 -#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) -#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 -#define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) -#define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 -#define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) -#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c -#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) - -/* PRM.MPU_PRM register offsets */ -#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 -#define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) -#define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 -#define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) -#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008 -#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) - -/* PRM.DEVICE_PRM register offsets */ -#define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 -#define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) -#define AM33XX_PRM_RSTTIME_OFFSET 0x0004 -#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) -#define AM33XX_PRM_RSTST_OFFSET 0x0008 -#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) -#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c -#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) -#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 -#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) -#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 -#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) -#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 -#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) -#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c -#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) - -/* PRM.RTC_PRM register offsets */ -#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 -#define AM33XX_PM_RTC_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000) -#define AM33XX_PM_RTC_PWRSTST_OFFSET 0x0004 -#define AM33XX_PM_RTC_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004) - -/* PRM.GFX_PRM register offsets */ -#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 -#define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) -#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 -#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) -#define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 -#define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) -#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014 -#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) - -/* PRM.CEFUSE_PRM register offsets */ -#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 -#define AM33XX_PM_CEFUSE_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000) -#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 -#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) - -extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); -extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); -extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); -extern void am33xx_prm_global_warm_sw_reset(void); -extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, - u16 rstctrl_offs); -extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs); -extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, - u16 rstctrl_offs, u16 rstst_offs); -#endif diff --git a/trunk/arch/arm/mach-omap2/timer.c b/trunk/arch/arm/mach-omap2/timer.c index ea6a0eb13f05..840929bd9dae 100644 --- a/trunk/arch/arm/mach-omap2/timer.c +++ b/trunk/arch/arm/mach-omap2/timer.c @@ -368,11 +368,6 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, OMAP_SYS_TIMER(3_secure) #endif -#ifdef CONFIG_SOC_AM33XX -OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) -OMAP_SYS_TIMER(3_am33xx) -#endif - #ifdef CONFIG_ARCH_OMAP4 #ifdef CONFIG_LOCAL_TIMERS static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, diff --git a/trunk/arch/arm/mach-omap2/voltage.h b/trunk/arch/arm/mach-omap2/voltage.h index a7c43c1042be..16a1b092cf36 100644 --- a/trunk/arch/arm/mach-omap2/voltage.h +++ b/trunk/arch/arm/mach-omap2/voltage.h @@ -156,7 +156,6 @@ int omap_voltage_late_init(void); extern void omap2xxx_voltagedomains_init(void); extern void omap3xxx_voltagedomains_init(void); -extern void am33xx_voltagedomains_init(void); extern void omap44xx_voltagedomains_init(void); struct voltagedomain *voltdm_lookup(const char *name); diff --git a/trunk/arch/arm/mach-omap2/voltagedomains33xx_data.c b/trunk/arch/arm/mach-omap2/voltagedomains33xx_data.c deleted file mode 100644 index 965458dc0cb9..000000000000 --- a/trunk/arch/arm/mach-omap2/voltagedomains33xx_data.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * AM33XX voltage domain data - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include "voltage.h" - -static struct voltagedomain am33xx_voltdm_mpu = { - .name = "mpu", -}; - -static struct voltagedomain am33xx_voltdm_core = { - .name = "core", -}; - -static struct voltagedomain am33xx_voltdm_rtc = { - .name = "rtc", -}; - -static struct voltagedomain *voltagedomains_am33xx[] __initdata = { - &am33xx_voltdm_mpu, - &am33xx_voltdm_core, - &am33xx_voltdm_rtc, - NULL, -}; - -void __init am33xx_voltagedomains_init(void) -{ - voltdm_init(voltagedomains_am33xx); -} diff --git a/trunk/arch/arm/mach-tegra/Kconfig b/trunk/arch/arm/mach-tegra/Kconfig index 7c407393cd07..6a113a9bb87a 100644 --- a/trunk/arch/arm/mach-tegra/Kconfig +++ b/trunk/arch/arm/mach-tegra/Kconfig @@ -63,6 +63,7 @@ comment "Tegra board type" config MACH_HARMONY bool "Harmony board" depends on ARCH_TEGRA_2x_SOC + select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Harmony development platform @@ -70,6 +71,7 @@ config MACH_KAEN bool "Kaen board" depends on ARCH_TEGRA_2x_SOC select MACH_SEABOARD + select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for the Kaen version of Seaboard @@ -82,6 +84,7 @@ config MACH_PAZ00 config MACH_SEABOARD bool "Seaboard board" depends on ARCH_TEGRA_2x_SOC + select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC help Support for nVidia Seaboard development platform. It will also be included for some of the derivative boards that diff --git a/trunk/arch/arm/mach-tegra/Makefile b/trunk/arch/arm/mach-tegra/Makefile index e9f48ec00ca7..2eb4445ddb14 100644 --- a/trunk/arch/arm/mach-tegra/Makefile +++ b/trunk/arch/arm/mach-tegra/Makefile @@ -8,7 +8,6 @@ obj-y += timer.o obj-y += fuse.o obj-y += pmc.o obj-y += flowctrl.o -obj-y += apbio.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CPU_IDLE) += sleep.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o @@ -19,7 +18,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += reset.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o -obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o +obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_TEGRA_PCI) += pcie.o obj-$(CONFIG_USB_SUPPORT) += usb_phy.o diff --git a/trunk/arch/arm/mach-tegra/Makefile.boot b/trunk/arch/arm/mach-tegra/Makefile.boot index 8040345bd971..9a82094092d7 100644 --- a/trunk/arch/arm/mach-tegra/Makefile.boot +++ b/trunk/arch/arm/mach-tegra/Makefile.boot @@ -2,9 +2,9 @@ zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC) += 0x00008000 params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000 -dtb-$(CONFIG_MACH_HARMONY) += tegra20-harmony.dtb -dtb-$(CONFIG_MACH_PAZ00) += tegra20-paz00.dtb -dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb -dtb-$(CONFIG_MACH_TRIMSLICE) += tegra20-trimslice.dtb -dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb -dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb +dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb +dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb +dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb +dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb +dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb +dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb diff --git a/trunk/arch/arm/mach-tegra/apbio.c b/trunk/arch/arm/mach-tegra/apbio.c index dc0fe389be56..e75451e517bd 100644 --- a/trunk/arch/arm/mach-tegra/apbio.c +++ b/trunk/arch/arm/mach-tegra/apbio.c @@ -15,9 +15,6 @@ #include #include -#include -#include -#include #include #include #include @@ -25,21 +22,17 @@ #include #include +#include #include "apbio.h" -#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA) static DEFINE_MUTEX(tegra_apb_dma_lock); + +static struct tegra_dma_channel *tegra_apb_dma; static u32 *tegra_apb_bb; static dma_addr_t tegra_apb_bb_phys; static DECLARE_COMPLETION(tegra_apb_wait); -static u32 tegra_apb_readl_direct(unsigned long offset); -static void tegra_apb_writel_direct(u32 value, unsigned long offset); - -#if defined(CONFIG_TEGRA_SYSTEM_DMA) -static struct tegra_dma_channel *tegra_apb_dma; - bool tegra_apb_init(void) { struct tegra_dma_channel *ch; @@ -79,13 +72,13 @@ static void apb_dma_complete(struct tegra_dma_req *req) complete(&tegra_apb_wait); } -static u32 tegra_apb_readl_using_dma(unsigned long offset) +u32 tegra_apb_readl(unsigned long offset) { struct tegra_dma_req req; int ret; if (!tegra_apb_dma && !tegra_apb_init()) - return tegra_apb_readl_direct(offset); + return readl(IO_TO_VIRT(offset)); mutex_lock(&tegra_apb_dma_lock); req.complete = apb_dma_complete; @@ -115,13 +108,13 @@ static u32 tegra_apb_readl_using_dma(unsigned long offset) return *((u32 *)tegra_apb_bb); } -static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) +void tegra_apb_writel(u32 value, unsigned long offset) { struct tegra_dma_req req; int ret; if (!tegra_apb_dma && !tegra_apb_init()) { - tegra_apb_writel_direct(value, offset); + writel(value, IO_TO_VIRT(offset)); return; } @@ -150,176 +143,3 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) mutex_unlock(&tegra_apb_dma_lock); } - -#else -static struct dma_chan *tegra_apb_dma_chan; -static struct dma_slave_config dma_sconfig; - -bool tegra_apb_dma_init(void) -{ - dma_cap_mask_t mask; - - mutex_lock(&tegra_apb_dma_lock); - - /* Check to see if we raced to setup */ - if (tegra_apb_dma_chan) - goto skip_init; - - dma_cap_zero(mask); - dma_cap_set(DMA_SLAVE, mask); - tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL); - if (!tegra_apb_dma_chan) { - /* - * This is common until the device is probed, so don't - * shout about it. - */ - pr_debug("%s: can not allocate dma channel\n", __func__); - goto err_dma_alloc; - } - - tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32), - &tegra_apb_bb_phys, GFP_KERNEL); - if (!tegra_apb_bb) { - pr_err("%s: can not allocate bounce buffer\n", __func__); - goto err_buff_alloc; - } - - dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR; - dma_sconfig.src_maxburst = 1; - dma_sconfig.dst_maxburst = 1; - -skip_init: - mutex_unlock(&tegra_apb_dma_lock); - return true; - -err_buff_alloc: - dma_release_channel(tegra_apb_dma_chan); - tegra_apb_dma_chan = NULL; - -err_dma_alloc: - mutex_unlock(&tegra_apb_dma_lock); - return false; -} - -static void apb_dma_complete(void *args) -{ - complete(&tegra_apb_wait); -} - -static int do_dma_transfer(unsigned long apb_add, - enum dma_transfer_direction dir) -{ - struct dma_async_tx_descriptor *dma_desc; - int ret; - - if (dir == DMA_DEV_TO_MEM) - dma_sconfig.src_addr = apb_add; - else - dma_sconfig.dst_addr = apb_add; - - ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig); - if (ret) - return ret; - - dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan, - tegra_apb_bb_phys, sizeof(u32), dir, - DMA_PREP_INTERRUPT | DMA_CTRL_ACK); - if (!dma_desc) - return -EINVAL; - - dma_desc->callback = apb_dma_complete; - dma_desc->callback_param = NULL; - - INIT_COMPLETION(tegra_apb_wait); - - dmaengine_submit(dma_desc); - dma_async_issue_pending(tegra_apb_dma_chan); - ret = wait_for_completion_timeout(&tegra_apb_wait, - msecs_to_jiffies(50)); - - if (WARN(ret == 0, "apb read dma timed out")) { - dmaengine_terminate_all(tegra_apb_dma_chan); - return -EFAULT; - } - return 0; -} - -static u32 tegra_apb_readl_using_dma(unsigned long offset) -{ - int ret; - - if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) - return tegra_apb_readl_direct(offset); - - mutex_lock(&tegra_apb_dma_lock); - ret = do_dma_transfer(offset, DMA_DEV_TO_MEM); - if (ret < 0) { - pr_err("error in reading offset 0x%08lx using dma\n", offset); - *(u32 *)tegra_apb_bb = 0; - } - mutex_unlock(&tegra_apb_dma_lock); - return *((u32 *)tegra_apb_bb); -} - -static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) -{ - int ret; - - if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) { - tegra_apb_writel_direct(value, offset); - return; - } - - mutex_lock(&tegra_apb_dma_lock); - *((u32 *)tegra_apb_bb) = value; - ret = do_dma_transfer(offset, DMA_MEM_TO_DEV); - if (ret < 0) - pr_err("error in writing offset 0x%08lx using dma\n", offset); - mutex_unlock(&tegra_apb_dma_lock); -} -#endif -#else -#define tegra_apb_readl_using_dma tegra_apb_readl_direct -#define tegra_apb_writel_using_dma tegra_apb_writel_direct -#endif - -typedef u32 (*apbio_read_fptr)(unsigned long offset); -typedef void (*apbio_write_fptr)(u32 value, unsigned long offset); - -static apbio_read_fptr apbio_read; -static apbio_write_fptr apbio_write; - -static u32 tegra_apb_readl_direct(unsigned long offset) -{ - return readl(IO_TO_VIRT(offset)); -} - -static void tegra_apb_writel_direct(u32 value, unsigned long offset) -{ - writel(value, IO_TO_VIRT(offset)); -} - -void tegra_apb_io_init(void) -{ - /* Need to use dma only when it is Tegra20 based platform */ - if (of_machine_is_compatible("nvidia,tegra20") || - !of_have_populated_dt()) { - apbio_read = tegra_apb_readl_using_dma; - apbio_write = tegra_apb_writel_using_dma; - } else { - apbio_read = tegra_apb_readl_direct; - apbio_write = tegra_apb_writel_direct; - } -} - -u32 tegra_apb_readl(unsigned long offset) -{ - return apbio_read(offset); -} - -void tegra_apb_writel(u32 value, unsigned long offset) -{ - apbio_write(value, offset); -} diff --git a/trunk/arch/arm/mach-tegra/apbio.h b/trunk/arch/arm/mach-tegra/apbio.h index f05d71c303c7..8b49e8c89a64 100644 --- a/trunk/arch/arm/mach-tegra/apbio.h +++ b/trunk/arch/arm/mach-tegra/apbio.h @@ -16,7 +16,24 @@ #ifndef __MACH_TEGRA_APBIO_H #define __MACH_TEGRA_APBIO_H -void tegra_apb_io_init(void); +#ifdef CONFIG_TEGRA_SYSTEM_DMA + u32 tegra_apb_readl(unsigned long offset); void tegra_apb_writel(u32 value, unsigned long offset); + +#else +#include +#include + +static inline u32 tegra_apb_readl(unsigned long offset) +{ + return readl(IO_TO_VIRT(offset)); +} + +static inline void tegra_apb_writel(u32 value, unsigned long offset) +{ + writel(value, IO_TO_VIRT(offset)); +} +#endif + #endif diff --git a/trunk/arch/arm/mach-tegra/common.c b/trunk/arch/arm/mach-tegra/common.c index 96fef6bcc651..204a5c8b0b57 100644 --- a/trunk/arch/arm/mach-tegra/common.c +++ b/trunk/arch/arm/mach-tegra/common.c @@ -33,7 +33,6 @@ #include "clock.h" #include "fuse.h" #include "pmc.h" -#include "apbio.h" /* * Storage for debug-macro.S's state. @@ -128,7 +127,6 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) #ifdef CONFIG_ARCH_TEGRA_2x_SOC void __init tegra20_init_early(void) { - tegra_apb_io_init(); tegra_init_fuse(); tegra2_init_clocks(); tegra_clk_init_from_table(tegra20_clk_init_table); @@ -140,7 +138,6 @@ void __init tegra20_init_early(void) #ifdef CONFIG_ARCH_TEGRA_3x_SOC void __init tegra30_init_early(void) { - tegra_apb_io_init(); tegra_init_fuse(); tegra30_init_clocks(); tegra_clk_init_from_table(tegra30_clk_init_table); diff --git a/trunk/arch/arm/mach-tegra/cpuidle.c b/trunk/arch/arm/mach-tegra/cpuidle.c index 566e2f88899b..d83a8c0296f5 100644 --- a/trunk/arch/arm/mach-tegra/cpuidle.c +++ b/trunk/arch/arm/mach-tegra/cpuidle.c @@ -27,10 +27,10 @@ #include #include -#include - #include +extern void tegra_cpu_wfi(void); + static int tegra_idle_enter_lp3(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); @@ -64,7 +64,7 @@ static int tegra_idle_enter_lp3(struct cpuidle_device *dev, enter = ktime_get(); - cpu_do_idle(); + tegra_cpu_wfi(); exit = ktime_sub(ktime_get(), enter); us = ktime_to_us(exit); diff --git a/trunk/arch/arm/mach-tegra/sleep.S b/trunk/arch/arm/mach-tegra/sleep.S index d29b156a8011..5b20197bae7f 100644 --- a/trunk/arch/arm/mach-tegra/sleep.S +++ b/trunk/arch/arm/mach-tegra/sleep.S @@ -62,3 +62,32 @@ movw \reg, #:lower16:\val movt \reg, #:upper16:\val .endm + +/* + * tegra_cpu_wfi + * + * puts current CPU in clock-gated wfi using the flow controller + * + * corrupts r0-r3 + * must be called with MMU on + */ + +ENTRY(tegra_cpu_wfi) + cpu_id r0 + cpu_to_halt_reg r1, r0 + cpu_to_csr_reg r2, r0 + mov32 r0, TEGRA_FLOW_CTRL_VIRT + mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + str r3, [r0, r2] @ clear event & interrupt status + mov r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME + str r3, [r0, r1] @ put flow controller in wait irq mode + dsb + wfi + mov r3, #0 + str r3, [r0, r1] @ clear flow controller halt status + mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG + str r3, [r0, r2] @ clear event & interrupt status + dsb + mov pc, lr +ENDPROC(tegra_cpu_wfi) + diff --git a/trunk/arch/arm/mach-vexpress/Kconfig b/trunk/arch/arm/mach-vexpress/Kconfig index cf8730d35e70..fc3730f01650 100644 --- a/trunk/arch/arm/mach-vexpress/Kconfig +++ b/trunk/arch/arm/mach-vexpress/Kconfig @@ -2,7 +2,8 @@ menu "Versatile Express platform type" depends on ARCH_VEXPRESS config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA - bool + bool "Enable A5 and A9 only errata work-arounds" + default y select ARM_ERRATA_720789 select ARM_ERRATA_751472 select PL310_ERRATA_753970 if CACHE_PL310 @@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA config ARCH_VEXPRESS_CA9X4 bool "Versatile Express Cortex-A9x4 tile" - select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA select ARM_GIC select CPU_V7 select HAVE_SMP @@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4 config ARCH_VEXPRESS_DT bool "Device Tree support for Versatile Express platforms" - select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA select ARM_GIC select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR diff --git a/trunk/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/trunk/arch/arm/plat-mxc/devices/platform-mxc_rtc.c index a5c9ad5721c2..16d0ec4df5f6 100644 --- a/trunk/arch/arm/plat-mxc/devices/platform-mxc_rtc.c +++ b/trunk/arch/arm/plat-mxc/devices/platform-mxc_rtc.c @@ -20,11 +20,6 @@ const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst = imx_mxc_rtc_data_entry_single(MX31); #endif /* ifdef CONFIG_SOC_IMX31 */ -#ifdef CONFIG_SOC_IMX35 -const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst = - imx_mxc_rtc_data_entry_single(MX35); -#endif /* ifdef CONFIG_SOC_IMX35 */ - struct platform_device *__init imx_add_mxc_rtc( const struct imx_mxc_rtc_data *data) { diff --git a/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h index 2623e7a2e190..36c8989d9de6 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/trunk/arch/arm/plat-mxc/include/mach/iomux-mx51.h @@ -107,13 +107,11 @@ #define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D25__GPT_CMPOUT1 IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL) #define MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_EIM_D26__GPT_CMPOUT2 IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) @@ -230,7 +228,6 @@ #define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DRAM_CS1__CCM_CLKO IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL) @@ -259,14 +256,12 @@ #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2 IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3 IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) @@ -642,9 +637,7 @@ #define MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_DI1_PIN15__DI1_PIN15 IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL) #define MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL) @@ -787,8 +780,6 @@ #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) -#define MX51_PAD_GPIO1_3__CCM_CLKO2 IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_3__GPT_CLKIN IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL) @@ -797,16 +788,13 @@ #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) #define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_4__GPT_CAPIN1 IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_5__CCM_CLKO IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_6__GPT_CAPIN2 IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) @@ -815,13 +803,11 @@ #define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_8__CCM_CLKO2 IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) -#define MX51_PAD_GPIO1_9__CCM_CLKO IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL) #endif /* __MACH_IOMUX_MX51_H__ */ diff --git a/trunk/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/trunk/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 7eb9d1329671..9ffd1bbe615f 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/trunk/arch/arm/plat-mxc/include/mach/mxc_ehci.h @@ -20,15 +20,13 @@ #define MXC_EHCI_INTERFACE_MASK (0xf) #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) -#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) -#define MXC_EHCI_TTL_ENABLED (1 << 8) - -#define MXC_EHCI_INTERNAL_PHY (1 << 9) -#define MXC_EHCI_IPPUE_DOWN (1 << 10) -#define MXC_EHCI_IPPUE_UP (1 << 11) -#define MXC_EHCI_WAKEUP_ENABLED (1 << 12) -#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13) +#define MXC_EHCI_TTL_ENABLED (1 << 6) + +#define MXC_EHCI_INTERNAL_PHY (1 << 7) +#define MXC_EHCI_IPPUE_DOWN (1 << 8) +#define MXC_EHCI_IPPUE_UP (1 << 9) +#define MXC_EHCI_WAKEUP_ENABLED (1 << 10) +#define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) #define MXC_USBCTRL_OFFSET 0 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 diff --git a/trunk/arch/arm/plat-omap/include/plat/serial.h b/trunk/arch/arm/plat-omap/include/plat/serial.h index 28e2d250c2fd..b073e5f2b190 100644 --- a/trunk/arch/arm/plat-omap/include/plat/serial.h +++ b/trunk/arch/arm/plat-omap/include/plat/serial.h @@ -60,9 +60,6 @@ /* AM3505/3517 UART4 */ #define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */ -/* AM33XX serial port */ -#define AM33XX_UART1_BASE 0x44E09000 - /* External port on Zoom2/3 */ #define ZOOM_UART_BASE 0x10000000 #define ZOOM_UART_VIRT 0xfa400000 @@ -96,7 +93,6 @@ #define TI81XXUART1 81 #define TI81XXUART2 82 #define TI81XXUART3 83 -#define AM33XXUART1 84 #define ZOOM_UART 95 /* Only on zoom2/3 */ /* This is only used by 8250.c for omap1510 */ diff --git a/trunk/arch/arm/plat-omap/include/plat/uncompress.h b/trunk/arch/arm/plat-omap/include/plat/uncompress.h index ac4323390213..cc3f11ba7a99 100644 --- a/trunk/arch/arm/plat-omap/include/plat/uncompress.h +++ b/trunk/arch/arm/plat-omap/include/plat/uncompress.h @@ -103,10 +103,6 @@ static inline void flush(void) _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ TI81XXUART##p) -#define DEBUG_LL_AM33XX(p, mach) \ - _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT, \ - AM33XXUART##p) - static inline void __arch_decomp_setup(unsigned long arch_id) { int port = 0; @@ -187,8 +183,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* TI8148 base boards using UART1 */ DEBUG_LL_TI81XX(1, ti8148evm); - /* AM33XX base boards using UART1 */ - DEBUG_LL_AM33XX(1, am335xevm); } while (0); } diff --git a/trunk/drivers/amba/tegra-ahb.c b/trunk/drivers/amba/tegra-ahb.c index 0b6f0b28a487..aa0b1f160528 100644 --- a/trunk/drivers/amba/tegra-ahb.c +++ b/trunk/drivers/amba/tegra-ahb.c @@ -264,6 +264,11 @@ static int __devinit tegra_ahb_probe(struct platform_device *pdev) return 0; } +static int __devexit tegra_ahb_remove(struct platform_device *pdev) +{ + return 0; +} + static const struct of_device_id tegra_ahb_of_match[] __devinitconst = { { .compatible = "nvidia,tegra30-ahb", }, { .compatible = "nvidia,tegra20-ahb", }, @@ -272,6 +277,7 @@ static const struct of_device_id tegra_ahb_of_match[] __devinitconst = { static struct platform_driver tegra_ahb_driver = { .probe = tegra_ahb_probe, + .remove = __devexit_p(tegra_ahb_remove), .driver = { .name = DRV_NAME, .owner = THIS_MODULE, diff --git a/trunk/drivers/clk/Makefile b/trunk/drivers/clk/Makefile index 26b6b92942e1..b9a5158a30b1 100644 --- a/trunk/drivers/clk/Makefile +++ b/trunk/drivers/clk/Makefile @@ -3,6 +3,5 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ clk-mux.o clk-divider.o clk-fixed-factor.o # SoCs specific -obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o obj-$(CONFIG_ARCH_MXS) += mxs/ obj-$(CONFIG_PLAT_SPEAR) += spear/ diff --git a/trunk/drivers/clk/clk-nomadik.c b/trunk/drivers/clk/clk-nomadik.c deleted file mode 100644 index 517a8ff7121e..000000000000 --- a/trunk/drivers/clk/clk-nomadik.c +++ /dev/null @@ -1,47 +0,0 @@ -#include -#include -#include -#include -#include - -/* - * The Nomadik clock tree is described in the STN8815A12 DB V4.2 - * reference manual for the chip, page 94 ff. - */ - -void __init nomadik_clk_init(void) -{ - struct clk *clk; - - clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); - clk_register_clkdev(clk, "apb_pclk", NULL); - clk_register_clkdev(clk, NULL, "gpio.0"); - clk_register_clkdev(clk, NULL, "gpio.1"); - clk_register_clkdev(clk, NULL, "gpio.2"); - clk_register_clkdev(clk, NULL, "gpio.3"); - clk_register_clkdev(clk, NULL, "rng"); - - /* - * The 2.4 MHz TIMCLK reference clock is active at boot time, this is - * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used - * by the timers and watchdog. See page 105 ff. - */ - clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT, - 2400000); - clk_register_clkdev(clk, NULL, "mtu0"); - clk_register_clkdev(clk, NULL, "mtu1"); - - /* - * At boot time, PLL2 is set to generate a set of fixed clocks, - * one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD - * I2C, IrDA, USB and SSP blocks. - */ - clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT, - 48000000); - clk_register_clkdev(clk, NULL, "uart0"); - clk_register_clkdev(clk, NULL, "uart1"); - clk_register_clkdev(clk, NULL, "mmci"); - clk_register_clkdev(clk, NULL, "ssp"); - clk_register_clkdev(clk, NULL, "nmk-i2c.0"); - clk_register_clkdev(clk, NULL, "nmk-i2c.1"); -} diff --git a/trunk/drivers/mmc/host/sdhci-tegra.c b/trunk/drivers/mmc/host/sdhci-tegra.c index 6e5338a071ce..b38d8a78f6a0 100644 --- a/trunk/drivers/mmc/host/sdhci-tegra.c +++ b/trunk/drivers/mmc/host/sdhci-tegra.c @@ -223,7 +223,6 @@ static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata( { struct tegra_sdhci_platform_data *plat; struct device_node *np = pdev->dev.of_node; - u32 bus_width; if (!np) return NULL; @@ -237,9 +236,7 @@ static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata( plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0); - - if (of_property_read_u32(np, "bus-width", &bus_width) == 0 && - bus_width == 8) + if (of_find_property(np, "support-8bit", NULL)) plat->is_8bit = 1; return plat; diff --git a/trunk/include/linux/platform_data/clk-nomadik.h b/trunk/include/linux/platform_data/clk-nomadik.h deleted file mode 100644 index 5713c87b2477..000000000000 --- a/trunk/include/linux/platform_data/clk-nomadik.h +++ /dev/null @@ -1,2 +0,0 @@ -/* Minimal platform data header */ -void nomadik_clk_init(void); diff --git a/trunk/sound/soc/tegra/Kconfig b/trunk/sound/soc/tegra/Kconfig index 76dc230f2bb0..c1c8e955f4d3 100644 --- a/trunk/sound/soc/tegra/Kconfig +++ b/trunk/sound/soc/tegra/Kconfig @@ -58,9 +58,17 @@ config SND_SOC_TEGRA_WM8753 Say Y or M here if you want to add support for SoC audio on Tegra boards using the WM8753 codec, such as Whistler. +config MACH_HAS_SND_SOC_TEGRA_WM8903 + bool + help + Machines that use the SND_SOC_TEGRA_WM8903 driver should select + this config option, in order to allow the user to enable + SND_SOC_TEGRA_WM8903. + config SND_SOC_TEGRA_WM8903 tristate "SoC Audio support for Tegra boards using a WM8903 codec" depends on SND_SOC_TEGRA && I2C + depends on MACH_HAS_SND_SOC_TEGRA_WM8903 select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC select SND_SOC_TEGRA30_I2S if ARCH_TEGRA_3x_SOC select SND_SOC_WM8903 @@ -71,7 +79,7 @@ config SND_SOC_TEGRA_WM8903 config SND_SOC_TEGRA_TRIMSLICE tristate "SoC Audio support for TrimSlice board" - depends on SND_SOC_TEGRA && I2C + depends on SND_SOC_TEGRA && MACH_TRIMSLICE && I2C select SND_SOC_TEGRA20_I2S if ARCH_TEGRA_2x_SOC select SND_SOC_TLV320AIC23 help