From 70a281727be1480506c2621f93b8099ab1307017 Mon Sep 17 00:00:00 2001 From: Benjamin Herrenschmidt Date: Thu, 18 Dec 2008 19:13:46 +0000 Subject: [PATCH] --- yaml --- r: 123117 b: refs/heads/master c: 760ec0e02d8a13d0ed60d99f47879d4aa8ef1910 h: refs/heads/master i: 123115: 93820a122dc93a4bb00c8c8a37fca88deb3c5938 v: v3 --- [refs] | 2 +- trunk/arch/powerpc/mm/tlb_nohash_low.S | 19 ++++++++++--------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/[refs] b/[refs] index 3ff14937a1f3..043da072858d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2a4aca1144394653269720ffbb5a325a77abd5fa +refs/heads/master: 760ec0e02d8a13d0ed60d99f47879d4aa8ef1910 diff --git a/trunk/arch/powerpc/mm/tlb_nohash_low.S b/trunk/arch/powerpc/mm/tlb_nohash_low.S index 763c59fe0076..f900a39e6ec4 100644 --- a/trunk/arch/powerpc/mm/tlb_nohash_low.S +++ b/trunk/arch/powerpc/mm/tlb_nohash_low.S @@ -75,18 +75,19 @@ _GLOBAL(_tlbil_va) mfspr r5,SPRN_MMUCR rlwimi r5,r4,0,24,31 /* Set TID */ - /* We have to run the search with interrupts disabled, even critical - * and debug interrupts (in fact the only critical exceptions we have - * are debug and machine check). Otherwise an interrupt which causes - * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ + /* We have to run the search with interrupts disabled, otherwise + * an interrupt which causes a TLB miss can clobber the MMUCR + * between the mtspr and the tlbsx. + * + * Critical and Machine Check interrupts take care of saving + * and restoring MMUCR, so only normal interrupts have to be + * taken care of. + */ mfmsr r4 - lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha - addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l - andc r6,r4,r6 - mtmsr r6 + wrteei 0 mtspr SPRN_MMUCR,r5 tlbsx. r3, 0, r3 - mtmsr r4 + wrtee r4 bne 1f sync /* There are only 64 TLB entries, so r3 < 64,