From 713b1fe25d663896128cf90f14d227509df2adf2 Mon Sep 17 00:00:00 2001
From: Kukjin Kim <kgene.kim@samsung.com>
Date: Sat, 5 Jan 2013 08:32:55 -0800
Subject: [PATCH] --- yaml --- r: 348486 b: refs/heads/master c:
 61bcbc2af8be4cafb5723d4bd306053b70f52a7a h: refs/heads/master v: v3

---
 [refs]                              | 2 +-
 trunk/arch/arm/mach-exynos/common.c | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 3341c325307f..05e59458774b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b2318482a3a9818af9138a323263a0f761a5e5f8
+refs/heads/master: 61bcbc2af8be4cafb5723d4bd306053b70f52a7a
diff --git a/trunk/arch/arm/mach-exynos/common.c b/trunk/arch/arm/mach-exynos/common.c
index d6d0dc651089..1a89824a5f78 100644
--- a/trunk/arch/arm/mach-exynos/common.c
+++ b/trunk/arch/arm/mach-exynos/common.c
@@ -424,11 +424,18 @@ static void __init exynos5_init_clocks(int xtal)
 {
 	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 
+	/* EXYNOS5440 can support only common clock framework */
+
+	if (soc_is_exynos5440())
+		return;
+
+#ifdef CONFIG_SOC_EXYNOS5250
 	s3c24xx_register_baseclocks(xtal);
 	s5p_register_clocks(xtal);
 
 	exynos5_register_clocks();
 	exynos5_setup_clocks();
+#endif
 }
 
 #define COMBINER_ENABLE_SET	0x0