From 719e0eef725f27a5ac6ea5c0cf3f1b448615fc6c Mon Sep 17 00:00:00 2001
From: Al Viro <viro@ftp.linux.org.uk>
Date: Thu, 29 Sep 2005 00:34:30 +0100
Subject: [PATCH] --- yaml --- r: 9421 b: refs/heads/master c:
 a7625d6e49cb4fd94be7576d85422c33003101b7 h: refs/heads/master i:   9419:
 dd802e61ac943b313fd626e130ff1b6e6c7916d2 v: v3

---
 [refs]                          | 2 +-
 trunk/arch/ppc/syslib/mv64x60.c | 4 ++--
 trunk/include/asm-ppc/mv64x60.h | 4 ++--
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/[refs] b/[refs]
index 2e9d282b9d50..db6dc032eaea 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 9fcdfcd90526c8c5c2bd117fd3713f8f0f1a46a8
+refs/heads/master: a7625d6e49cb4fd94be7576d85422c33003101b7
diff --git a/trunk/arch/ppc/syslib/mv64x60.c b/trunk/arch/ppc/syslib/mv64x60.c
index 839f8872826f..4849850a59ed 100644
--- a/trunk/arch/ppc/syslib/mv64x60.c
+++ b/trunk/arch/ppc/syslib/mv64x60.c
@@ -34,7 +34,7 @@ u8 mv64x60_pci_exclude_bridge = 1;
 DEFINE_SPINLOCK(mv64x60_lock);
 
 static phys_addr_t 	mv64x60_bridge_pbase;
-static void 		*mv64x60_bridge_vbase;
+static void 		__iomem *mv64x60_bridge_vbase;
 static u32		mv64x60_bridge_type = MV64x60_TYPE_INVALID;
 static u32		mv64x60_bridge_rev;
 #if defined(CONFIG_SYSFS) && !defined(CONFIG_GT64260)
@@ -938,7 +938,7 @@ mv64x60_setup_for_chip(struct mv64x60_handle *bh)
  *
  * Return the virtual address of the bridge's registers.
  */
-void *
+void __iomem *
 mv64x60_get_bridge_vbase(void)
 {
 	return mv64x60_bridge_vbase;
diff --git a/trunk/include/asm-ppc/mv64x60.h b/trunk/include/asm-ppc/mv64x60.h
index 75c2ffa26b26..ee2f9188cc64 100644
--- a/trunk/include/asm-ppc/mv64x60.h
+++ b/trunk/include/asm-ppc/mv64x60.h
@@ -233,7 +233,7 @@ struct mv64x60_chip_info {
 struct mv64x60_handle {
 	u32		type;		/* type of bridge */
 	u32		rev;		/* revision of bridge */
-	void		*v_base;	/* virtual base addr of bridge regs */
+	void		__iomem *v_base;/* virtual base addr of bridge regs */
 	phys_addr_t	p_base;		/* physical base addr of bridge regs */
 
 	u32		pci_mode_a;	/* pci 0 mode: conventional pci, pci-x*/
@@ -303,7 +303,7 @@ void mv64x60_alloc_hose(struct mv64x60_handle *bh, u32 cfg_addr,
 	u32 cfg_data, struct pci_controller **hose);
 int mv64x60_get_type(struct mv64x60_handle *bh);
 int mv64x60_setup_for_chip(struct mv64x60_handle *bh);
-void *mv64x60_get_bridge_vbase(void);
+void __iomem *mv64x60_get_bridge_vbase(void);
 u32 mv64x60_get_bridge_type(void);
 u32 mv64x60_get_bridge_rev(void);
 void mv64x60_get_mem_windows(struct mv64x60_handle *bh,