From 71a383f58b04f4454b5ba44d169ecba98f5fcb78 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Tue, 22 Nov 2011 23:54:25 +0800 Subject: [PATCH] --- yaml --- r: 281798 b: refs/heads/master c: b07fed455c883f07f8e847f5b0d79975b4dc8e7a h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-mxs/clock-mx28.c | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 109c7210e8cd..675b9401eebb 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 4c0174c52010435e6e0158500033868dc404f014 +refs/heads/master: b07fed455c883f07f8e847f5b0d79975b4dc8e7a diff --git a/trunk/arch/arm/mach-mxs/clock-mx28.c b/trunk/arch/arm/mach-mxs/clock-mx28.c index 60c189a441b7..df0ad3ce234b 100644 --- a/trunk/arch/arm/mach-mxs/clock-mx28.c +++ b/trunk/arch/arm/mach-mxs/clock-mx28.c @@ -814,6 +814,15 @@ int __init mx28_clocks_init(void) clk_set_parent(&saif0_clk, &pll0_clk); clk_set_parent(&saif1_clk, &pll0_clk); + /* + * Set an initial clock rate for the saif internal logic to work + * properly. This is important when working in EXTMASTER mode that + * uses the other saif's BITCLK&LRCLK but it still needs a basic + * clock which should be fast enough for the internal logic. + */ + clk_set_rate(&saif0_clk, 24000000); + clk_set_rate(&saif1_clk, 24000000); + clkdev_add_table(lookups, ARRAY_SIZE(lookups)); mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);