diff --git a/[refs] b/[refs] index c213eff1e495..949a45f25f11 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6e1d521b9d1201214ec4a67a7e4360232be5f963 +refs/heads/master: 89d4a1753b6632327f18d6c8e0842b366b736621 diff --git a/trunk/Documentation/devicetree/bindings/arm/vexpress.txt b/trunk/Documentation/devicetree/bindings/arm/vexpress.txt deleted file mode 100644 index ec8b50cbb2e8..000000000000 --- a/trunk/Documentation/devicetree/bindings/arm/vexpress.txt +++ /dev/null @@ -1,146 +0,0 @@ -ARM Versatile Express boards family ------------------------------------ - -ARM's Versatile Express platform consists of a motherboard and one -or more daughterboards (tiles). The motherboard provides a set of -peripherals. Processor and RAM "live" on the tiles. - -The motherboard and each core tile should be described by a separate -Device Tree source file, with the tile's description including -the motherboard file using a /include/ directive. As the motherboard -can be initialized in one of two different configurations ("memory -maps"), care must be taken to include the correct one. - -Required properties in the root node: -- compatible value: - compatible = "arm,vexpress,", "arm,vexpress"; - where is the full tile model name (as used in the tile's - Technical Reference Manual), eg.: - - for Coretile Express A5x2 (V2P-CA5s): - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - - for Coretile Express A9x4 (V2P-CA9): - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - If a tile comes in several variants or can be used in more then one - configuration, the compatible value should be: - compatible = "arm,vexpress,,", \ - "arm,vexpress,", "arm,vexpress"; - eg: - - Coretile Express A15x2 (V2P-CA15) with Tech Chip 1: - compatible = "arm,vexpress,v2p-ca15,tc1", \ - "arm,vexpress,v2p-ca15", "arm,vexpress"; - - LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM: - compatible = "arm,vexpress,v2f-2xv6,ca7x3", \ - "arm,vexpress,v2f-2xv6", "arm,vexpress"; - -Optional properties in the root node: -- tile model name (use name from the tile's Technical Reference - Manual, eg. "V2P-CA5s") - model = ""; -- tile's HBI number (unique ARM's board model ID, visible on the - PCB's silkscreen) in hexadecimal transcription: - arm,hbi = <0xhbi> - eg: - - for Coretile Express A5x2 (V2P-CA5s) HBI-0191: - arm,hbi = <0x191>; - - Coretile Express A9x4 (V2P-CA9) HBI-0225: - arm,hbi = <0x225>; - -Top-level standard "cpus" node is required. It must contain a node -with device_type = "cpu" property for every available core, eg.: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - -The motherboard description file provides a single "motherboard" node -using 2 address cells corresponding to the Static Memory Bus used -between the motherboard and the tile. The first cell defines the Chip -Select (CS) line number, the second cell address offset within the CS. -All interrupt lines between the motherboard and the tile are active -high and are described using single cell. - -Optional properties of the "motherboard" node: -- motherboard's memory map variant: - arm,v2m-memory-map = ""; - where name is one of: - - "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also - referred to as "ARM Cortex-A Series memory map": - arm,v2m-memory-map = "rs1"; - When this property is missing, the motherboard is using the original - memory map (also known as the "Legacy memory map", primarily used - with the original CoreTile Express A9x4) with peripherals on CS7. - -Motherboard .dtsi files provide a set of labelled peripherals that -can be used to obtain required phandle in the tile's "aliases" node: -- UARTs, note that the numbers correspond to the physical connectors - on the motherboard's back panel: - v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3 -- I2C controllers: - v2m_i2c_dvi and v2m_i2c_pcie -- SP804 timers: - v2m_timer01 and v2m_timer23 - -Current Linux implementation requires a "arm,v2m_timer" alias -pointing at one of the motherboard's SP804 timers, if it is to be -used as the system timer. This alias should be defined in the -motherboard files. - -The tile description must define "ranges", "interrupt-map-mask" and -"interrupt-map" properties to translate the motherboard's address -and interrupt space into one used by the tile's processor. - -Abbreviated example: - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - }; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - motherboard { - /* CS0 is visible at 0x08000000 */ - ranges = <0 0 0x08000000 0x04000000>; - interrupt-map-mask = <0 0 63>; - /* Active high IRQ 0 is connected to GIC's SPI0 */ - interrupt-map = <0 0 0 &gic 0 0 4>; - }; -}; - -/include/ "vexpress-v2m-rs1.dtsi" diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 09a04b4141a8..57dd0f56cd37 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -269,6 +269,7 @@ S: Orphan F: drivers/platform/x86/wmi.c AD1889 ALSA SOUND DRIVER +M: Kyle McMartin M: Thibaut Varene W: http://wiki.parisc-linux.org/AD1889 L: linux-parisc@vger.kernel.org @@ -3046,6 +3047,7 @@ F: drivers/hwspinlock/hwspinlock_* F: include/linux/hwspinlock.h HARMONY SOUND DRIVER +M: Kyle McMartin L: linux-parisc@vger.kernel.org S: Maintained F: sound/parisc/harmony.* @@ -5007,8 +5009,9 @@ F: Documentation/blockdev/paride.txt F: drivers/block/paride/ PARISC ARCHITECTURE -M: "James E.J. Bottomley" +M: Kyle McMartin M: Helge Deller +M: "James E.J. Bottomley" L: linux-parisc@vger.kernel.org W: http://www.parisc-linux.org/ Q: http://patchwork.kernel.org/project/linux-parisc/list/ @@ -5867,7 +5870,7 @@ S: Maintained F: drivers/mmc/host/sdhci-spear.c SECURITY SUBSYSTEM -M: James Morris +M: James Morris L: linux-security-module@vger.kernel.org (suggested Cc:) T: git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git W: http://security.wiki.kernel.org/ @@ -5880,7 +5883,7 @@ S: Supported SELINUX SECURITY MODULE M: Stephen Smalley -M: James Morris +M: James Morris M: Eric Paris L: selinux@tycho.nsa.gov (subscribers-only, general discussion) W: http://selinuxproject.org diff --git a/trunk/Makefile b/trunk/Makefile index b61a9638b6fc..7c44b676b77a 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 3 SUBLEVEL = 0 -EXTRAVERSION = -rc5 +EXTRAVERSION = -rc3 NAME = Saber-toothed Squirrel # *DOCUMENTATION* diff --git a/trunk/arch/arm/boot/dts/exynos4210.dtsi b/trunk/arch/arm/boot/dts/exynos4210.dtsi index a1dd2ee83753..63d7578856c1 100644 --- a/trunk/arch/arm/boot/dts/exynos4210.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4210.dtsi @@ -29,7 +29,6 @@ compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; - cpu-offset = <0x8000>; reg = <0x10490000 0x1000>, <0x10480000 0x100>; }; diff --git a/trunk/arch/arm/boot/dts/imx51-babbage.dts b/trunk/arch/arm/boot/dts/imx51-babbage.dts index 9949e6060dee..564cb8c19f15 100644 --- a/trunk/arch/arm/boot/dts/imx51-babbage.dts +++ b/trunk/arch/arm/boot/dts/imx51-babbage.dts @@ -56,95 +56,8 @@ compatible = "fsl,mc13892"; spi-max-frequency = <6000000>; reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <8>; - - regulators { - sw1_reg: sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: sw3 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: sw4 { - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - - vpll_reg: vpll { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - vdig_reg: vdig { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1650000>; - regulator-boot-on; - }; - - vsd_reg: vsd { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3150000>; - }; - - vusb2_reg: vusb2 { - regulator-min-microvolt = <2400000>; - regulator-max-microvolt = <2775000>; - regulator-boot-on; - regulator-always-on; - }; - - vvideo_reg: vvideo { - regulator-min-microvolt = <2775000>; - regulator-max-microvolt = <2775000>; - }; - - vaudio_reg: vaudio { - regulator-min-microvolt = <2300000>; - regulator-max-microvolt = <3000000>; - }; - - vcam_reg: vcam { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3000000>; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - }; + mc13xxx-irq-gpios = <&gpio1 8 0>; + fsl,mc13xxx-uses-regulator; }; flash: at45db321d@1 { diff --git a/trunk/arch/arm/boot/dts/imx6q-arm2.dts b/trunk/arch/arm/boot/dts/imx6q-arm2.dts index ce1c8238c897..c3977e0478b9 100644 --- a/trunk/arch/arm/boot/dts/imx6q-arm2.dts +++ b/trunk/arch/arm/boot/dts/imx6q-arm2.dts @@ -36,13 +36,11 @@ usdhc@02198000 { /* uSDHC3 */ cd-gpios = <&gpio6 11 0>; wp-gpios = <&gpio6 14 0>; - vmmc-supply = <®_3p3v>; status = "okay"; }; usdhc@0219c000 { /* uSDHC4 */ fsl,card-wired; - vmmc-supply = <®_3p3v>; status = "okay"; }; @@ -52,18 +50,6 @@ }; }; - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - leds { compatible = "gpio-leds"; diff --git a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts index 4663a4e5a285..08d920de7286 100644 --- a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -32,52 +32,18 @@ usdhc@02198000 { /* uSDHC3 */ cd-gpios = <&gpio7 0 0>; wp-gpios = <&gpio7 1 0>; - vmmc-supply = <®_3p3v>; status = "okay"; }; usdhc@0219c000 { /* uSDHC4 */ cd-gpios = <&gpio2 6 0>; wp-gpios = <&gpio2 7 0>; - vmmc-supply = <®_3p3v>; status = "okay"; }; uart2: uart@021e8000 { status = "okay"; }; - - i2c@021a0000 { /* I2C1 */ - status = "okay"; - clock-frequency = <100000>; - - codec: sgtl5000@0a { - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; - }; - }; - }; - }; - - regulators { - compatible = "simple-bus"; - - reg_2p5v: 2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap3-beagle.dts b/trunk/arch/arm/boot/dts/omap3-beagle.dts index 9f72cd4cf308..9486be62bcdd 100644 --- a/trunk/arch/arm/boot/dts/omap3-beagle.dts +++ b/trunk/arch/arm/boot/dts/omap3-beagle.dts @@ -13,6 +13,15 @@ model = "TI OMAP3 BeagleBoard"; compatible = "ti,omap3-beagle", "ti,omap3"; + /* + * Since the initial device tree board file does not create any + * devices (MMC, network...), the only way to boot is to provide a + * ramdisk. + */ + chosen { + bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ diff --git a/trunk/arch/arm/boot/dts/omap3-evm.dts b/trunk/arch/arm/boot/dts/omap3-evm.dts deleted file mode 100644 index 2eee16ec59b4..000000000000 --- a/trunk/arch/arm/boot/dts/omap3-evm.dts +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -/include/ "omap3.dtsi" - -/ { - model = "TI OMAP3 EVM (OMAP3530, AM/DM37x)"; - compatible = "ti,omap3-evm", "ti,omap3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; -}; diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi index e69806432874..216c3317461d 100644 --- a/trunk/arch/arm/boot/dts/omap3.dtsi +++ b/trunk/arch/arm/boot/dts/omap3.dtsi @@ -67,49 +67,28 @@ #interrupt-cells = <1>; }; - uart1: serial@4806a000 { + uart1: serial@0x4806a000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; - uart2: serial@4806c000 { + uart2: serial@0x4806c000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; - uart3: serial@49020000 { + uart3: serial@0x49020000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; - uart4: serial@49042000 { + uart4: serial@0x49042000 { compatible = "ti,omap3-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; - - i2c1: i2c@48070000 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap3-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/omap4-panda.dts b/trunk/arch/arm/boot/dts/omap4-panda.dts index 9755ad5917f8..c7026578ce7d 100644 --- a/trunk/arch/arm/boot/dts/omap4-panda.dts +++ b/trunk/arch/arm/boot/dts/omap4-panda.dts @@ -13,6 +13,15 @@ model = "TI OMAP4 PandaBoard"; compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; + /* + * Since the initial device tree board file does not create any + * devices (MMC, network...), the only way to boot is to provide a + * ramdisk. + */ + chosen { + bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ diff --git a/trunk/arch/arm/boot/dts/omap4-sdp.dts b/trunk/arch/arm/boot/dts/omap4-sdp.dts index 63c6b2b2bf42..066e28c90328 100644 --- a/trunk/arch/arm/boot/dts/omap4-sdp.dts +++ b/trunk/arch/arm/boot/dts/omap4-sdp.dts @@ -13,6 +13,15 @@ model = "TI OMAP4 SDP board"; compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; + /* + * Since the initial device tree board file does not create any + * devices (MMC, network...), the only way to boot is to provide a + * ramdisk. + */ + chosen { + bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug"; + }; + memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi index 3d35559e77bc..e8fe75fac7c5 100644 --- a/trunk/arch/arm/boot/dts/omap4.dtsi +++ b/trunk/arch/arm/boot/dts/omap4.dtsi @@ -99,61 +99,33 @@ gic: interrupt-controller@48241000 { compatible = "arm,cortex-a9-gic"; interrupt-controller; - #interrupt-cells = <3>; + #interrupt-cells = <1>; reg = <0x48241000 0x1000>, <0x48240100 0x0100>; }; - uart1: serial@4806a000 { + uart1: serial@0x4806a000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; - uart2: serial@4806c000 { + uart2: serial@0x4806c000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; - uart3: serial@48020000 { + uart3: serial@0x48020000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; - uart4: serial@4806e000 { + uart4: serial@0x4806e000 { compatible = "ti,omap4-uart"; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; - - i2c1: i2c@48070000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c1"; - }; - - i2c2: i2c@48072000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c2"; - }; - - i2c3: i2c@48060000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c3"; - }; - - i2c4: i2c@48350000 { - compatible = "ti,omap4-i2c"; - #address-cells = <1>; - #size-cells = <0>; - ti,hwmods = "i2c4"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/tegra-paz00.dts b/trunk/arch/arm/boot/dts/tegra-paz00.dts index 825d2957da0b..1a1d7023b69b 100644 --- a/trunk/arch/arm/boot/dts/tegra-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra-paz00.dts @@ -46,11 +46,11 @@ }; serial@70006200 { - clock-frequency = <216000000>; + status = "disable"; }; serial@70006300 { - status = "disable"; + clock-frequency = <216000000>; }; serial@70006400 { @@ -60,7 +60,7 @@ sdhci@c8000000 { cd-gpios = <&gpio 173 0>; /* gpio PV5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 169 0>; /* gpio PV1 */ + power-gpios = <&gpio 155 0>; /* gpio PT3 */ }; sdhci@c8000200 { diff --git a/trunk/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/trunk/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi deleted file mode 100644 index 16076e2d0934..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ /dev/null @@ -1,201 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * RS1 memory map ("ARM Cortex-A Series memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * original variant (vexpress-v2m.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m.dtsi! - */ - -/ { - aliases { - arm,v2m_timer = &v2m_timer01; - }; - - motherboard { - compatible = "simple-bus"; - arm,v2m-memory-map = "rs1"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <4 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@1,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <1 0x00000000 0x02000000>; - bank-width = <4>; - }; - - vram@2,00000000 { - compatible = "arm,vexpress-vram"; - reg = <2 0x00000000 0x00800000>; - }; - - ethernet@2,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <2 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - }; - - usb@2,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <2 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@3,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 3 0 0x200000>; - - sysreg@010000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x010000 0x1000>; - }; - - sysctl@020000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x020000 0x1000>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@030000 { - compatible = "arm,versatile-i2c"; - reg = <0x030000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@040000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x040000 0x1000>; - interrupts = <11>; - }; - - mmci@050000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x050000 0x1000>; - interrupts = <9 10>; - }; - - kmi@060000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x060000 0x1000>; - interrupts = <12>; - }; - - kmi@070000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x070000 0x1000>; - interrupts = <13>; - }; - - v2m_serial0: uart@090000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x090000 0x1000>; - interrupts = <5>; - }; - - v2m_serial1: uart@0a0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a0000 0x1000>; - interrupts = <6>; - }; - - v2m_serial2: uart@0b0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b0000 0x1000>; - interrupts = <7>; - }; - - v2m_serial3: uart@0c0000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c0000 0x1000>; - interrupts = <8>; - }; - - wdt@0f0000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f0000 0x1000>; - interrupts = <0>; - }; - - v2m_timer01: timer@110000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x110000 0x1000>; - interrupts = <2>; - }; - - v2m_timer23: timer@120000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x120000 0x1000>; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@160000 { - compatible = "arm,versatile-i2c"; - reg = <0x160000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@170000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x170000 0x1000>; - interrupts = <4>; - }; - - compact-flash@1a0000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a0000 0x100 - 0x1a0100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f0000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f0000 0x1000>; - interrupts = <14>; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/vexpress-v2m.dtsi b/trunk/arch/arm/boot/dts/vexpress-v2m.dtsi deleted file mode 100644 index a6c9c7c82d53..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2m.dtsi +++ /dev/null @@ -1,200 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * Motherboard Express uATX - * V2M-P1 - * - * HBI-0190D - * - * Original memory map ("Legacy memory map" in the board's - * Technical Reference Manual) - * - * WARNING! The hardware described in this file is independent from the - * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong - * correspondence between the two configurations. - * - * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT - * CHANGES TO vexpress-v2m-rs1.dtsi! - */ - -/ { - aliases { - arm,v2m_timer = &v2m_timer01; - }; - - motherboard { - compatible = "simple-bus"; - #address-cells = <2>; /* SMB chipselect number and offset */ - #size-cells = <1>; - #interrupt-cells = <1>; - - flash@0,00000000 { - compatible = "arm,vexpress-flash", "cfi-flash"; - reg = <0 0x00000000 0x04000000>, - <1 0x00000000 0x04000000>; - bank-width = <4>; - }; - - psram@2,00000000 { - compatible = "arm,vexpress-psram", "mtd-ram"; - reg = <2 0x00000000 0x02000000>; - bank-width = <4>; - }; - - vram@3,00000000 { - compatible = "arm,vexpress-vram"; - reg = <3 0x00000000 0x00800000>; - }; - - ethernet@3,02000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; - reg = <3 0x02000000 0x10000>; - interrupts = <15>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - }; - - usb@3,03000000 { - compatible = "nxp,usb-isp1761"; - reg = <3 0x03000000 0x20000>; - interrupts = <16>; - port1-otg; - }; - - iofpga@7,00000000 { - compatible = "arm,amba-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 7 0 0x20000>; - - sysreg@00000 { - compatible = "arm,vexpress-sysreg"; - reg = <0x00000 0x1000>; - }; - - sysctl@01000 { - compatible = "arm,sp810", "arm,primecell"; - reg = <0x01000 0x1000>; - }; - - /* PCI-E I2C bus */ - v2m_i2c_pcie: i2c@02000 { - compatible = "arm,versatile-i2c"; - reg = <0x02000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - pcie-switch@60 { - compatible = "idt,89hpes32h8"; - reg = <0x60>; - }; - }; - - aaci@04000 { - compatible = "arm,pl041", "arm,primecell"; - reg = <0x04000 0x1000>; - interrupts = <11>; - }; - - mmci@05000 { - compatible = "arm,pl180", "arm,primecell"; - reg = <0x05000 0x1000>; - interrupts = <9 10>; - }; - - kmi@06000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x06000 0x1000>; - interrupts = <12>; - }; - - kmi@07000 { - compatible = "arm,pl050", "arm,primecell"; - reg = <0x07000 0x1000>; - interrupts = <13>; - }; - - v2m_serial0: uart@09000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x09000 0x1000>; - interrupts = <5>; - }; - - v2m_serial1: uart@0a000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0a000 0x1000>; - interrupts = <6>; - }; - - v2m_serial2: uart@0b000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0b000 0x1000>; - interrupts = <7>; - }; - - v2m_serial3: uart@0c000 { - compatible = "arm,pl011", "arm,primecell"; - reg = <0x0c000 0x1000>; - interrupts = <8>; - }; - - wdt@0f000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x0f000 0x1000>; - interrupts = <0>; - }; - - v2m_timer01: timer@11000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x11000 0x1000>; - interrupts = <2>; - }; - - v2m_timer23: timer@12000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x12000 0x1000>; - }; - - /* DVI I2C bus */ - v2m_i2c_dvi: i2c@16000 { - compatible = "arm,versatile-i2c"; - reg = <0x16000 0x1000>; - - #address-cells = <1>; - #size-cells = <0>; - - dvi-transmitter@39 { - compatible = "sil,sii9022-tpi", "sil,sii9022"; - reg = <0x39>; - }; - - dvi-transmitter@60 { - compatible = "sil,sii9022-cpi", "sil,sii9022"; - reg = <0x60>; - }; - }; - - rtc@17000 { - compatible = "arm,pl031", "arm,primecell"; - reg = <0x17000 0x1000>; - interrupts = <4>; - }; - - compact-flash@1a000 { - compatible = "arm,vexpress-cf", "ata-generic"; - reg = <0x1a000 0x100 - 0x1a100 0xf00>; - reg-shift = <2>; - }; - - clcd@1f000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x1f000 0x1000>; - interrupts = <14>; - }; - }; - }; -}; diff --git a/trunk/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/trunk/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts deleted file mode 100644 index 941b161ab78c..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ /dev/null @@ -1,157 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A15x2 (version with Test Chip 1) - * Cortex-A15 MPCore (V2P-CA15) - * - * HBI-0237A - */ - -/dts-v1/; - -/ { - model = "V2P-CA15"; - arm,hbi = <0x237>; - compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <0>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a15"; - reg = <1>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - hdlcd@2b000000 { - compatible = "arm,hdlcd"; - reg = <0x2b000000 0x1000>; - interrupts = <0 85 4>; - }; - - memory-controller@2b0a0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2b0a0000 0x1000>; - }; - - wdt@2b060000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x2b060000 0x1000>; - interrupts = <98>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c002000 0x100>; - }; - - memory-controller@7ffd0000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x7ffd0000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - }; - - dma@7ffb0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x7ffb0000 0x1000>; - interrupts = <0 92 4>, - <0 88 4>, - <0 89 4>, - <0 90 4>, - <0 91 4>; - }; - - pmu { - compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - motherboard { - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; -}; - -/include/ "vexpress-v2m-rs1.dtsi" diff --git a/trunk/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/trunk/arch/arm/boot/dts/vexpress-v2p-ca5s.dts deleted file mode 100644 index 6905e66d4748..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ /dev/null @@ -1,162 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A5x2 - * Cortex-A5 MPCore (V2P-CA5s) - * - * HBI-0225B - */ - -/dts-v1/; - -/ { - model = "V2P-CA5s"; - arm,hbi = <0x225>; - compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a5"; - reg = <1>; - next-level-cache = <&L2>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - hdlcd@2a110000 { - compatible = "arm,hdlcd"; - reg = <0x2a110000 0x1000>; - interrupts = <0 85 4>; - }; - - memory-controller@2a150000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x2a150000 0x1000>; - }; - - memory-controller@2a190000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x2a190000 0x1000>; - interrupts = <0 86 4>, - <0 87 4>; - }; - - scu@2c000000 { - compatible = "arm,cortex-a5-scu"; - reg = <0x2c000000 0x58>; - }; - - timer@2c000600 { - compatible = "arm,cortex-a5-twd-timer"; - reg = <0x2c000600 0x38>; - interrupts = <1 2 0x304>, - <1 3 0x304>; - }; - - gic: interrupt-controller@2c001000 { - compatible = "arm,corex-a5-gic", "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x2c001000 0x1000>, - <0x2c000100 0x100>; - }; - - L2: cache-controller@2c0f0000 { - compatible = "arm,pl310-cache"; - reg = <0x2c0f0000 0x1000>; - interrupts = <0 84 4>; - cache-level = <2>; - }; - - pmu { - compatible = "arm,cortex-a5-pmu", "arm,cortex-a9-pmu"; - interrupts = <0 68 4>, - <0 69 4>; - }; - - motherboard { - ranges = <0 0 0x08000000 0x04000000>, - <1 0 0x14000000 0x04000000>, - <2 0 0x18000000 0x04000000>, - <3 0 0x1c000000 0x04000000>, - <4 0 0x0c000000 0x04000000>, - <5 0 0x10000000 0x04000000>; - - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; -}; - -/include/ "vexpress-v2m-rs1.dtsi" diff --git a/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts deleted file mode 100644 index da778693be54..000000000000 --- a/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ /dev/null @@ -1,192 +0,0 @@ -/* - * ARM Ltd. Versatile Express - * - * CoreTile Express A9x4 - * Cortex-A9 MPCore (V2P-CA9) - * - * HBI-0191B - */ - -/dts-v1/; - -/ { - model = "V2P-CA9"; - arm,hbi = <0x191>; - compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; - interrupt-parent = <&gic>; - #address-cells = <1>; - #size-cells = <1>; - - chosen { }; - - aliases { - serial0 = &v2m_serial0; - serial1 = &v2m_serial1; - serial2 = &v2m_serial2; - serial3 = &v2m_serial3; - i2c0 = &v2m_i2c_dvi; - i2c1 = &v2m_i2c_pcie; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - clcd@10020000 { - compatible = "arm,pl111", "arm,primecell"; - reg = <0x10020000 0x1000>; - interrupts = <0 44 4>; - }; - - memory-controller@100e0000 { - compatible = "arm,pl341", "arm,primecell"; - reg = <0x100e0000 0x1000>; - }; - - memory-controller@100e1000 { - compatible = "arm,pl354", "arm,primecell"; - reg = <0x100e1000 0x1000>; - interrupts = <0 45 4>, - <0 46 4>; - }; - - timer@100e4000 { - compatible = "arm,sp804", "arm,primecell"; - reg = <0x100e4000 0x1000>; - interrupts = <0 48 4>, - <0 49 4>; - }; - - watchdog@100e5000 { - compatible = "arm,sp805", "arm,primecell"; - reg = <0x100e5000 0x1000>; - interrupts = <0 51 4>; - }; - - scu@1e000000 { - compatible = "arm,cortex-a9-scu"; - reg = <0x1e000000 0x58>; - }; - - timer@1e000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x1e000600 0x20>; - interrupts = <1 2 0xf04>, - <1 3 0xf04>; - }; - - gic: interrupt-controller@1e001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0x1e001000 0x1000>, - <0x1e000100 0x100>; - }; - - L2: cache-controller@1e00a000 { - compatible = "arm,pl310-cache"; - reg = <0x1e00a000 0x1000>; - interrupts = <0 43 4>; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <1 1 1>; - }; - - pmu { - compatible = "arm,cortex-a9-pmu"; - interrupts = <0 60 4>, - <0 61 4>, - <0 62 4>, - <0 63 4>; - }; - - motherboard { - ranges = <0 0 0x40000000 0x04000000>, - <1 0 0x44000000 0x04000000>, - <2 0 0x48000000 0x04000000>, - <3 0 0x4c000000 0x04000000>, - <7 0 0x10000000 0x00020000>; - - interrupt-map-mask = <0 0 63>; - interrupt-map = <0 0 0 &gic 0 0 4>, - <0 0 1 &gic 0 1 4>, - <0 0 2 &gic 0 2 4>, - <0 0 3 &gic 0 3 4>, - <0 0 4 &gic 0 4 4>, - <0 0 5 &gic 0 5 4>, - <0 0 6 &gic 0 6 4>, - <0 0 7 &gic 0 7 4>, - <0 0 8 &gic 0 8 4>, - <0 0 9 &gic 0 9 4>, - <0 0 10 &gic 0 10 4>, - <0 0 11 &gic 0 11 4>, - <0 0 12 &gic 0 12 4>, - <0 0 13 &gic 0 13 4>, - <0 0 14 &gic 0 14 4>, - <0 0 15 &gic 0 15 4>, - <0 0 16 &gic 0 16 4>, - <0 0 17 &gic 0 17 4>, - <0 0 18 &gic 0 18 4>, - <0 0 19 &gic 0 19 4>, - <0 0 20 &gic 0 20 4>, - <0 0 21 &gic 0 21 4>, - <0 0 22 &gic 0 22 4>, - <0 0 23 &gic 0 23 4>, - <0 0 24 &gic 0 24 4>, - <0 0 25 &gic 0 25 4>, - <0 0 26 &gic 0 26 4>, - <0 0 27 &gic 0 27 4>, - <0 0 28 &gic 0 28 4>, - <0 0 29 &gic 0 29 4>, - <0 0 30 &gic 0 30 4>, - <0 0 31 &gic 0 31 4>, - <0 0 32 &gic 0 32 4>, - <0 0 33 &gic 0 33 4>, - <0 0 34 &gic 0 34 4>, - <0 0 35 &gic 0 35 4>, - <0 0 36 &gic 0 36 4>, - <0 0 37 &gic 0 37 4>, - <0 0 38 &gic 0 38 4>, - <0 0 39 &gic 0 39 4>, - <0 0 40 &gic 0 40 4>, - <0 0 41 &gic 0 41 4>, - <0 0 42 &gic 0 42 4>; - }; -}; - -/include/ "vexpress-v2m.dtsi" diff --git a/trunk/arch/arm/common/it8152.c b/trunk/arch/arm/common/it8152.c index fb1f1cfce60c..d1bcd7b13ebc 100644 --- a/trunk/arch/arm/common/it8152.c +++ b/trunk/arch/arm/common/it8152.c @@ -320,6 +320,13 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) return -EBUSY; } +/* + * If we set up a device for bus mastering, we need to check the latency + * timer as we don't have even crappy BIOSes to set it properly. + * The implementation is from arch/i386/pci/i386.c + */ +unsigned int pcibios_max_latency = 255; + /* ITE bridge requires setting latency timer to avoid early bus access termination by PCI bus master devices */ diff --git a/trunk/arch/arm/common/pl330.c b/trunk/arch/arm/common/pl330.c index ff3ad2244824..d8e44a43047c 100644 --- a/trunk/arch/arm/common/pl330.c +++ b/trunk/arch/arm/common/pl330.c @@ -1502,13 +1502,12 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op) struct pl330_thread *thrd = ch_id; struct pl330_dmac *pl330; unsigned long flags; - int ret = 0, active; + int ret = 0, active = thrd->req_running; if (!thrd || thrd->free || thrd->dmac->state == DYING) return -EINVAL; pl330 = thrd->dmac; - active = thrd->req_running; spin_lock_irqsave(&pl330->lock, flags); diff --git a/trunk/arch/arm/include/asm/assembler.h b/trunk/arch/arm/include/asm/assembler.h index 23371b17b23e..62f8095d46de 100644 --- a/trunk/arch/arm/include/asm/assembler.h +++ b/trunk/arch/arm/include/asm/assembler.h @@ -137,11 +137,6 @@ disable_irq .endm - .macro save_and_disable_irqs_notrace, oldcpsr - mrs \oldcpsr, cpsr - disable_irq_notrace - .endm - /* * Restore interrupt state previously stored in a register. We don't * guarantee that this will preserve the flags. diff --git a/trunk/arch/arm/include/asm/hardware/arm_timer.h b/trunk/arch/arm/include/asm/hardware/arm_timer.h index d6030ff599db..c0f4e7bf22de 100644 --- a/trunk/arch/arm/include/asm/hardware/arm_timer.h +++ b/trunk/arch/arm/include/asm/hardware/arm_timer.h @@ -9,12 +9,7 @@ * * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview * can have 16-bit or 32-bit selectable via a bit in the control register. - * - * Every SP804 contains two identical timers. */ -#define TIMER_1_BASE 0x00 -#define TIMER_2_BASE 0x20 - #define TIMER_LOAD 0x00 /* ACVR rw */ #define TIMER_VALUE 0x04 /* ACVR ro */ #define TIMER_CTRL 0x08 /* ACVR rw */ diff --git a/trunk/arch/arm/include/asm/hardware/pl330.h b/trunk/arch/arm/include/asm/hardware/pl330.h index c1821385abfa..575fa8186ca0 100644 --- a/trunk/arch/arm/include/asm/hardware/pl330.h +++ b/trunk/arch/arm/include/asm/hardware/pl330.h @@ -41,7 +41,7 @@ enum pl330_dstcachectrl { DCCTRL1, /* Bufferable only */ DCCTRL2, /* Cacheable, but do not allocate */ DCCTRL3, /* Cacheable and bufferable, but do not allocate */ - DINVALID1, /* AWCACHE = 0x1000 */ + DINVALID1 = 8, DINVALID2, DCCTRL6, /* Cacheable write-through, allocate on writes only */ DCCTRL7, /* Cacheable write-back, allocate on writes only */ diff --git a/trunk/arch/arm/include/asm/processor.h b/trunk/arch/arm/include/asm/processor.h index cb8d638924fd..ce280b8d613c 100644 --- a/trunk/arch/arm/include/asm/processor.h +++ b/trunk/arch/arm/include/asm/processor.h @@ -22,7 +22,6 @@ #include #include #include -#include #ifdef __KERNEL__ #define STACK_TOP ((current->personality & ADDR_LIMIT_32BIT) ? \ diff --git a/trunk/arch/arm/kernel/ptrace.c b/trunk/arch/arm/kernel/ptrace.c index ede6443c34d9..e33870ff0ac0 100644 --- a/trunk/arch/arm/kernel/ptrace.c +++ b/trunk/arch/arm/kernel/ptrace.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include @@ -905,12 +904,6 @@ long arch_ptrace(struct task_struct *child, long request, return ret; } -#ifdef __ARMEB__ -#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB -#else -#define AUDIT_ARCH_NR AUDIT_ARCH_ARM -#endif - asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) { unsigned long ip; @@ -925,7 +918,7 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno) if (!ip) audit_syscall_exit(regs); else - audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0, + audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3); if (!test_thread_flag(TIF_SYSCALL_TRACE)) diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c index 7a79b24597b2..4285daa077b0 100644 --- a/trunk/arch/arm/kernel/smp_twd.c +++ b/trunk/arch/arm/kernel/smp_twd.c @@ -129,7 +129,7 @@ static struct notifier_block twd_cpufreq_nb = { static int twd_cpufreq_init(void) { - if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) + if (!IS_ERR(twd_clk)) return cpufreq_register_notifier(&twd_cpufreq_nb, CPUFREQ_TRANSITION_NOTIFIER); diff --git a/trunk/arch/arm/mach-at91/at91rm9200_devices.c b/trunk/arch/arm/mach-at91/at91rm9200_devices.c index 99ce5c955e39..640520c04c46 100644 --- a/trunk/arch/arm/mach-at91/at91rm9200_devices.c +++ b/trunk/arch/arm/mach-at91/at91rm9200_devices.c @@ -84,7 +84,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { diff --git a/trunk/arch/arm/mach-at91/at91sam9260_devices.c b/trunk/arch/arm/mach-at91/at91sam9260_devices.c index 40f6aeaea043..df487ce83c5e 100644 --- a/trunk/arch/arm/mach-at91/at91sam9260_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9260_devices.c @@ -85,7 +85,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { @@ -1239,7 +1239,8 @@ void __init at91_add_device_serial(void) {} * CF/IDE * -------------------------------------------------------------------- */ -#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ +#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ + defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) static struct at91_cf_data cf0_data; @@ -1336,8 +1337,10 @@ void __init at91_add_device_cf(struct at91_cf_data *data) if (data->flags & AT91_CF_TRUE_IDE) #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) pdev->name = "pata_at91"; +#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) + pdev->name = "at91_ide"; #else -#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91" +#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" #endif else pdev->name = "at91_cf"; diff --git a/trunk/arch/arm/mach-at91/at91sam9261_devices.c b/trunk/arch/arm/mach-at91/at91sam9261_devices.c index 096da87dc00d..3bd10ce4854e 100644 --- a/trunk/arch/arm/mach-at91/at91sam9261_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9261_devices.c @@ -88,7 +88,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { diff --git a/trunk/arch/arm/mach-at91/at91sam9263_devices.c b/trunk/arch/arm/mach-at91/at91sam9263_devices.c index 53688c46f956..7792de5b83d4 100644 --- a/trunk/arch/arm/mach-at91/at91sam9263_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9263_devices.c @@ -93,7 +93,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {} * USB Device (Gadget) * -------------------------------------------------------------------- */ -#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE) +#ifdef CONFIG_USB_AT91 static struct at91_udc_data udc_data; static struct resource udc_resources[] = { @@ -356,8 +356,8 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} * Compact Flash (PCMCIA or IDE) * -------------------------------------------------------------------- */ -#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ - defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) +#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ + defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) static struct at91_cf_data cf0_data; @@ -451,7 +451,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data) at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ - pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "pata_at91" : "at91_cf"; + pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; platform_device_register(pdev); } #else diff --git a/trunk/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/trunk/arch/arm/mach-at91/include/mach/at91sam9_smc.h index 175e1fdd9fe8..eb18a70fa647 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91sam9_smc.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91sam9_smc.h @@ -18,35 +18,6 @@ #include -#ifndef __ASSEMBLY__ -struct sam9_smc_config { - /* Setup register */ - u8 ncs_read_setup; - u8 nrd_setup; - u8 ncs_write_setup; - u8 nwe_setup; - - /* Pulse register */ - u8 ncs_read_pulse; - u8 nrd_pulse; - u8 ncs_write_pulse; - u8 nwe_pulse; - - /* Cycle register */ - u16 read_cycle; - u16 write_cycle; - - /* Mode register */ - u32 mode; - u8 tdf_cycles:4; -}; - -extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); -extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); -#endif - #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ #define AT91_SMC_NWESETUP_(x) ((x) << 0) diff --git a/trunk/arch/arm/mach-at91/sam9_smc.c b/trunk/arch/arm/mach-at91/sam9_smc.c index 99a0a1d2b7dc..8294783b679d 100644 --- a/trunk/arch/arm/mach-at91/sam9_smc.c +++ b/trunk/arch/arm/mach-at91/sam9_smc.c @@ -2,7 +2,6 @@ * linux/arch/arm/mach-at91/sam9_smc.c * * Copyright (C) 2008 Andrew Victor - * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -23,22 +22,7 @@ static void __iomem *smc_base_addr[2]; -static void sam9_smc_cs_write_mode(void __iomem *base, - struct sam9_smc_config *config) -{ - __raw_writel(config->mode - | AT91_SMC_TDF_(config->tdf_cycles), - base + AT91_SMC_MODE); -} - -void sam9_smc_write_mode(int id, int cs, - struct sam9_smc_config *config) -{ - sam9_smc_cs_write_mode(AT91_SMC_CS(id, cs), config); -} - -static void sam9_smc_cs_configure(void __iomem *base, - struct sam9_smc_config *config) +static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config) { /* Setup register */ @@ -61,66 +45,16 @@ static void sam9_smc_cs_configure(void __iomem *base, base + AT91_SMC_CYCLE); /* Mode register */ - sam9_smc_cs_write_mode(base, config); + __raw_writel(config->mode + | AT91_SMC_TDF_(config->tdf_cycles), + base + AT91_SMC_MODE); } -void sam9_smc_configure(int id, int cs, - struct sam9_smc_config *config) +void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config) { sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config); } -static void sam9_smc_cs_read_mode(void __iomem *base, - struct sam9_smc_config *config) -{ - u32 val = __raw_readl(base + AT91_SMC_MODE); - - config->mode = (val & ~AT91_SMC_NWECYCLE); - config->tdf_cycles = (val & AT91_SMC_NWECYCLE) >> 16 ; -} - -void sam9_smc_read_mode(int id, int cs, - struct sam9_smc_config *config) -{ - sam9_smc_cs_read_mode(AT91_SMC_CS(id, cs), config); -} - -static void sam9_smc_cs_read(void __iomem *base, - struct sam9_smc_config *config) -{ - u32 val; - - /* Setup register */ - val = __raw_readl(base + AT91_SMC_SETUP); - - config->nwe_setup = val & AT91_SMC_NWESETUP; - config->ncs_write_setup = (val & AT91_SMC_NCS_WRSETUP) >> 8; - config->nrd_setup = (val & AT91_SMC_NRDSETUP) >> 16; - config->ncs_read_setup = (val & AT91_SMC_NCS_RDSETUP) >> 24; - - /* Pulse register */ - val = __raw_readl(base + AT91_SMC_PULSE); - - config->nwe_setup = val & AT91_SMC_NWEPULSE; - config->ncs_write_pulse = (val & AT91_SMC_NCS_WRPULSE) >> 8; - config->nrd_pulse = (val & AT91_SMC_NRDPULSE) >> 16; - config->ncs_read_pulse = (val & AT91_SMC_NCS_RDPULSE) >> 24; - - /* Cycle register */ - val = __raw_readl(base + AT91_SMC_CYCLE); - - config->write_cycle = val & AT91_SMC_NWECYCLE; - config->read_cycle = (val & AT91_SMC_NRDCYCLE) >> 16; - - /* Mode register */ - sam9_smc_cs_read_mode(base, config); -} - -void sam9_smc_read(int id, int cs, struct sam9_smc_config *config) -{ - sam9_smc_cs_read(AT91_SMC_CS(id, cs), config); -} - void __init at91sam9_ioremap_smc(int id, u32 addr) { if (id > 1) { diff --git a/trunk/arch/arm/mach-at91/sam9_smc.h b/trunk/arch/arm/mach-at91/sam9_smc.h index 3e52dcd4a59f..039c5ce17aec 100644 --- a/trunk/arch/arm/mach-at91/sam9_smc.h +++ b/trunk/arch/arm/mach-at91/sam9_smc.h @@ -8,4 +8,27 @@ * published by the Free Software Foundation. */ +struct sam9_smc_config { + /* Setup register */ + u8 ncs_read_setup; + u8 nrd_setup; + u8 ncs_write_setup; + u8 nwe_setup; + + /* Pulse register */ + u8 ncs_read_pulse; + u8 nrd_pulse; + u8 ncs_write_pulse; + u8 nwe_pulse; + + /* Cycle register */ + u16 read_cycle; + u16 write_cycle; + + /* Mode register */ + u32 mode; + u8 tdf_cycles:4; +}; + +extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config); extern void __init at91sam9_ioremap_smc(int id, u32 addr); diff --git a/trunk/arch/arm/mach-dove/common.c b/trunk/arch/arm/mach-dove/common.c index bda7aca04ca0..dd1429ae6405 100644 --- a/trunk/arch/arm/mach-dove/common.c +++ b/trunk/arch/arm/mach-dove/common.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include "common.h" @@ -72,7 +71,7 @@ void __init dove_map_io(void) ****************************************************************************/ void __init dove_ehci0_init(void) { - orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA); + orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0); } /***************************************************************************** diff --git a/trunk/arch/arm/mach-ep93xx/vision_ep9307.c b/trunk/arch/arm/mach-ep93xx/vision_ep9307.c index d5fb44f16d31..03dd4012043e 100644 --- a/trunk/arch/arm/mach-ep93xx/vision_ep9307.c +++ b/trunk/arch/arm/mach-ep93xx/vision_ep9307.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include @@ -154,6 +153,7 @@ static struct i2c_board_info vision_i2c_info[] __initdata = { }, { I2C_BOARD_INFO("pca9539", 0x74), .platform_data = &pca953x_74_gpio_data, + .irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)), }, { I2C_BOARD_INFO("pca9539", 0x75), .platform_data = &pca953x_75_gpio_data, @@ -348,8 +348,6 @@ static void __init vision_init_machine(void) "pca9539:74")) pr_warn("cannot request interrupt gpio for pca9539:74\n"); - vision_i2c_info[1].irq = gpio_to_irq(EP93XX_GPIO_LINE_F(7)); - ep93xx_register_i2c(&vision_i2c_gpio_data, vision_i2c_info, ARRAY_SIZE(vision_i2c_info)); ep93xx_register_spi(&vision_spi_master, vision_spi_board_info, diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4210.c b/trunk/arch/arm/mach-exynos/clock-exynos4210.c index 13312ccb2d93..a5823a7f249e 100644 --- a/trunk/arch/arm/mach-exynos/clock-exynos4210.c +++ b/trunk/arch/arm/mach-exynos/clock-exynos4210.c @@ -32,7 +32,6 @@ #include "common.h" -#ifdef CONFIG_PM_SLEEP static struct sleep_save exynos4210_clock_save[] = { SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(S5P_CLKSRC_LCD1), @@ -43,7 +42,6 @@ static struct sleep_save exynos4210_clock_save[] = { SAVE_ITEM(S5P_CLKGATE_IP_LCD1), SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), }; -#endif static struct clksrc_clk *sysclks[] = { /* nothing here yet */ diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4212.c b/trunk/arch/arm/mach-exynos/clock-exynos4212.c index 48af28566fa1..26a668b0d101 100644 --- a/trunk/arch/arm/mach-exynos/clock-exynos4212.c +++ b/trunk/arch/arm/mach-exynos/clock-exynos4212.c @@ -32,14 +32,12 @@ #include "common.h" -#ifdef CONFIG_PM_SLEEP static struct sleep_save exynos4212_clock_save[] = { SAVE_ITEM(S5P_CLKSRC_IMAGE), SAVE_ITEM(S5P_CLKDIV_IMAGE), SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), }; -#endif static struct clk *clk_src_mpll_user_list[] = { [0] = &clk_fin_mpll, diff --git a/trunk/arch/arm/mach-exynos/clock.c b/trunk/arch/arm/mach-exynos/clock.c index 187287aa57ab..5a8c42e90005 100644 --- a/trunk/arch/arm/mach-exynos/clock.c +++ b/trunk/arch/arm/mach-exynos/clock.c @@ -30,7 +30,6 @@ #include "common.h" -#ifdef CONFIG_PM_SLEEP static struct sleep_save exynos4_clock_save[] = { SAVE_ITEM(S5P_CLKDIV_LEFTBUS), SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), @@ -94,7 +93,6 @@ static struct sleep_save exynos4_clock_save[] = { SAVE_ITEM(S5P_CLKGATE_SCLKCPU), SAVE_ITEM(S5P_CLKGATE_IP_CPU), }; -#endif struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", diff --git a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c index e6b02fdf1b09..85fa02767d67 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -15,13 +15,11 @@ #include #include -#include #include #include #include - -#include "common.h" +#include /* * The following lookup table is used to override device names when devices @@ -62,7 +60,7 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { static void __init exynos4210_dt_map_io(void) { - exynos_init_io(NULL, 0); + s5p_init_io(NULL, 0, S5P_VA_CHIPID); s3c24xx_init_clocks(24000000); } @@ -81,9 +79,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") /* Maintainer: Thomas Abraham */ .init_irq = exynos4_init_irq, .map_io = exynos4210_dt_map_io, - .handle_irq = gic_handle_irq, .init_machine = exynos4210_dt_machine_init, .timer = &exynos4_timer, .dt_compat = exynos4210_dt_compat, - .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c index 435261f83f46..b895ec031105 100644 --- a/trunk/arch/arm/mach-exynos/mach-nuri.c +++ b/trunk/arch/arm/mach-exynos/mach-nuri.c @@ -220,14 +220,14 @@ static struct s3c_fb_pd_win nuri_fb_win0 = { .lower_margin = 1, .hsync_len = 48, .vsync_len = 3, - .xres = 1024, - .yres = 600, + .xres = 1280, + .yres = 800, .refresh = 60, }, .max_bpp = 24, .default_bpp = 16, - .virtual_x = 1024, - .virtual_y = 2 * 600, + .virtual_x = 1280, + .virtual_y = 800, }; static struct s3c_fb_platdata nuri_fb_pdata __initdata = { diff --git a/trunk/arch/arm/mach-exynos/mach-universal_c210.c b/trunk/arch/arm/mach-exynos/mach-universal_c210.c index 0fc65ffde8ff..37ac93e8d6d9 100644 --- a/trunk/arch/arm/mach-exynos/mach-universal_c210.c +++ b/trunk/arch/arm/mach-exynos/mach-universal_c210.c @@ -910,7 +910,7 @@ static struct s5p_fimc_isp_info universal_camera_sensors[] = { .bus_type = FIMC_MIPI_CSI2, .board_info = &m5mols_board_info, .i2c_bus_num = 0, - .clk_frequency = 24000000UL, + .clk_frequency = 21600000UL, .csi_data_align = 32, }, }; diff --git a/trunk/arch/arm/mach-exynos/pm.c b/trunk/arch/arm/mach-exynos/pm.c index e19013051772..a4f61a43c7ba 100644 --- a/trunk/arch/arm/mach-exynos/pm.c +++ b/trunk/arch/arm/mach-exynos/pm.c @@ -206,7 +206,7 @@ static void exynos4_pm_prepare(void) } -static int exynos4_pm_add(struct device *dev, struct subsys_interface *sif) +static int exynos4_pm_add(struct device *dev) { pm_cpu_prep = exynos4_pm_prepare; pm_cpu_sleep = exynos4_cpu_suspend; @@ -384,9 +384,7 @@ static void exynos4_pm_resume(void) exynos4_restore_pll(); -#ifdef CONFIG_SMP scu_enable(S5P_VA_SCU); -#endif #ifdef CONFIG_CACHE_L2X0 s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save)); diff --git a/trunk/arch/arm/mach-imx/Makefile.boot b/trunk/arch/arm/mach-imx/Makefile.boot index 3851d8a27875..6dfdbcc83afd 100644 --- a/trunk/arch/arm/mach-imx/Makefile.boot +++ b/trunk/arch/arm/mach-imx/Makefile.boot @@ -38,8 +38,5 @@ zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000 -dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb -dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \ - imx53-qsb.dtb imx53-smd.dtb dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \ imx6q-sabrelite.dtb diff --git a/trunk/arch/arm/mach-imx/imx51-dt.c b/trunk/arch/arm/mach-imx/imx51-dt.c index 5cca573964f0..1e03ef42faa0 100644 --- a/trunk/arch/arm/mach-imx/imx51-dt.c +++ b/trunk/arch/arm/mach-imx/imx51-dt.c @@ -104,7 +104,6 @@ static struct sys_timer imx51_timer = { static const char *imx51_dt_board_compat[] __initdata = { "fsl,imx51-babbage", - "fsl,imx51", NULL }; diff --git a/trunk/arch/arm/mach-imx/imx53-dt.c b/trunk/arch/arm/mach-imx/imx53-dt.c index 4172279b3900..fd5be0f20fbb 100644 --- a/trunk/arch/arm/mach-imx/imx53-dt.c +++ b/trunk/arch/arm/mach-imx/imx53-dt.c @@ -114,7 +114,6 @@ static const char *imx53_dt_board_compat[] __initdata = { "fsl,imx53-evk", "fsl,imx53-qsb", "fsl,imx53-smd", - "fsl,imx53", NULL }; diff --git a/trunk/arch/arm/mach-imx/mach-imx6q.c b/trunk/arch/arm/mach-imx/mach-imx6q.c index 379b1a9cd22b..6075d4d62dd6 100644 --- a/trunk/arch/arm/mach-imx/mach-imx6q.c +++ b/trunk/arch/arm/mach-imx/mach-imx6q.c @@ -129,7 +129,6 @@ static struct sys_timer imx6q_timer = { static const char *imx6q_dt_compat[] __initdata = { "fsl,imx6q-arm2", "fsl,imx6q-sabrelite", - "fsl,imx6q", NULL, }; diff --git a/trunk/arch/arm/mach-kirkwood/common.c b/trunk/arch/arm/mach-kirkwood/common.c index 77d4852e19f2..cc15426787b1 100644 --- a/trunk/arch/arm/mach-kirkwood/common.c +++ b/trunk/arch/arm/mach-kirkwood/common.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -74,7 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED; void __init kirkwood_ehci_init(void) { kirkwood_clk_ctrl |= CGC_USB0; - orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA); + orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB); } diff --git a/trunk/arch/arm/mach-kirkwood/mpp.h b/trunk/arch/arm/mach-kirkwood/mpp.h index d5a0d1da2e0e..e8fda45c0736 100644 --- a/trunk/arch/arm/mach-kirkwood/mpp.h +++ b/trunk/arch/arm/mach-kirkwood/mpp.h @@ -31,314 +31,314 @@ #define MPP_F6282_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 0, 1 ) #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1, 1 ) #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1, 1 ) #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1, 1 ) #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1, 1 ) #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1, 1 ) #define MPP4_LCD_VGA_HSYNC MPP( 4, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1, 0 ) #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP5_LCD_VGA_VSYNC MPP( 5, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1, 0 ) #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP7_LCD_PWM MPP( 7, 0xb, 0, 1, 0, 0, 0, 0, 1 ) #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW0_SDA MPP( 8, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP8_TW0_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1, 1 ) +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1, 1 ) #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW0_SCK MPP( 9, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP9_TW0_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1, 1 ) #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 0, 1, 1, 1, 1, 0 ) +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1, 0 ) #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 0, 0, 1, 1, 1, 1, 0 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1, 0 ) +#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1, 0 ) +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1, 1 ) #define MPP12_GPIO MPP( 12, 0x0, 1, 1, 0, 0, 0, 1, 0 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP12_TW1_SDA MPP( 12, 0xd, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP12_AU_SPDIF0 MPP( 12, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP12_SPI_MOSI MPP( 12, 0xb, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP12_TW1_SDA MPP( 12, 0xd, 1, 0, 0, 0, 0, 0, 1 ) #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP13_LCDPWM MPP( 13, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP13_AU_SPDIFRMCLK MPP( 13, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP13_LCDPWM MPP( 13, 0xb, 0, 1, 0, 0, 0, 0, 1 ) #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP14_AU_SPDIFI MPP( 14, 0xa, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP14_AU_I2SDI MPP( 14, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP14_AU_SPDIFI MPP( 14, 0xa, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP14_AU_I2SDI MPP( 14, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1, 1 ) #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP15_SPI_CSn MPP( 15, 0xb, 0, 1, 0, 0, 0, 0, 1 ) #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1, 1 ) +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP16_LCD_EXT_REF_CLK MPP( 16, 0xb, 1, 0, 0, 0, 0, 0, 1 ) +#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1, 1 ) #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP17_TW1_SCK MPP( 17, 0xd, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1, 1 ) +#define MPP17_SATA1_ACTn MPP( 17, 0xa, 0, 1, 0, 0, 0, 0, 1 ) +#define MPP17_TW1_SCK MPP( 17, 0xd, 1, 1, 0, 0, 0, 0, 1 ) #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 0, 0, 1, 1, 1, 1, 1 ) -#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1, 1 ) +#define MPP18_PEX0_CLKREQ MPP( 18, 0x2, 0, 1, 0, 0, 0, 0, 1 ) #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1, 1 ) #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP20_GE1_TXD0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP20_AU_SPDIFI MPP( 20, 0x4, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP20_AU_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1, 1 ) +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1, 1 ) #define MPP20_LCD_D0 MPP( 20, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP21_GE1_TXD1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP21_AU_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP21_LCD_D1 MPP( 21, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP22_GE1_TXD2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP22_AU_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1, 1 ) #define MPP22_LCD_D2 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1, 1 ) #define MPP23_GE1_TXD3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP23_AU_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1, 1 ) +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP23_LCD_D3 MPP( 23, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP24_TDM_SPI_CS0 MPP( 24, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP24_GE1_RXD0 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP24_AU_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1, 1 ) #define MPP24_LCD_D4 MPP( 24, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP25_GE1_RXD1 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP25_AU_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1, 1 ) #define MPP25_LCD_D5 MPP( 25, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1, 1 ) #define MPP26_GE1_RXD2 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP26_AU_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1, 1 ) #define MPP26_LCD_D6 MPP( 26, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP27_GE1_RXD3 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP27_AU_I2SDI MPP( 27, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP27_AU_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1, 1 ) #define MPP27_LCD_D7 MPP( 27, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1, 1 ) #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP28_GE1_COL MPP( 28, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP28_AU_EXTCLK MPP( 28, 0x4, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP28_AU_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1, 1 ) #define MPP28_LCD_D8 MPP( 28, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1, 1 ) #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1, 1 ) #define MPP29_GE1_TCLK MPP( 29, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP29_LCD_D9 MPP( 29, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1, 1 ) #define MPP30_GE1_RXCTL MPP( 30, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP30_LCD_D10 MPP( 30, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1, 1 ) #define MPP31_GE1_RXCLK MPP( 31, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP31_LCD_D11 MPP( 31, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 0, 0, 0, 0, 1, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1, 1 ) +#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1, 1 ) #define MPP32_GE1_TCLKOUT MPP( 32, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP32_LCD_D12 MPP( 32, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP33_GPO MPP( 33, 0x0, 0, 1, 0, 1, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP33_GE1_TXCTL MPP( 33, 0x3, 0, 0, 0, 1, 1, 1, 1 ) #define MPP33_LCD_D13 MPP( 33, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP34_GE1_TXEN MPP( 34, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP34_SATA1_ACTn MPP( 34, 0x5, 0, 1, 0, 0, 0, 1, 1 ) #define MPP34_LCD_D14 MPP( 34, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 0, 0, 0, 1, 1, 1 ) +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1, 1 ) #define MPP35_GE1_RXERR MPP( 35, 0x3, 0, 0, 0, 1, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 0, 0, 1, 1, 1, 1 ) +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1, 1 ) #define MPP35_LCD_D15 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 0, 0, 1, 1, 1, 1, 1 ) +#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1, 1 ) #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP36_AU_SPDIFI MPP( 36, 0x4, 0, 0, 1, 0, 0, 1, 1 ) -#define MPP36_TW1_SDA MPP( 36, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP36_AU_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1, 1 ) +#define MPP36_TW1_SDA MPP( 36, 0xb, 1, 1, 0, 0, 0, 0, 1 ) #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 0, 1, 0, 0, 1, 1 ) -#define MPP37_TW1_SCK MPP( 37, 0xb, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP37_AU_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1, 1 ) +#define MPP37_TW1_SCK MPP( 37, 0xb, 1, 1, 0, 0, 0, 0, 1 ) #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP38_AU_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1, 1 ) #define MPP38_LCD_D18 MPP( 38, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP39_AU_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1, 1 ) #define MPP39_LCD_D19 MPP( 39, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP40_AU_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1, 1 ) #define MPP40_LCD_D20 MPP( 40, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1, 1 ) +#define MPP41_AU_I2SLRCLK MPP( 41, 0x4, 0, 1, 1, 0, 0, 1, 1 ) #define MPP41_LCD_D21 MPP( 41, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP42_AU_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1, 1 ) #define MPP42_LCD_D22 MPP( 42, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1, 1 ) #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP43_AU_I2SDI MPP( 43, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP43_AU_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1, 1 ) #define MPP43_LCD_D23 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1, 1 ) #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP44_AU_EXTCLK MPP( 44, 0x4, 0, 0, 1, 0, 0, 1, 1 ) +#define MPP44_AU_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1, 1 ) #define MPP44_LCD_CLK MPP( 44, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1, 1 ) #define MPP245_LCD_E MPP( 45, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1, 1 ) #define MPP46_LCD_HSYNC MPP( 46, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1, 1 ) #define MPP47_LCD_VSYNC MPP( 47, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 0, 0, 0, 0, 1, 1 ) +#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1, 1 ) #define MPP48_LCD_D16 MPP( 22, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1, 0 ) #define MPP49_GPO MPP( 49, 0x0, 0, 1, 0, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 0, 0, 0, 0, 0, 1, 0 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 0, 0, 0, 0, 1, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 0, 0, 0, 0, 0, 1, 0 ) -#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 0, 0, 0, 0, 0, 1 ) +#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1, 0 ) +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1, 1 ) +#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1, 0 ) +#define MPP49_PEX0_CLKREQ MPP( 49, 0xa, 0, 1, 0, 0, 0, 0, 1 ) #define MPP49_LCD_D17 MPP( 49, 0xb, 0, 0, 0, 0, 0, 0, 1 ) #define MPP_MAX 49 diff --git a/trunk/arch/arm/mach-mv78xx0/common.c b/trunk/arch/arm/mach-mv78xx0/common.c index a5dcf766a3f9..0cdd41004ad0 100644 --- a/trunk/arch/arm/mach-mv78xx0/common.c +++ b/trunk/arch/arm/mach-mv78xx0/common.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -170,7 +169,7 @@ void __init mv78xx0_map_io(void) ****************************************************************************/ void __init mv78xx0_ehci0_init(void) { - orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0, EHCI_PHY_NA); + orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0); } diff --git a/trunk/arch/arm/mach-mv78xx0/mpp.h b/trunk/arch/arm/mach-mv78xx0/mpp.h index 3752302ae2ee..b61b50927123 100644 --- a/trunk/arch/arm/mach-mv78xx0/mpp.h +++ b/trunk/arch/arm/mach-mv78xx0/mpp.h @@ -24,296 +24,296 @@ #define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1) #define MPP0_GPIO MPP(0, 0x0, 1, 1, 1) -#define MPP0_GE0_COL MPP(0, 0x1, 0, 0, 1) -#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 0, 1) +#define MPP0_GE0_COL MPP(0, 0x1, 1, 0, 1) +#define MPP0_GE1_TXCLK MPP(0, 0x2, 0, 1, 1) #define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1) #define MPP1_GPIO MPP(1, 0x0, 1, 1, 1) -#define MPP1_GE0_RXERR MPP(1, 0x1, 0, 0, 1) -#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 0, 1) +#define MPP1_GE0_RXERR MPP(1, 0x1, 1, 0, 1) +#define MPP1_GE1_TXCTL MPP(1, 0x2, 0, 1, 1) #define MPP1_UNUSED MPP(1, 0x3, 0, 0, 1) #define MPP2_GPIO MPP(2, 0x0, 1, 1, 1) -#define MPP2_GE0_CRS MPP(2, 0x1, 0, 0, 1) -#define MPP2_GE1_RXCTL MPP(2, 0x2, 0, 0, 1) +#define MPP2_GE0_CRS MPP(2, 0x1, 1, 0, 1) +#define MPP2_GE1_RXCTL MPP(2, 0x2, 1, 0, 1) #define MPP2_UNUSED MPP(2, 0x3, 0, 0, 1) #define MPP3_GPIO MPP(3, 0x0, 1, 1, 1) -#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 0, 1) -#define MPP3_GE1_RXCLK MPP(3, 0x2, 0, 0, 1) +#define MPP3_GE0_TXERR MPP(3, 0x1, 0, 1, 1) +#define MPP3_GE1_RXCLK MPP(3, 0x2, 1, 0, 1) #define MPP3_UNUSED MPP(3, 0x3, 0, 0, 1) #define MPP4_GPIO MPP(4, 0x0, 1, 1, 1) -#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 0, 1) -#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 0, 1) +#define MPP4_GE0_TXD4 MPP(4, 0x1, 0, 1, 1) +#define MPP4_GE1_TXD0 MPP(4, 0x2, 0, 1, 1) #define MPP4_UNUSED MPP(4, 0x3, 0, 0, 1) #define MPP5_GPIO MPP(5, 0x0, 1, 1, 1) -#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 0, 1) -#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 0, 1) +#define MPP5_GE0_TXD5 MPP(5, 0x1, 0, 1, 1) +#define MPP5_GE1_TXD1 MPP(5, 0x2, 0, 1, 1) #define MPP5_UNUSED MPP(5, 0x3, 0, 0, 1) #define MPP6_GPIO MPP(6, 0x0, 1, 1, 1) -#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 0, 1) -#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 0, 1) +#define MPP6_GE0_TXD6 MPP(6, 0x1, 0, 1, 1) +#define MPP6_GE1_TXD2 MPP(6, 0x2, 0, 1, 1) #define MPP6_UNUSED MPP(6, 0x3, 0, 0, 1) #define MPP7_GPIO MPP(7, 0x0, 1, 1, 1) -#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 0, 1) -#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 0, 1) +#define MPP7_GE0_TXD7 MPP(7, 0x1, 0, 1, 1) +#define MPP7_GE1_TXD3 MPP(7, 0x2, 0, 1, 1) #define MPP7_UNUSED MPP(7, 0x3, 0, 0, 1) #define MPP8_GPIO MPP(8, 0x0, 1, 1, 1) -#define MPP8_GE0_RXD4 MPP(8, 0x1, 0, 0, 1) -#define MPP8_GE1_RXD0 MPP(8, 0x2, 0, 0, 1) +#define MPP8_GE0_RXD4 MPP(8, 0x1, 1, 0, 1) +#define MPP8_GE1_RXD0 MPP(8, 0x2, 1, 0, 1) #define MPP8_UNUSED MPP(8, 0x3, 0, 0, 1) #define MPP9_GPIO MPP(9, 0x0, 1, 1, 1) -#define MPP9_GE0_RXD5 MPP(9, 0x1, 0, 0, 1) -#define MPP9_GE1_RXD1 MPP(9, 0x2, 0, 0, 1) +#define MPP9_GE0_RXD5 MPP(9, 0x1, 1, 0, 1) +#define MPP9_GE1_RXD1 MPP(9, 0x2, 1, 0, 1) #define MPP9_UNUSED MPP(9, 0x3, 0, 0, 1) #define MPP10_GPIO MPP(10, 0x0, 1, 1, 1) -#define MPP10_GE0_RXD6 MPP(10, 0x1, 0, 0, 1) -#define MPP10_GE1_RXD2 MPP(10, 0x2, 0, 0, 1) +#define MPP10_GE0_RXD6 MPP(10, 0x1, 1, 0, 1) +#define MPP10_GE1_RXD2 MPP(10, 0x2, 1, 0, 1) #define MPP10_UNUSED MPP(10, 0x3, 0, 0, 1) #define MPP11_GPIO MPP(11, 0x0, 1, 1, 1) -#define MPP11_GE0_RXD7 MPP(11, 0x1, 0, 0, 1) -#define MPP11_GE1_RXD3 MPP(11, 0x2, 0, 0, 1) +#define MPP11_GE0_RXD7 MPP(11, 0x1, 1, 0, 1) +#define MPP11_GE1_RXD3 MPP(11, 0x2, 1, 0, 1) #define MPP11_UNUSED MPP(11, 0x3, 0, 0, 1) #define MPP12_GPIO MPP(12, 0x0, 1, 1, 1) -#define MPP12_M_BB MPP(12, 0x3, 0, 0, 1) -#define MPP12_UA0_CTSn MPP(12, 0x4, 0, 0, 1) -#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 0, 1) -#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 0, 1) +#define MPP12_M_BB MPP(12, 0x3, 1, 0, 1) +#define MPP12_UA0_CTSn MPP(12, 0x4, 1, 0, 1) +#define MPP12_NAND_FLASH_REn0 MPP(12, 0x5, 0, 1, 1) +#define MPP12_TDM0_SCSn MPP(12, 0X6, 0, 1, 1) #define MPP12_UNUSED MPP(12, 0x1, 0, 0, 1) #define MPP13_GPIO MPP(13, 0x0, 1, 1, 1) -#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 0, 1) -#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 0, 1) -#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 0, 1) -#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 0, 1) +#define MPP13_SYSRST_OUTn MPP(13, 0x3, 0, 1, 1) +#define MPP13_UA0_RTSn MPP(13, 0x4, 0, 1, 1) +#define MPP13_NAN_FLASH_WEn0 MPP(13, 0x5, 0, 1, 1) +#define MPP13_TDM_SCLK MPP(13, 0x6, 0, 1, 1) #define MPP13_UNUSED MPP(13, 0x1, 0, 0, 1) #define MPP14_GPIO MPP(14, 0x0, 1, 1, 1) -#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 0, 1) -#define MPP14_UA1_CTSn MPP(14, 0x4, 0, 0, 1) -#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 0, 1) -#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 0, 1) +#define MPP14_SATA1_ACTn MPP(14, 0x3, 0, 1, 1) +#define MPP14_UA1_CTSn MPP(14, 0x4, 1, 0, 1) +#define MPP14_NAND_FLASH_REn1 MPP(14, 0x5, 0, 1, 1) +#define MPP14_TDM_SMOSI MPP(14, 0x6, 0, 1, 1) #define MPP14_UNUSED MPP(14, 0x1, 0, 0, 1) #define MPP15_GPIO MPP(15, 0x0, 1, 1, 1) -#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 0, 1) -#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 0, 1) -#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 0, 1) -#define MPP15_TDM_SMISO MPP(15, 0x6, 0, 0, 1) +#define MPP15_SATA0_ACTn MPP(15, 0x3, 0, 1, 1) +#define MPP15_UA1_RTSn MPP(15, 0x4, 0, 1, 1) +#define MPP15_NAND_FLASH_WEn1 MPP(15, 0x5, 0, 1, 1) +#define MPP15_TDM_SMISO MPP(15, 0x6, 1, 0, 1) #define MPP15_UNUSED MPP(15, 0x1, 0, 0, 1) #define MPP16_GPIO MPP(16, 0x0, 1, 1, 1) -#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 0, 1) -#define MPP16_UA2_TXD MPP(16, 0x4, 0, 0, 1) -#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 0, 1) -#define MPP16_TDM_INTn MPP(16, 0x6, 0, 0, 1) +#define MPP16_SATA1_PRESENTn MPP(16, 0x3, 0, 1, 1) +#define MPP16_UA2_TXD MPP(16, 0x4, 0, 1, 1) +#define MPP16_NAND_FLASH_REn3 MPP(16, 0x5, 0, 1, 1) +#define MPP16_TDM_INTn MPP(16, 0x6, 1, 0, 1) #define MPP16_UNUSED MPP(16, 0x1, 0, 0, 1) #define MPP17_GPIO MPP(17, 0x0, 1, 1, 1) -#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 0, 1) -#define MPP17_UA2_RXD MPP(17, 0x4, 0, 0, 1) -#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 0, 1) -#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 0, 1) +#define MPP17_SATA0_PRESENTn MPP(17, 0x3, 0, 1, 1) +#define MPP17_UA2_RXD MPP(17, 0x4, 1, 0, 1) +#define MPP17_NAND_FLASH_WEn3 MPP(17, 0x5, 0, 1, 1) +#define MPP17_TDM_RSTn MPP(17, 0x6, 0, 1, 1) #define MPP17_UNUSED MPP(17, 0x1, 0, 0, 1) #define MPP18_GPIO MPP(18, 0x0, 1, 1, 1) -#define MPP18_UA0_CTSn MPP(18, 0x4, 0, 0, 1) -#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 0, 1) +#define MPP18_UA0_CTSn MPP(18, 0x4, 1, 0, 1) +#define MPP18_BOOT_FLASH_REn MPP(18, 0x5, 0, 1, 1) #define MPP18_UNUSED MPP(18, 0x1, 0, 0, 1) #define MPP19_GPIO MPP(19, 0x0, 1, 1, 1) -#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 0, 1) -#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 0, 1) +#define MPP19_UA0_CTSn MPP(19, 0x4, 0, 1, 1) +#define MPP19_BOOT_FLASH_WEn MPP(19, 0x5, 0, 1, 1) #define MPP19_UNUSED MPP(19, 0x1, 0, 0, 1) #define MPP20_GPIO MPP(20, 0x0, 1, 1, 1) -#define MPP20_UA1_CTSs MPP(20, 0x4, 0, 0, 1) -#define MPP20_TDM_PCLK MPP(20, 0x6, 0, 0, 0) +#define MPP20_UA1_CTSs MPP(20, 0x4, 1, 0, 1) +#define MPP20_TDM_PCLK MPP(20, 0x6, 1, 1, 0) #define MPP20_UNUSED MPP(20, 0x1, 0, 0, 1) #define MPP21_GPIO MPP(21, 0x0, 1, 1, 1) -#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 0, 1) -#define MPP21_TDM_FSYNC MPP(21, 0x6, 0, 0, 0) +#define MPP21_UA1_CTSs MPP(21, 0x4, 0, 1, 1) +#define MPP21_TDM_FSYNC MPP(21, 0x6, 1, 1, 0) #define MPP21_UNUSED MPP(21, 0x1, 0, 0, 1) #define MPP22_GPIO MPP(22, 0x0, 1, 1, 1) -#define MPP22_UA3_TDX MPP(22, 0x4, 0, 0, 1) -#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 0, 1) -#define MPP22_TDM_DRX MPP(22, 0x6, 0, 0, 1) +#define MPP22_UA3_TDX MPP(22, 0x4, 0, 1, 1) +#define MPP22_NAND_FLASH_REn2 MPP(22, 0x5, 0, 1, 1) +#define MPP22_TDM_DRX MPP(22, 0x6, 1, 0, 1) #define MPP22_UNUSED MPP(22, 0x1, 0, 0, 1) #define MPP23_GPIO MPP(23, 0x0, 1, 1, 1) -#define MPP23_UA3_RDX MPP(23, 0x4, 0, 0, 1) -#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 0, 1) -#define MPP23_TDM_DTX MPP(23, 0x6, 0, 0, 1) +#define MPP23_UA3_RDX MPP(23, 0x4, 1, 0, 1) +#define MPP23_NAND_FLASH_WEn2 MPP(23, 0x5, 0, 1, 1) +#define MPP23_TDM_DTX MPP(23, 0x6, 0, 1, 1) #define MPP23_UNUSED MPP(23, 0x1, 0, 0, 1) #define MPP24_GPIO MPP(24, 0x0, 1, 1, 1) -#define MPP24_UA2_TXD MPP(24, 0x4, 0, 0, 1) -#define MPP24_TDM_INTn MPP(24, 0x6, 0, 0, 1) +#define MPP24_UA2_TXD MPP(24, 0x4, 0, 1, 1) +#define MPP24_TDM_INTn MPP(24, 0x6, 1, 0, 1) #define MPP24_UNUSED MPP(24, 0x1, 0, 0, 1) #define MPP25_GPIO MPP(25, 0x0, 1, 1, 1) -#define MPP25_UA2_RXD MPP(25, 0x4, 0, 0, 1) -#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 0, 1) +#define MPP25_UA2_RXD MPP(25, 0x4, 1, 0, 1) +#define MPP25_TDM_RSTn MPP(25, 0x6, 0, 1, 1) #define MPP25_UNUSED MPP(25, 0x1, 0, 0, 1) #define MPP26_GPIO MPP(26, 0x0, 1, 1, 1) -#define MPP26_UA2_CTSn MPP(26, 0x4, 0, 0, 1) -#define MPP26_TDM_PCLK MPP(26, 0x6, 0, 0, 1) +#define MPP26_UA2_CTSn MPP(26, 0x4, 1, 0, 1) +#define MPP26_TDM_PCLK MPP(26, 0x6, 1, 1, 1) #define MPP26_UNUSED MPP(26, 0x1, 0, 0, 1) #define MPP27_GPIO MPP(27, 0x0, 1, 1, 1) -#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 0, 1) -#define MPP27_TDM_FSYNC MPP(27, 0x6, 0, 0, 1) +#define MPP27_UA2_RTSn MPP(27, 0x4, 0, 1, 1) +#define MPP27_TDM_FSYNC MPP(27, 0x6, 1, 1, 1) #define MPP27_UNUSED MPP(27, 0x1, 0, 0, 1) #define MPP28_GPIO MPP(28, 0x0, 1, 1, 1) -#define MPP28_UA3_TXD MPP(28, 0x4, 0, 0, 1) -#define MPP28_TDM_DRX MPP(28, 0x6, 0, 0, 1) +#define MPP28_UA3_TXD MPP(28, 0x4, 0, 1, 1) +#define MPP28_TDM_DRX MPP(28, 0x6, 1, 0, 1) #define MPP28_UNUSED MPP(28, 0x1, 0, 0, 1) #define MPP29_GPIO MPP(29, 0x0, 1, 1, 1) -#define MPP29_UA3_RXD MPP(29, 0x4, 0, 0, 1) -#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 0, 1) -#define MPP29_TDM_DTX MPP(29, 0x6, 0, 0, 1) +#define MPP29_UA3_RXD MPP(29, 0x4, 1, 0, 1) +#define MPP29_SYSRST_OUTn MPP(29, 0x5, 0, 1, 1) +#define MPP29_TDM_DTX MPP(29, 0x6, 0, 1, 1) #define MPP29_UNUSED MPP(29, 0x1, 0, 0, 1) #define MPP30_GPIO MPP(30, 0x0, 1, 1, 1) -#define MPP30_UA3_CTSn MPP(30, 0x4, 0, 0, 1) +#define MPP30_UA3_CTSn MPP(30, 0x4, 1, 0, 1) #define MPP30_UNUSED MPP(30, 0x1, 0, 0, 1) #define MPP31_GPIO MPP(31, 0x0, 1, 1, 1) -#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 0, 1) -#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 0, 1) +#define MPP31_UA3_RTSn MPP(31, 0x4, 0, 1, 1) +#define MPP31_TDM1_SCSn MPP(31, 0x6, 0, 1, 1) #define MPP31_UNUSED MPP(31, 0x1, 0, 0, 1) #define MPP32_GPIO MPP(32, 0x1, 1, 1, 1) -#define MPP32_UA3_TDX MPP(32, 0x4, 0, 0, 1) -#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 0, 1) -#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 0, 1) +#define MPP32_UA3_TDX MPP(32, 0x4, 0, 1, 1) +#define MPP32_SYSRST_OUTn MPP(32, 0x5, 0, 1, 1) +#define MPP32_TDM0_RXQ MPP(32, 0x6, 0, 1, 1) #define MPP32_UNUSED MPP(32, 0x3, 0, 0, 1) #define MPP33_GPIO MPP(33, 0x1, 1, 1, 1) -#define MPP33_UA3_RDX MPP(33, 0x4, 0, 0, 1) -#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 0, 1) +#define MPP33_UA3_RDX MPP(33, 0x4, 1, 0, 1) +#define MPP33_TDM0_TXQ MPP(33, 0x6, 0, 1, 1) #define MPP33_UNUSED MPP(33, 0x3, 0, 0, 1) #define MPP34_GPIO MPP(34, 0x1, 1, 1, 1) -#define MPP34_UA2_TDX MPP(34, 0x4, 0, 0, 1) -#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 0, 1) +#define MPP34_UA2_TDX MPP(34, 0x4, 0, 1, 1) +#define MPP34_TDM1_RXQ MPP(34, 0x6, 0, 1, 1) #define MPP34_UNUSED MPP(34, 0x3, 0, 0, 1) #define MPP35_GPIO MPP(35, 0x1, 1, 1, 1) -#define MPP35_UA2_RDX MPP(35, 0x4, 0, 0, 1) -#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 0, 1) +#define MPP35_UA2_RDX MPP(35, 0x4, 1, 0, 1) +#define MPP35_TDM1_TXQ MPP(35, 0x6, 0, 1, 1) #define MPP35_UNUSED MPP(35, 0x3, 0, 0, 1) #define MPP36_GPIO MPP(36, 0x1, 1, 1, 1) -#define MPP36_UA0_CTSn MPP(36, 0x2, 0, 0, 1) -#define MPP36_UA2_TDX MPP(36, 0x4, 0, 0, 1) -#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 0, 1) +#define MPP36_UA0_CTSn MPP(36, 0x2, 1, 0, 1) +#define MPP36_UA2_TDX MPP(36, 0x4, 0, 1, 1) +#define MPP36_TDM0_SCSn MPP(36, 0x6, 0, 1, 1) #define MPP36_UNUSED MPP(36, 0x3, 0, 0, 1) #define MPP37_GPIO MPP(37, 0x1, 1, 1, 1) -#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 0, 1) -#define MPP37_UA2_RXD MPP(37, 0x4, 0, 0, 1) -#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 0, 1) -#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 0, 1) +#define MPP37_UA0_RTSn MPP(37, 0x2, 0, 1, 1) +#define MPP37_UA2_RXD MPP(37, 0x4, 1, 0, 1) +#define MPP37_SYSRST_OUTn MPP(37, 0x5, 0, 1, 1) +#define MPP37_TDM_SCLK MPP(37, 0x6, 0, 1, 1) #define MPP37_UNUSED MPP(37, 0x3, 0, 0, 1) #define MPP38_GPIO MPP(38, 0x1, 1, 1, 1) -#define MPP38_UA1_CTSn MPP(38, 0x2, 0, 0, 1) -#define MPP38_UA3_TXD MPP(38, 0x4, 0, 0, 1) -#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 0, 1) -#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 0, 1) +#define MPP38_UA1_CTSn MPP(38, 0x2, 1, 0, 1) +#define MPP38_UA3_TXD MPP(38, 0x4, 0, 1, 1) +#define MPP38_SYSRST_OUTn MPP(38, 0x5, 0, 1, 1) +#define MPP38_TDM_SMOSI MPP(38, 0x6, 0, 1, 1) #define MPP38_UNUSED MPP(38, 0x3, 0, 0, 1) #define MPP39_GPIO MPP(39, 0x1, 1, 1, 1) -#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 0, 1) -#define MPP39_UA3_RXD MPP(39, 0x4, 0, 0, 1) -#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 0, 1) -#define MPP39_TDM_SMISO MPP(39, 0x6, 0, 0, 1) +#define MPP39_UA1_RTSn MPP(39, 0x2, 0, 1, 1) +#define MPP39_UA3_RXD MPP(39, 0x4, 1, 0, 1) +#define MPP39_SYSRST_OUTn MPP(39, 0x5, 0, 1, 1) +#define MPP39_TDM_SMISO MPP(39, 0x6, 1, 0, 1) #define MPP39_UNUSED MPP(39, 0x3, 0, 0, 1) #define MPP40_GPIO MPP(40, 0x1, 1, 1, 1) -#define MPP40_TDM_INTn MPP(40, 0x6, 0, 0, 1) +#define MPP40_TDM_INTn MPP(40, 0x6, 1, 0, 1) #define MPP40_UNUSED MPP(40, 0x0, 0, 0, 1) #define MPP41_GPIO MPP(41, 0x1, 1, 1, 1) -#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 0, 1) +#define MPP41_TDM_RSTn MPP(41, 0x6, 0, 1, 1) #define MPP41_UNUSED MPP(41, 0x0, 0, 0, 1) #define MPP42_GPIO MPP(42, 0x1, 1, 1, 1) -#define MPP42_TDM_PCLK MPP(42, 0x6, 0, 0, 1) +#define MPP42_TDM_PCLK MPP(42, 0x6, 1, 1, 1) #define MPP42_UNUSED MPP(42, 0x0, 0, 0, 1) #define MPP43_GPIO MPP(43, 0x1, 1, 1, 1) -#define MPP43_TDM_FSYNC MPP(43, 0x6, 0, 0, 1) +#define MPP43_TDM_FSYNC MPP(43, 0x6, 1, 1, 1) #define MPP43_UNUSED MPP(43, 0x0, 0, 0, 1) #define MPP44_GPIO MPP(44, 0x1, 1, 1, 1) -#define MPP44_TDM_DRX MPP(44, 0x6, 0, 0, 1) +#define MPP44_TDM_DRX MPP(44, 0x6, 1, 0, 1) #define MPP44_UNUSED MPP(44, 0x0, 0, 0, 1) #define MPP45_GPIO MPP(45, 0x1, 1, 1, 1) -#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 0, 1) -#define MPP45_TDM_DRX MPP(45, 0x6, 0, 0, 1) +#define MPP45_SATA0_ACTn MPP(45, 0x3, 0, 1, 1) +#define MPP45_TDM_DRX MPP(45, 0x6, 0, 1, 1) #define MPP45_UNUSED MPP(45, 0x0, 0, 0, 1) #define MPP46_GPIO MPP(46, 0x1, 1, 1, 1) -#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 0, 1) +#define MPP46_TDM_SCSn MPP(46, 0x6, 0, 1, 1) #define MPP46_UNUSED MPP(46, 0x0, 0, 0, 1) @@ -323,14 +323,14 @@ #define MPP48_GPIO MPP(48, 0x1, 1, 1, 1) -#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 0, 1) +#define MPP48_SATA1_ACTn MPP(48, 0x3, 0, 1, 1) #define MPP48_UNUSED MPP(48, 0x2, 0, 0, 1) #define MPP49_GPIO MPP(49, 0x1, 1, 1, 1) -#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 0, 1) -#define MPP49_M_BB MPP(49, 0x4, 0, 0, 1) +#define MPP49_SATA0_ACTn MPP(49, 0x3, 0, 1, 1) +#define MPP49_M_BB MPP(49, 0x4, 1, 0, 1) #define MPP49_UNUSED MPP(49, 0x2, 0, 0, 1) diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index 72ce50ecf328..d965da45160e 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -117,6 +117,7 @@ comment "OMAP Board Type" config MACH_OMAP_GENERIC bool "Generic OMAP2+ board" depends on ARCH_OMAP2PLUS + select USE_OF default y help Support for generic TI OMAP2+ boards using Flattened Device Tree. diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index bd76394ccaf8..fc9b238cbc19 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -11,9 +11,9 @@ hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o clock-common = clock.o clock_common_data.o \ clkt_dpll.o clkt_clksel.o -secure-common = omap-smc.o omap-secure.o +secure-common = omap-smc.o omap-secure.o -obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) diff --git a/trunk/arch/arm/mach-omap2/board-cm-t35.c b/trunk/arch/arm/mach-omap2/board-cm-t35.c index d73316ed4207..e921e3be24a4 100644 --- a/trunk/arch/arm/mach-omap2/board-cm-t35.c +++ b/trunk/arch/arm/mach-omap2/board-cm-t35.c @@ -437,7 +437,7 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = { .reset_gpio_port[2] = -EINVAL }; -static void __init cm_t35_init_usbh(void) +static void cm_t35_init_usbh(void) { int err; diff --git a/trunk/arch/arm/mach-omap2/board-generic.c b/trunk/arch/arm/mach-omap2/board-generic.c index 02d7e828a14b..00b1d024fa87 100644 --- a/trunk/arch/arm/mach-omap2/board-generic.c +++ b/trunk/arch/arm/mach-omap2/board-generic.c @@ -17,7 +17,6 @@ #include #include -#include #include #include @@ -91,18 +90,18 @@ static void __init omap3_init(void) } #endif -#ifdef CONFIG_SOC_OMAP2420 +#if defined(CONFIG_SOC_OMAP2420) static const char *omap242x_boards_compat[] __initdata = { "ti,omap2420", NULL, }; DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") + .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap242x_map_io, .init_early = omap2420_init_early, .init_irq = omap2_init_irq, - .handle_irq = omap2_intc_handle_irq, .init_machine = omap_generic_init, .timer = &omap2_timer, .dt_compat = omap242x_boards_compat, @@ -110,13 +109,14 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)") MACHINE_END #endif -#ifdef CONFIG_SOC_OMAP2430 +#if defined(CONFIG_SOC_OMAP2430) static const char *omap243x_boards_compat[] __initdata = { "ti,omap2430", NULL, }; DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") + .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap243x_map_io, .init_early = omap2430_init_early, @@ -129,18 +129,18 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)") MACHINE_END #endif -#ifdef CONFIG_ARCH_OMAP3 +#if defined(CONFIG_ARCH_OMAP3) static const char *omap3_boards_compat[] __initdata = { "ti,omap3", NULL, }; DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") + .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap3_map_io, .init_early = omap3430_init_early, .init_irq = omap3_init_irq, - .handle_irq = omap3_intc_handle_irq, .init_machine = omap3_init, .timer = &omap3_timer, .dt_compat = omap3_boards_compat, @@ -148,18 +148,18 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)") MACHINE_END #endif -#ifdef CONFIG_ARCH_OMAP4 +#if defined(CONFIG_ARCH_OMAP4) static const char *omap4_boards_compat[] __initdata = { "ti,omap4", NULL, }; DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") + .atag_offset = 0x100, .reserve = omap_reserve, .map_io = omap4_map_io, .init_early = omap4430_init_early, .init_irq = gic_init_irq, - .handle_irq = gic_handle_irq, .init_machine = omap4_init, .timer = &omap4_timer, .dt_compat = omap4_boards_compat, diff --git a/trunk/arch/arm/mach-omap2/pm.c b/trunk/arch/arm/mach-omap2/pm.c index ad4f69394166..1881fe915149 100644 --- a/trunk/arch/arm/mach-omap2/pm.c +++ b/trunk/arch/arm/mach-omap2/pm.c @@ -227,14 +227,6 @@ postcore_initcall(omap2_common_pm_init); static int __init omap2_common_pm_late_init(void) { - /* - * In the case of DT, the PMIC and SR initialization will be done using - * a completely different mechanism. - * Disable this part if a DT blob is available. - */ - if (of_have_populated_dt()) - return 0; - /* Init the voltage layer */ omap_pmic_late_init(); omap_voltage_late_init(); diff --git a/trunk/arch/arm/mach-omap2/pm24xx.c b/trunk/arch/arm/mach-omap2/pm24xx.c index a4eb5c280435..1f736222a629 100644 --- a/trunk/arch/arm/mach-omap2/pm24xx.c +++ b/trunk/arch/arm/mach-omap2/pm24xx.c @@ -82,7 +82,13 @@ static int omap2_fclks_active(void) f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); - return (f1 | f2) ? 1 : 0; + /* Ignore UART clocks. These are handled by UART core (serial.c) */ + f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); + f2 &= ~OMAP24XX_EN_UART3_MASK; + + if (f1 | f2) + return 1; + return 0; } static void omap2_enter_full_retention(void) diff --git a/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c index 57db2038b23c..c005e2f5e383 100644 --- a/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c +++ b/trunk/arch/arm/mach-omap2/voltagedomains3xxx_data.c @@ -108,7 +108,6 @@ void __init omap3xxx_voltagedomains_init(void) * XXX Will depend on the process, validation, and binning * for the currently-running IC */ -#ifdef CONFIG_PM_OPP if (cpu_is_omap3630()) { omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data; omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data; @@ -116,7 +115,6 @@ void __init omap3xxx_voltagedomains_init(void) omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data; omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data; } -#endif if (cpu_is_omap3517() || cpu_is_omap3505()) voltdms = voltagedomains_am35xx; diff --git a/trunk/arch/arm/mach-omap2/voltagedomains44xx_data.c b/trunk/arch/arm/mach-omap2/voltagedomains44xx_data.c index c3115f6853d4..4e11d022595d 100644 --- a/trunk/arch/arm/mach-omap2/voltagedomains44xx_data.c +++ b/trunk/arch/arm/mach-omap2/voltagedomains44xx_data.c @@ -100,11 +100,9 @@ void __init omap44xx_voltagedomains_init(void) * XXX Will depend on the process, validation, and binning * for the currently-running IC */ -#ifdef CONFIG_PM_OPP omap4_voltdm_mpu.volt_data = omap44xx_vdd_mpu_volt_data; omap4_voltdm_iva.volt_data = omap44xx_vdd_iva_volt_data; omap4_voltdm_core.volt_data = omap44xx_vdd_core_volt_data; -#endif for (i = 0; voltdm = voltagedomains_omap4[i], voltdm; i++) voltdm->sys_clk.name = sys_clk_name; diff --git a/trunk/arch/arm/mach-orion5x/common.c b/trunk/arch/arm/mach-orion5x/common.c index 5dad38ec00ea..0e28bae20bd4 100644 --- a/trunk/arch/arm/mach-orion5x/common.c +++ b/trunk/arch/arm/mach-orion5x/common.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include @@ -73,8 +72,7 @@ void __init orion5x_map_io(void) ****************************************************************************/ void __init orion5x_ehci0_init(void) { - orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL, - EHCI_PHY_ORION); + orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL); } diff --git a/trunk/arch/arm/mach-s3c2410/cpu-freq.c b/trunk/arch/arm/mach-s3c2410/cpu-freq.c index 5404535da1a5..7dc6c46b5e2b 100644 --- a/trunk/arch/arm/mach-s3c2410/cpu-freq.c +++ b/trunk/arch/arm/mach-s3c2410/cpu-freq.c @@ -115,8 +115,7 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = { .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), }; -static int s3c2410_cpufreq_add(struct device *dev, - struct subsys_interface *sif) +static int s3c2410_cpufreq_add(struct device *dev) { return s3c_cpufreq_register(&s3c2410_cpufreq_info); } @@ -134,8 +133,7 @@ static int __init s3c2410_cpufreq_init(void) arch_initcall(s3c2410_cpufreq_init); -static int s3c2410a_cpufreq_add(struct device *dev, - struct subsys_interface *sif) +static int s3c2410a_cpufreq_add(struct device *dev) { /* alter the maximum freq settings for S3C2410A. If a board knows * it only has a maximum of 200, then it should register its own @@ -146,7 +144,7 @@ static int s3c2410a_cpufreq_add(struct device *dev, s3c2410_cpufreq_info.max.pclk = 66500000; s3c2410_cpufreq_info.name = "s3c2410a"; - return s3c2410_cpufreq_add(dev, sif); + return s3c2410_cpufreq_add(dev); } static struct subsys_interface s3c2410a_cpufreq_interface = { diff --git a/trunk/arch/arm/mach-s3c2410/dma.c b/trunk/arch/arm/mach-s3c2410/dma.c index 4803338cf56e..2afd00014a77 100644 --- a/trunk/arch/arm/mach-s3c2410/dma.c +++ b/trunk/arch/arm/mach-s3c2410/dma.c @@ -132,8 +132,7 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = { }, }; -static int __init s3c2410_dma_add(struct device *dev, - struct subsys_interface *sif) +static int __init s3c2410_dma_add(struct device *dev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2410_dma_order); @@ -149,7 +148,7 @@ static struct subsys_interface s3c2410_dma_interface = { static int __init s3c2410_dma_drvinit(void) { - return subsys_interface_register(&s3c2410_dma_interface); + return subsys_interface_register(&s3c2410_interface); } arch_initcall(s3c2410_dma_drvinit); diff --git a/trunk/arch/arm/mach-s3c2410/pll.c b/trunk/arch/arm/mach-s3c2410/pll.c index e0b3b347da82..c07438bfc99f 100644 --- a/trunk/arch/arm/mach-s3c2410/pll.c +++ b/trunk/arch/arm/mach-s3c2410/pll.c @@ -66,7 +66,7 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = { { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, }; -static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) +static int s3c2410_plls_add(struct device *dev) { return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz)); } diff --git a/trunk/arch/arm/mach-s3c2410/pm.c b/trunk/arch/arm/mach-s3c2410/pm.c index 03f706dd6009..fda5385deff6 100644 --- a/trunk/arch/arm/mach-s3c2410/pm.c +++ b/trunk/arch/arm/mach-s3c2410/pm.c @@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = { .resume = s3c2410_pm_resume, }; -static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif) +static int s3c2410_pm_add(struct device *dev) { pm_cpu_prep = s3c2410_pm_prepare; pm_cpu_sleep = s3c2410_cpu_suspend; diff --git a/trunk/arch/arm/mach-s3c2412/cpu-freq.c b/trunk/arch/arm/mach-s3c2412/cpu-freq.c index 125be7d5fa60..d8664b7652ce 100644 --- a/trunk/arch/arm/mach-s3c2412/cpu-freq.c +++ b/trunk/arch/arm/mach-s3c2412/cpu-freq.c @@ -194,8 +194,7 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = { .debug_io_show = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs), }; -static int s3c2412_cpufreq_add(struct device *dev, - struct subsys_interface *sif) +static int s3c2412_cpufreq_add(struct device *dev) { unsigned long fclk_rate; diff --git a/trunk/arch/arm/mach-s3c2412/dma.c b/trunk/arch/arm/mach-s3c2412/dma.c index 38472ac920ff..142acd3b5e15 100644 --- a/trunk/arch/arm/mach-s3c2412/dma.c +++ b/trunk/arch/arm/mach-s3c2412/dma.c @@ -159,8 +159,7 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = { .map_size = ARRAY_SIZE(s3c2412_dma_mappings), }; -static int __init s3c2412_dma_add(struct device *dev, - struct subsys_interface *sif) +static int __init s3c2412_dma_add(struct device *dev) { s3c2410_dma_init(); return s3c24xx_dma_init_map(&s3c2412_dma_sel); diff --git a/trunk/arch/arm/mach-s3c2412/irq.c b/trunk/arch/arm/mach-s3c2412/irq.c index e65619ddbccc..a8a46c1644f4 100644 --- a/trunk/arch/arm/mach-s3c2412/irq.c +++ b/trunk/arch/arm/mach-s3c2412/irq.c @@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state) static struct irq_chip s3c2412_irq_rtc_chip; -static int s3c2412_irq_add(struct device *dev, struct subsys_interface *sif) +static int s3c2412_irq_add(struct device *dev) { unsigned int irqno; diff --git a/trunk/arch/arm/mach-s3c2412/pm.c b/trunk/arch/arm/mach-s3c2412/pm.c index d04588506ec4..d1adfa65f66d 100644 --- a/trunk/arch/arm/mach-s3c2412/pm.c +++ b/trunk/arch/arm/mach-s3c2412/pm.c @@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void) { } -static int s3c2412_pm_add(struct device *dev, struct subsys_interface *sif) +static int s3c2412_pm_add(struct device *dev) { pm_cpu_prep = s3c2412_pm_prepare; pm_cpu_sleep = s3c2412_cpu_suspend; diff --git a/trunk/arch/arm/mach-s3c2416/irq.c b/trunk/arch/arm/mach-s3c2416/irq.c index fd49f35e448e..36df761061de 100644 --- a/trunk/arch/arm/mach-s3c2416/irq.c +++ b/trunk/arch/arm/mach-s3c2416/irq.c @@ -213,8 +213,7 @@ static int __init s3c2416_add_sub(unsigned int base, return 0; } -static int __init s3c2416_irq_add(struct device *dev, - struct subsys_interface *sif) +static int __init s3c2416_irq_add(struct device *dev) { printk(KERN_INFO "S3C2416: IRQ Support\n"); diff --git a/trunk/arch/arm/mach-s3c2416/pm.c b/trunk/arch/arm/mach-s3c2416/pm.c index 1bd4817b8eb8..3bdb15a0d419 100644 --- a/trunk/arch/arm/mach-s3c2416/pm.c +++ b/trunk/arch/arm/mach-s3c2416/pm.c @@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void) __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); } -static int s3c2416_pm_add(struct device *dev, struct subsys_interface *sif) +static int s3c2416_pm_add(struct device *dev) { pm_cpu_prep = s3c2416_pm_prepare; pm_cpu_sleep = s3c2416_cpu_suspend; diff --git a/trunk/arch/arm/mach-s3c2440/clock.c b/trunk/arch/arm/mach-s3c2440/clock.c index 414364eb426c..bedbc87a3426 100644 --- a/trunk/arch/arm/mach-s3c2440/clock.c +++ b/trunk/arch/arm/mach-s3c2440/clock.c @@ -149,7 +149,7 @@ static struct clk_lookup s3c2440_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n), }; -static int s3c2440_clk_add(struct device *dev, struct subsys_interface *sif) +static int s3c2440_clk_add(struct device *dev) { struct clk *clock_upll; struct clk *clock_h; diff --git a/trunk/arch/arm/mach-s3c2440/dma.c b/trunk/arch/arm/mach-s3c2440/dma.c index 5f0a0c8ef84f..15b1ddf8f626 100644 --- a/trunk/arch/arm/mach-s3c2440/dma.c +++ b/trunk/arch/arm/mach-s3c2440/dma.c @@ -174,8 +174,7 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = { }, }; -static int __init s3c2440_dma_add(struct device *dev, - struct subsys_interface *sif) +static int __init s3c2440_dma_add(struct device *dev) { s3c2410_dma_init(); s3c24xx_dma_order_set(&s3c2440_dma_order); diff --git a/trunk/arch/arm/mach-s3c2440/irq.c b/trunk/arch/arm/mach-s3c2440/irq.c index 4a18cde439cc..4fee9bc6bcb5 100644 --- a/trunk/arch/arm/mach-s3c2440/irq.c +++ b/trunk/arch/arm/mach-s3c2440/irq.c @@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = { .irq_ack = s3c_irq_wdtac97_ack, }; -static int s3c2440_irq_add(struct device *dev, struct subsys_interface *sif) +static int s3c2440_irq_add(struct device *dev) { unsigned int irqno; diff --git a/trunk/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/trunk/arch/arm/mach-s3c2440/s3c2440-cpufreq.c index 61776764d9f4..cf7596694efe 100644 --- a/trunk/arch/arm/mach-s3c2440/s3c2440-cpufreq.c +++ b/trunk/arch/arm/mach-s3c2440/s3c2440-cpufreq.c @@ -270,8 +270,7 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = { .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs), }; -static int s3c2440_cpufreq_add(struct device *dev, - struct subsys_interface *sif) +static int s3c2440_cpufreq_add(struct device *dev) { xtal = s3c_cpufreq_clk_get(NULL, "xtal"); hclk = s3c_cpufreq_clk_get(NULL, "hclk"); diff --git a/trunk/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/trunk/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c index 551fb433be87..b5368ae8d7fe 100644 --- a/trunk/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c +++ b/trunk/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c @@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ }; -static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) +static int s3c2440_plls12_add(struct device *dev) { struct clk *xtal_clk; unsigned long xtal; diff --git a/trunk/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/trunk/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c index 3f15bcf64290..42f2b5cd2399 100644 --- a/trunk/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c +++ b/trunk/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c @@ -79,8 +79,7 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ }; -static int s3c2440_plls169344_add(struct device *dev, - struct subsys_interface *sif) +static int s3c2440_plls169344_add(struct device *dev) { struct clk *xtal_clk; unsigned long xtal; diff --git a/trunk/arch/arm/mach-s3c2440/s3c2442.c b/trunk/arch/arm/mach-s3c2440/s3c2442.c index 22cb7c94a8c8..8004e0497bf4 100644 --- a/trunk/arch/arm/mach-s3c2440/s3c2442.c +++ b/trunk/arch/arm/mach-s3c2440/s3c2442.c @@ -122,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = { }, }; -static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif) +static int s3c2442_clk_add(struct device *dev) { struct clk *clock_upll; struct clk *clock_h; diff --git a/trunk/arch/arm/mach-s3c2440/s3c244x-clock.c b/trunk/arch/arm/mach-s3c2440/s3c244x-clock.c index 6d9b688c442b..b3fdbdda3d5f 100644 --- a/trunk/arch/arm/mach-s3c2440/s3c244x-clock.c +++ b/trunk/arch/arm/mach-s3c2440/s3c244x-clock.c @@ -72,7 +72,7 @@ static struct clk clk_arm = { }, }; -static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif) +static int s3c244x_clk_add(struct device *dev) { unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN); unsigned long clkdivn; diff --git a/trunk/arch/arm/mach-s3c2440/s3c244x-irq.c b/trunk/arch/arm/mach-s3c2440/s3c244x-irq.c index 5fe8e58d3afd..74d3dcf46a48 100644 --- a/trunk/arch/arm/mach-s3c2440/s3c244x-irq.c +++ b/trunk/arch/arm/mach-s3c2440/s3c244x-irq.c @@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = { .irq_ack = s3c_irq_cam_ack, }; -static int s3c244x_irq_add(struct device *dev, struct subsys_interface *sif) +static int s3c244x_irq_add(struct device *dev) { unsigned int irqno; diff --git a/trunk/arch/arm/mach-s3c2443/dma.c b/trunk/arch/arm/mach-s3c2443/dma.c index 14224517e621..de6b4a23c9ed 100644 --- a/trunk/arch/arm/mach-s3c2443/dma.c +++ b/trunk/arch/arm/mach-s3c2443/dma.c @@ -135,8 +135,7 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = { .map_size = ARRAY_SIZE(s3c2443_dma_mappings), }; -static int __init s3c2443_dma_add(struct device *dev, - struct subsys_interface *sif) +static int __init s3c2443_dma_add(struct device *dev) { s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100); return s3c24xx_dma_init_map(&s3c2443_dma_sel); diff --git a/trunk/arch/arm/mach-s3c2443/irq.c b/trunk/arch/arm/mach-s3c2443/irq.c index ac2829f56d12..35e4ff24fb43 100644 --- a/trunk/arch/arm/mach-s3c2443/irq.c +++ b/trunk/arch/arm/mach-s3c2443/irq.c @@ -241,8 +241,7 @@ static int __init s3c2443_add_sub(unsigned int base, return 0; } -static int __init s3c2443_irq_add(struct device *dev, - struct subsys_interface *sif) +static int __init s3c2443_irq_add(struct device *dev) { printk("S3C2443: IRQ Support\n"); diff --git a/trunk/arch/arm/mach-s3c64xx/clock.c b/trunk/arch/arm/mach-s3c64xx/clock.c index aebbcc291b4e..31bb27dc4aeb 100644 --- a/trunk/arch/arm/mach-s3c64xx/clock.c +++ b/trunk/arch/arm/mach-s3c64xx/clock.c @@ -138,11 +138,6 @@ static struct clk init_clocks_off[] = { .ctrlbit = S3C_CLKCON_PCLK_TSADC, }, { .name = "i2c", -#ifdef CONFIG_S3C_DEV_I2C1 - .devname = "s3c2440-i2c.0", -#else - .devname = "s3c2440-i2c", -#endif .parent = &clk_p, .enable = s3c64xx_pclk_ctrl, .ctrlbit = S3C_CLKCON_PCLK_IIC, diff --git a/trunk/arch/arm/mach-s3c64xx/common.c b/trunk/arch/arm/mach-s3c64xx/common.c index bee7dcd4df7c..4a7394d4bd9e 100644 --- a/trunk/arch/arm/mach-s3c64xx/common.c +++ b/trunk/arch/arm/mach-s3c64xx/common.c @@ -49,7 +49,7 @@ /* uart registration process */ -static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) +void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) { s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); } diff --git a/trunk/arch/arm/mach-s5p64x0/pm.c b/trunk/arch/arm/mach-s5p64x0/pm.c index 9cba18bfe47b..23f9b22439c9 100644 --- a/trunk/arch/arm/mach-s5p64x0/pm.c +++ b/trunk/arch/arm/mach-s5p64x0/pm.c @@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void) } -static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif) +static int s5p64x0_pm_add(struct device *dev) { pm_cpu_prep = s5p64x0_pm_prepare; pm_cpu_sleep = s5p64x0_cpu_suspend; diff --git a/trunk/arch/arm/mach-s5pv210/clock.c b/trunk/arch/arm/mach-s5pv210/clock.c index b9ec0c35379f..c78dfddd77fd 100644 --- a/trunk/arch/arm/mach-s5pv210/clock.c +++ b/trunk/arch/arm/mach-s5pv210/clock.c @@ -175,7 +175,7 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); } -static int s5pv210_clk_hdmiphy_ctrl(struct clk *clk, int enable) +static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable); } @@ -372,7 +372,7 @@ static struct clk init_clocks_off[] = { }, { .name = "hdmiphy", .devname = "s5pv210-hdmi", - .enable = s5pv210_clk_hdmiphy_ctrl, + .enable = exynos4_clk_hdmiphy_ctrl, .ctrlbit = (1 << 0), }, { .name = "dacphy", diff --git a/trunk/arch/arm/mach-s5pv210/pm.c b/trunk/arch/arm/mach-s5pv210/pm.c index 736bfb103cbc..677c71c41e50 100644 --- a/trunk/arch/arm/mach-s5pv210/pm.c +++ b/trunk/arch/arm/mach-s5pv210/pm.c @@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void) s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save)); } -static int s5pv210_pm_add(struct device *dev, struct subsys_interface *sif) +static int s5pv210_pm_add(struct device *dev) { pm_cpu_prep = s5pv210_pm_prepare; pm_cpu_sleep = s5pv210_cpu_suspend; diff --git a/trunk/arch/arm/mach-shmobile/board-ag5evm.c b/trunk/arch/arm/mach-shmobile/board-ag5evm.c index 068b754bc348..eff8a96c75ee 100644 --- a/trunk/arch/arm/mach-shmobile/board-ag5evm.c +++ b/trunk/arch/arm/mach-shmobile/board-ag5evm.c @@ -30,7 +30,6 @@ #include #include #include -#include #include #include #include @@ -38,6 +37,7 @@ #include #include #include +#include #include