From 727b344e16cc5d57e518872e01d77bc4a0edde0f Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 14 Apr 2012 18:57:10 +0100 Subject: [PATCH] --- yaml --- r: 299875 b: refs/heads/master c: 354535845ffb74d8a4827fbdaa493037d0030eea h: refs/heads/master i: 299873: 0b9977cbb26f4c31a86259cb50297c9027ff590a 299871: 283fc4a85d31956ef8a058d765769fa20a51363a v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-omap/dma.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index d4287240d6ea..02830f795eab 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 754aba436bed2051deaa2af7bdda553df056b6fc +refs/heads/master: 354535845ffb74d8a4827fbdaa493037d0030eea diff --git a/trunk/arch/arm/plat-omap/dma.c b/trunk/arch/arm/plat-omap/dma.c index ecdb3da0dea9..c58d896cd5c3 100644 --- a/trunk/arch/arm/plat-omap/dma.c +++ b/trunk/arch/arm/plat-omap/dma.c @@ -916,6 +916,13 @@ void omap_start_dma(int lch) l |= OMAP_DMA_CCR_BUFFERING_DISABLE; l |= OMAP_DMA_CCR_EN; + /* + * As dma_write() uses IO accessors which are weakly ordered, there + * is no guarantee that data in coherent DMA memory will be visible + * to the DMA device. Add a memory barrier here to ensure that any + * such data is visible prior to enabling DMA. + */ + mb(); p->dma_write(l, CCR, lch); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; @@ -965,6 +972,13 @@ void omap_stop_dma(int lch) p->dma_write(l, CCR, lch); } + /* + * Ensure that data transferred by DMA is visible to any access + * after DMA has been disabled. This is important for coherent + * DMA regions. + */ + mb(); + if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch = lch; char dma_chan_link_map[dma_lch_count];