From 728fa1397c804a0a3e506f24ad0030817dc6bb15 Mon Sep 17 00:00:00 2001 From: Seungwhan Youn Date: Thu, 14 Oct 2010 10:39:15 +0900 Subject: [PATCH] --- yaml --- r: 221151 b: refs/heads/master c: 42a6e20e4fd4755e6b4539891a4f20905af18dcd h: refs/heads/master i: 221149: 5b11340c39d25369bfa50d9890ae46d9378a37fb 221147: a32f41b87b06ae911dc0dc8853ffafd59db2bee1 221143: 3512d25021c40199ec04c5565d157eb4a4910aed 221135: b6b17baaa32016324c4ef0092b4d85b4e9121532 221119: 5a22a0834183b18f614be99ac7b0c07da76d55de v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-s5pv210/clock.c | 3 ++- trunk/arch/arm/mach-s5pv210/include/mach/regs-clock.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index fb403258b79b..22aec538f031 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: d4b34c6c849d67b7afaa90d55dc7fab981c72950 +refs/heads/master: 42a6e20e4fd4755e6b4539891a4f20905af18dcd diff --git a/trunk/arch/arm/mach-s5pv210/clock.c b/trunk/arch/arm/mach-s5pv210/clock.c index b9c9f3bd2954..00a721771a43 100644 --- a/trunk/arch/arm/mach-s5pv210/clock.c +++ b/trunk/arch/arm/mach-s5pv210/clock.c @@ -1082,7 +1082,8 @@ void __init_or_cpufreq s5pv210_setup_clocks(void) apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); - epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); + epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), + __raw_readl(S5P_EPLL_CON1), pll_4600); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); diff --git a/trunk/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/trunk/arch/arm/mach-s5pv210/include/mach/regs-clock.h index 61b55c8e438c..ebaabe021af9 100644 --- a/trunk/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/trunk/arch/arm/mach-s5pv210/include/mach/regs-clock.h @@ -25,6 +25,7 @@ #define S5P_APLL_CON S5P_CLKREG(0x100) #define S5P_MPLL_CON S5P_CLKREG(0x108) #define S5P_EPLL_CON S5P_CLKREG(0x110) +#define S5P_EPLL_CON1 S5P_CLKREG(0x114) #define S5P_VPLL_CON S5P_CLKREG(0x120) #define S5P_CLK_SRC0 S5P_CLKREG(0x200)