From 732fdc4f0b847d0aa8bac42c9e166857fa786b91 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Sat, 24 Oct 2009 02:49:59 -0200 Subject: [PATCH] --- yaml --- r: 172317 b: refs/heads/master c: 18fa000ae453767b59ab97477925895a3f0c46ea h: refs/heads/master i: 172315: 697370b024c5876c764a2a718e04554931464398 v: v3 --- [refs] | 2 +- trunk/arch/x86/kvm/svm.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index 7975de1ce730..558e9b99ab73 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fa40052ca04bdbbeb20b839cc8ffe9fa7beefbe9 +refs/heads/master: 18fa000ae453767b59ab97477925895a3f0c46ea diff --git a/trunk/arch/x86/kvm/svm.c b/trunk/arch/x86/kvm/svm.c index ffa6ad216b71..c9ef6c0e1e98 100644 --- a/trunk/arch/x86/kvm/svm.c +++ b/trunk/arch/x86/kvm/svm.c @@ -628,11 +628,12 @@ static void init_vmcb(struct vcpu_svm *svm) save->rip = 0x0000fff0; svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip; - /* - * cr0 val on cpu init should be 0x60000010, we enable cpu - * cache by default. the orderly way is to enable cache in bios. + /* This is the guest-visible cr0 value. + * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0. */ - save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; + svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; + kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0); + save->cr4 = X86_CR4_PAE; /* rdx = ?? */