From 7356e835ac356fec70d604e26a88d41aa3d09ec4 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 6 Jul 2007 14:40:05 +0100
Subject: [PATCH] --- yaml --- r: 58235 b: refs/heads/master c:
 fde97822a295da9dffa4af643b49a58ffc4516ad h: refs/heads/master i:   58233:
 881a109dd053b1febff64c04cd2e54ca5eab02b5   58231:
 eda5ae2ef40383186fc868dabcca66267732600e v: v3

---
 [refs]                       |  2 +-
 trunk/include/asm-mips/cpu.h | 11 +++++++++++
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index d07ccd1c3094..597b7c23a74f 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 075c733e19ce7530b53b78151cc4d303c8f64548
+refs/heads/master: fde97822a295da9dffa4af643b49a58ffc4516ad
diff --git a/trunk/include/asm-mips/cpu.h b/trunk/include/asm-mips/cpu.h
index d38fdbf845b2..2924069075e0 100644
--- a/trunk/include/asm-mips/cpu.h
+++ b/trunk/include/asm-mips/cpu.h
@@ -124,6 +124,17 @@
 #define PRID_REV_VR4181A	0x0070	/* Same as VR4122 */
 #define PRID_REV_VR4130		0x0080
 
+/*
+ * Older processors used to encode processor version and revision in two
+ * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
+ * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
+ * the patch number.  *ARGH*
+ */
+#define PRID_REV_ENCODE_44(ver, rev)					\
+	((ver) << 4 | (rev))
+#define PRID_REV_ENCODE_332(ver, rev, patch)				\
+	((ver) << 5 | (rev) << 2 | (patch))
+
 /*
  * FPU implementation/revision register (CP1 control register 0).
  *