From 737a46780030a15853dddd3202111dffa2d73f54 Mon Sep 17 00:00:00 2001 From: Tomas Winkler Date: Thu, 17 Apr 2008 16:03:38 -0700 Subject: [PATCH] --- yaml --- r: 102443 b: refs/heads/master c: a693f187facbf25925bbcf201db88c5384468646 h: refs/heads/master i: 102441: c00a94f283e3eec5f9ae85a161381f419fece6ed 102439: e2bb9ce71215fc28ce37b1ab44edd5873cf52d03 v: v3 --- [refs] | 2 +- trunk/drivers/net/wireless/iwlwifi/iwl-3945.c | 2 +- trunk/drivers/net/wireless/iwlwifi/iwl-csr.h | 7 +++++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 9d9d2c0011ce..a1340fb01332 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fe07aa7acd9ec221d4440a38ffc9a58776cb34bc +refs/heads/master: a693f187facbf25925bbcf201db88c5384468646 diff --git a/trunk/drivers/net/wireless/iwlwifi/iwl-3945.c b/trunk/drivers/net/wireless/iwlwifi/iwl-3945.c index d3406830c8e3..8464397f7816 100644 --- a/trunk/drivers/net/wireless/iwlwifi/iwl-3945.c +++ b/trunk/drivers/net/wireless/iwlwifi/iwl-3945.c @@ -1229,7 +1229,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv) iwl3945_power_init_handle(priv); spin_lock_irqsave(&priv->lock, flags); - iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24)); + iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL); iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS, CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); diff --git a/trunk/drivers/net/wireless/iwlwifi/iwl-csr.h b/trunk/drivers/net/wireless/iwlwifi/iwl-csr.h index a59f48b02f05..82c7445d2927 100644 --- a/trunk/drivers/net/wireless/iwlwifi/iwl-csr.h +++ b/trunk/drivers/net/wireless/iwlwifi/iwl-csr.h @@ -95,8 +95,7 @@ #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100) #define CSR_LED_REG (CSR_BASE+0x094) -/* Analog phase-lock-loop configuration (3945 only) - * Set bit 24. */ +/* Analog phase-lock-loop configuration */ #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c) /* * Indicates hardware rev, to determine CCK backoff for txpower calculation. @@ -219,6 +218,10 @@ #define CSR_LED_REG_TRUN_ON (0x78) #define CSR_LED_REG_TRUN_OFF (0x38) +/* ANA_PLL */ +#define CSR39_ANA_PLL_CFG_VAL (0x01000000) +#define CSR50_ANA_PLL_CFG_VAL (0x00880300) + /*=== HBUS (Host-side Bus) ===*/ #define HBUS_BASE (0x400) /*