From 73cd081f7f1281c4f4d081593ed117362e248b21 Mon Sep 17 00:00:00 2001 From: Yu Zhao Date: Wed, 25 Feb 2009 13:15:52 +0800 Subject: [PATCH] --- yaml --- r: 139348 b: refs/heads/master c: 998dd7c719f62dcfa91d7bf7f4eb9c160e03d817 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/include/linux/pci_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 0c4ff2a7a63c..7da291dd7571 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c74d724462d1845535667f4d3f720e02e3432e53 +refs/heads/master: 998dd7c719f62dcfa91d7bf7f4eb9c160e03d817 diff --git a/trunk/include/linux/pci_regs.h b/trunk/include/linux/pci_regs.h index 027815b4635e..b647a4df59fc 100644 --- a/trunk/include/linux/pci_regs.h +++ b/trunk/include/linux/pci_regs.h @@ -235,7 +235,7 @@ #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ #define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ -#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ +#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */