From 74578178c1b7779c889cd67a3b4ca71912b343d9 Mon Sep 17 00:00:00 2001 From: Giuseppe CAVALLARO Date: Mon, 10 Oct 2011 21:37:56 +0000 Subject: [PATCH] --- yaml --- r: 266842 b: refs/heads/master c: a4886d522e18e5d4a63b95a5ead72f6105e3ef98 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/net/phy/icplus.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index 7f18221690e0..6a003e03c2f5 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2425717b27eb92b175335ca4ff0bb218cbe0cb64 +refs/heads/master: a4886d522e18e5d4a63b95a5ead72f6105e3ef98 diff --git a/trunk/drivers/net/phy/icplus.c b/trunk/drivers/net/phy/icplus.c index d66bd8d12599..c81f136ae670 100644 --- a/trunk/drivers/net/phy/icplus.c +++ b/trunk/drivers/net/phy/icplus.c @@ -128,12 +128,15 @@ static int ip1001_config_init(struct phy_device *phydev) if (c < 0) return c; - /* Additional delay (2ns) used to adjust RX clock phase - * at GMII/ RGMII interface */ - c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); - c |= IP1001_PHASE_SEL_MASK; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII) { + /* Additional delay (2ns) used to adjust RX clock phase + * at RGMII interface */ + c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS); + c |= IP1001_PHASE_SEL_MASK; + c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); + } - return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); + return c; } static int ip101a_config_init(struct phy_device *phydev)