From 74f3cfb1b73d3473baa54c2504c0c16456773e83 Mon Sep 17 00:00:00 2001 From: Catalin Marinas Date: Wed, 1 Apr 2009 13:53:48 +0100 Subject: [PATCH] --- yaml --- r: 139884 b: refs/heads/master c: fe68e68f6a379d317a87ae24de050a65b11ea1fb h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/abort-ev6.S | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index dc8e4db6f0de..c1500abc8be1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 01a24d2b9309676ec2e7069cd19f5b1c4a1505e0 +refs/heads/master: fe68e68f6a379d317a87ae24de050a65b11ea1fb diff --git a/trunk/arch/arm/mm/abort-ev6.S b/trunk/arch/arm/mm/abort-ev6.S index 94077fbd96b7..6f7e70907e44 100644 --- a/trunk/arch/arm/mm/abort-ev6.S +++ b/trunk/arch/arm/mm/abort-ev6.S @@ -29,10 +29,10 @@ ENTRY(v6_early_abort) mrc p15, 0, r1, c5, c0, 0 @ get FSR mrc p15, 0, r0, c6, c0, 0 @ get FAR /* - * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR. + * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103). * The test below covers all the write situations, including Java bytecodes */ - bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR + bic r1, r1, #1 << 11 @ clear bit 11 of FSR tst r3, #PSR_J_BIT @ Java? movne pc, lr do_thumb_abort