From 75f5c5df0d2da8b196d3031d9a65fc92edcf9116 Mon Sep 17 00:00:00 2001 From: Maarten ter Huurne Date: Fri, 30 Mar 2012 16:18:57 +0200 Subject: [PATCH] --- yaml --- r: 319639 b: refs/heads/master c: ea3952e01c47ac76d71857099cbfc2f487f507d2 h: refs/heads/master i: 319637: 6c27c712333a34729190137a0058cd19f79b7d90 319635: 3e41b6cdbb17655c0f0936b8d6bd482e6caf2eae 319631: 7ff6c5e3147d97785a88a126e47321184705faf8 v: v3 --- [refs] | 2 +- trunk/arch/mips/jz4740/reset.c | 49 ++++++++++++++++++++++++++++++---- 2 files changed, 45 insertions(+), 6 deletions(-) diff --git a/[refs] b/[refs] index f40a078aea1e..1c000aa77ec8 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 56635d79932c805f6eb2a775ad1cdf9ace12c2b5 +refs/heads/master: ea3952e01c47ac76d71857099cbfc2f487f507d2 diff --git a/trunk/arch/mips/jz4740/reset.c b/trunk/arch/mips/jz4740/reset.c index 5f1fb95c0d0d..6c0da5afcf17 100644 --- a/trunk/arch/mips/jz4740/reset.c +++ b/trunk/arch/mips/jz4740/reset.c @@ -21,6 +21,9 @@ #include #include +#include "reset.h" +#include "clock.h" + static void jz4740_halt(void) { while (1) { @@ -53,21 +56,57 @@ static void jz4740_restart(char *command) jz4740_halt(); } -#define JZ_REG_RTC_CTRL 0x00 -#define JZ_REG_RTC_HIBERNATE 0x20 +#define JZ_REG_RTC_CTRL 0x00 +#define JZ_REG_RTC_HIBERNATE 0x20 +#define JZ_REG_RTC_WAKEUP_FILTER 0x24 +#define JZ_REG_RTC_RESET_COUNTER 0x28 -#define JZ_RTC_CTRL_WRDY BIT(7) +#define JZ_RTC_CTRL_WRDY BIT(7) +#define JZ_RTC_WAKEUP_FILTER_MASK 0x0000FFE0 +#define JZ_RTC_RESET_COUNTER_MASK 0x00000FE0 -static void jz4740_power_off(void) +static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base) { - void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24); uint32_t ctrl; do { ctrl = readl(rtc_base + JZ_REG_RTC_CTRL); } while (!(ctrl & JZ_RTC_CTRL_WRDY)); +} +static void jz4740_power_off(void) +{ + void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38); + unsigned long wakeup_filter_ticks; + unsigned long reset_counter_ticks; + + /* + * Set minimum wakeup pin assertion time: 100 ms. + * Range is 0 to 2 sec if RTC is clocked at 32 kHz. + */ + wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000; + if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK) + wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK; + else + wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK; + jz4740_rtc_wait_ready(rtc_base); + writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER); + + /* + * Set reset pin low-level assertion time after wakeup: 60 ms. + * Range is 0 to 125 ms if RTC is clocked at 32 kHz. + */ + reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000; + if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK) + reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK; + else + reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK; + jz4740_rtc_wait_ready(rtc_base); + writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER); + + jz4740_rtc_wait_ready(rtc_base); writel(1, rtc_base + JZ_REG_RTC_HIBERNATE); + jz4740_halt(); }