From 77cedb1b190277102fc99292113d36a1c8f6b56d Mon Sep 17 00:00:00 2001
From: Laxman Dewangan <ldewangan@nvidia.com>
Date: Tue, 29 Jan 2013 18:26:20 +0530
Subject: [PATCH] --- yaml --- r: 355596 b: refs/heads/master c:
 031b77afc374cf1b86dbcda5dfa6e1bbb989836c h: refs/heads/master v: v3

---
 [refs]                                | 2 +-
 trunk/arch/arm/boot/dts/tegra114.dtsi | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 86d452214cf5..862b6e2794ee 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: b16f9183c7c1918a3a5c36d35482f5e01dc9c384
+refs/heads/master: 031b77afc374cf1b86dbcda5dfa6e1bbb989836c
diff --git a/trunk/arch/arm/boot/dts/tegra114.dtsi b/trunk/arch/arm/boot/dts/tegra114.dtsi
index 8f7ea189f6df..1dfaf2874c57 100644
--- a/trunk/arch/arm/boot/dts/tegra114.dtsi
+++ b/trunk/arch/arm/boot/dts/tegra114.dtsi
@@ -54,6 +54,12 @@
 		interrupt-controller;
 	};
 
+	pinmux: pinmux {
+		compatible = "nvidia,tegra114-pinmux";
+		reg = <0x70000868 0x148		/* Pad control registers */
+		       0x70003000 0x40c>;	/* Mux registers */
+	};
+
 	serial@70006000 {
 		compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 		reg = <0x70006000 0x40>;