From 791f165a59f194d79eec24431bc1f0e218bc5178 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 18 May 2006 12:38:47 +0100 Subject: [PATCH] --- yaml --- r: 27658 b: refs/heads/master c: b0b0e13e7dd309be13ab9324e67893e62b136e44 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/mips/mips-boards/malta/malta_smp.c | 19 ----------------- trunk/arch/mips/mips-boards/sim/sim_smp.c | 21 ------------------- 3 files changed, 1 insertion(+), 41 deletions(-) diff --git a/[refs] b/[refs] index a2d2e02e7c2f..0b04dabad9b7 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c583122c26ad04bb2379933dc5acc8b9479d6c67 +refs/heads/master: b0b0e13e7dd309be13ab9324e67893e62b136e44 diff --git a/trunk/arch/mips/mips-boards/malta/malta_smp.c b/trunk/arch/mips/mips-boards/malta/malta_smp.c index 6c6c8eeedbce..cf967170fe29 100644 --- a/trunk/arch/mips/mips-boards/malta/malta_smp.c +++ b/trunk/arch/mips/mips-boards/malta/malta_smp.c @@ -33,25 +33,6 @@ void core_send_ipi(int cpu, unsigned int action) #endif /* CONFIG_MIPS_MT_SMTC */ } -/* - * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map - */ - -void __init prom_build_cpu_map(void) -{ - int nextslot; - - /* - * As of November, 2004, MIPSsim only simulates one core - * at a time. However, that core may be a MIPS MT core - * with multiple virtual processors and thread contexts. - */ - - if (read_c0_config3() & (1<<2)) { - nextslot = mipsmt_build_cpu_map(1); - } -} - /* * Platform "CPU" startup hook */ diff --git a/trunk/arch/mips/mips-boards/sim/sim_smp.c b/trunk/arch/mips/mips-boards/sim/sim_smp.c index b7084e7c4bf9..004070956cca 100644 --- a/trunk/arch/mips/mips-boards/sim/sim_smp.c +++ b/trunk/arch/mips/mips-boards/sim/sim_smp.c @@ -50,27 +50,6 @@ void core_send_ipi(int cpu, unsigned int action) } -/* - * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map - */ - -void __init prom_build_cpu_map(void) -{ -#ifdef CONFIG_MIPS_MT_SMTC - int nextslot; - - /* - * As of November, 2004, MIPSsim only simulates one core - * at a time. However, that core may be a MIPS MT core - * with multiple virtual processors and thread contexts. - */ - - if (read_c0_config3() & (1<<2)) { - nextslot = mipsmt_build_cpu_map(1); - } -#endif /* CONFIG_MIPS_MT_SMTC */ -} - /* * Platform "CPU" startup hook */