From 79545f4431a411ed2258a24bfa626d32ee3fa8cc Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 18 Nov 2011 00:28:29 +0800 Subject: [PATCH] --- yaml --- r: 286866 b: refs/heads/master c: 6522ecdcfaae90ad1d2dd868fbdf3a2ddfc5f257 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 8002f7be2605..fcaec797bc40 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8134ff55646bd2c059ddfd0d479882a06d6ef09a +refs/heads/master: 6522ecdcfaae90ad1d2dd868fbdf3a2ddfc5f257 diff --git a/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h index 976f4a6c3353..d21932dcd6fa 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h @@ -16,7 +16,7 @@ #define AT91CAP9_DDRSDR_H #define AT91_DDRSDRC_MR 0x00 /* Mode Register */ -#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */ +#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */ #define AT91_DDRSDRC_MODE_NORMAL 0 #define AT91_DDRSDRC_MODE_NOP 1 #define AT91_DDRSDRC_MODE_PRECHARGE 2 @@ -42,6 +42,7 @@ #define AT91_DDRSDRC_NR_11 (0 << 2) #define AT91_DDRSDRC_NR_12 (1 << 2) #define AT91_DDRSDRC_NR_13 (2 << 2) +#define AT91_DDRSDRC_NR_14 (3 << 2) #define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */ #define AT91_DDRSDRC_CAS_2 (2 << 4) #define AT91_DDRSDRC_CAS_3 (3 << 4) @@ -86,6 +87,9 @@ #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 #define AT91_DDRSDRC_MD_DDR 2 #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 +#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ +#define AT91_DDRSDRC_DBW_32BITS (0 << 4) +#define AT91_DDRSDRC_DBW_16BITS (1 << 4) #define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */ #define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */