diff --git a/[refs] b/[refs] index 5ba0737131e3..d1eadb754157 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c9477f38cba225870862fd9e08868ae3d4abdfe0 +refs/heads/master: 986afc98ce24901865828dab9ba876fd9be6beb2 diff --git a/trunk/Documentation/ABI/testing/sysfs-class-scsi_host b/trunk/Documentation/ABI/testing/sysfs-class-scsi_host deleted file mode 100644 index 29a4f892e433..000000000000 --- a/trunk/Documentation/ABI/testing/sysfs-class-scsi_host +++ /dev/null @@ -1,13 +0,0 @@ -What: /sys/class/scsi_host/hostX/isci_id -Date: June 2011 -Contact: Dave Jiang -Description: - This file contains the enumerated host ID for the Intel - SCU controller. The Intel(R) C600 Series Chipset SATA/SAS - Storage Control Unit embeds up to two 4-port controllers in - a single PCI device. The controllers are enumerated in order - which usually means the lowest number scsi_host corresponds - with the first controller, but this association is not - guaranteed. The 'isci_id' attribute unambiguously identifies - the controller index: '0' for the first controller, - '1' for the second. diff --git a/trunk/Documentation/cgroups/memory.txt b/trunk/Documentation/cgroups/memory.txt index 06eb6d957c83..6f3c598971fc 100644 --- a/trunk/Documentation/cgroups/memory.txt +++ b/trunk/Documentation/cgroups/memory.txt @@ -380,7 +380,7 @@ will be charged as a new owner of it. 5.2 stat file -memory.stat file includes following statistics +5.2.1 memory.stat file includes following statistics # per-memory cgroup local status cache - # of bytes of page cache memory. @@ -438,6 +438,89 @@ Note: file_mapped is accounted only when the memory cgroup is owner of page cache.) +5.2.2 memory.vmscan_stat + +memory.vmscan_stat includes statistics information for memory scanning and +freeing, reclaiming. The statistics shows memory scanning information since +memory cgroup creation and can be reset to 0 by writing 0 as + + #echo 0 > ../memory.vmscan_stat + +This file contains following statistics. + +[param]_[file_or_anon]_pages_by_[reason]_[under_heararchy] +[param]_elapsed_ns_by_[reason]_[under_hierarchy] + +For example, + + scanned_file_pages_by_limit indicates the number of scanned + file pages at vmscan. + +Now, 3 parameters are supported + + scanned - the number of pages scanned by vmscan + rotated - the number of pages activated at vmscan + freed - the number of pages freed by vmscan + +If "rotated" is high against scanned/freed, the memcg seems busy. + +Now, 2 reason are supported + + limit - the memory cgroup's limit + system - global memory pressure + softlimit + (global memory pressure not under softlimit is not handled now) + +When under_hierarchy is added in the tail, the number indicates the +total memcg scan of its children and itself. + +elapsed_ns is a elapsed time in nanosecond. This may include sleep time +and not indicates CPU usage. So, please take this as just showing +latency. + +Here is an example. + +# cat /cgroup/memory/A/memory.vmscan_stat +scanned_pages_by_limit 9471864 +scanned_anon_pages_by_limit 6640629 +scanned_file_pages_by_limit 2831235 +rotated_pages_by_limit 4243974 +rotated_anon_pages_by_limit 3971968 +rotated_file_pages_by_limit 272006 +freed_pages_by_limit 2318492 +freed_anon_pages_by_limit 962052 +freed_file_pages_by_limit 1356440 +elapsed_ns_by_limit 351386416101 +scanned_pages_by_system 0 +scanned_anon_pages_by_system 0 +scanned_file_pages_by_system 0 +rotated_pages_by_system 0 +rotated_anon_pages_by_system 0 +rotated_file_pages_by_system 0 +freed_pages_by_system 0 +freed_anon_pages_by_system 0 +freed_file_pages_by_system 0 +elapsed_ns_by_system 0 +scanned_pages_by_limit_under_hierarchy 9471864 +scanned_anon_pages_by_limit_under_hierarchy 6640629 +scanned_file_pages_by_limit_under_hierarchy 2831235 +rotated_pages_by_limit_under_hierarchy 4243974 +rotated_anon_pages_by_limit_under_hierarchy 3971968 +rotated_file_pages_by_limit_under_hierarchy 272006 +freed_pages_by_limit_under_hierarchy 2318492 +freed_anon_pages_by_limit_under_hierarchy 962052 +freed_file_pages_by_limit_under_hierarchy 1356440 +elapsed_ns_by_limit_under_hierarchy 351386416101 +scanned_pages_by_system_under_hierarchy 0 +scanned_anon_pages_by_system_under_hierarchy 0 +scanned_file_pages_by_system_under_hierarchy 0 +rotated_pages_by_system_under_hierarchy 0 +rotated_anon_pages_by_system_under_hierarchy 0 +rotated_file_pages_by_system_under_hierarchy 0 +freed_pages_by_system_under_hierarchy 0 +freed_anon_pages_by_system_under_hierarchy 0 +freed_file_pages_by_system_under_hierarchy 0 +elapsed_ns_by_system_under_hierarchy 0 + 5.3 swappiness Similar to /proc/sys/vm/swappiness, but affecting a hierarchy of groups only. diff --git a/trunk/Documentation/hwmon/coretemp b/trunk/Documentation/hwmon/coretemp index 84d46c0c71a3..fa8776ab9b18 100644 --- a/trunk/Documentation/hwmon/coretemp +++ b/trunk/Documentation/hwmon/coretemp @@ -35,6 +35,13 @@ the Out-Of-Spec bit. Following table summarizes the exported sysfs files: All Sysfs entries are named with their core_id (represented here by 'X'). tempX_input - Core temperature (in millidegrees Celsius). tempX_max - All cooling devices should be turned on (on Core2). + Initialized with IA32_THERM_INTERRUPT. When the CPU + temperature reaches this temperature, an interrupt is + generated and tempX_max_alarm is set. +tempX_max_hyst - If the CPU temperature falls below than temperature, + an interrupt is generated and tempX_max_alarm is reset. +tempX_max_alarm - Set if the temperature reaches or exceeds tempX_max. + Reset if the temperature drops to or below tempX_max_hyst. tempX_crit - Maximum junction temperature (in millidegrees Celsius). tempX_crit_alarm - Set when Out-of-spec bit is set, never clears. Correct CPU operation is no longer guaranteed. @@ -42,10 +49,9 @@ tempX_label - Contains string "Core X", where X is processor number. For Package temp, this will be "Physical id Y", where Y is the package number. -On CPU models which support it, TjMax is read from a model-specific register. -On other models, it is set to an arbitrary value based on weak heuristics. -If these heuristics don't work for you, you can pass the correct TjMax value -as a module parameter (tjmax). +The TjMax temperature is set to 85 degrees C if undocumented model specific +register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as +(sometimes) documented in processor datasheet. Appendix A. Known TjMax lists (TBD): Some information comes from ark.intel.com diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index 854ed5ca7e3f..614d0382e2cb 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -2086,12 +2086,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. Override pmtimer IOPort with a hex value. e.g. pmtmr=0x508 - pnp.debug=1 [PNP] - Enable PNP debug messages (depends on the - CONFIG_PNP_DEBUG_MESSAGES option). Change at run-time - via /sys/module/pnp/parameters/debug. We always show - current resource usage; turning this on also shows - possible settings and some assignment information. + pnp.debug [PNP] + Enable PNP debug messages. This depends on the + CONFIG_PNP_DEBUG_MESSAGES option. pnpacpi= [ACPI] { off } diff --git a/trunk/Documentation/networking/dmfe.txt b/trunk/Documentation/networking/dmfe.txt index 25320bf19c86..8006c227fda2 100644 --- a/trunk/Documentation/networking/dmfe.txt +++ b/trunk/Documentation/networking/dmfe.txt @@ -1,5 +1,3 @@ -Note: This driver doesn't have a maintainer. - Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver for Linux. This program is free software; you can redistribute it and/or @@ -57,6 +55,7 @@ Test and make sure PCI latency is now correct for all cases. Authors: Sten Wang : Original Author +Tobias Ringstrom : Current Maintainer Contributors: diff --git a/trunk/Documentation/vm/transhuge.txt b/trunk/Documentation/vm/transhuge.txt index 29bdf62aac09..0924aaca3302 100644 --- a/trunk/Documentation/vm/transhuge.txt +++ b/trunk/Documentation/vm/transhuge.txt @@ -123,11 +123,10 @@ be automatically shutdown if it's set to "never". khugepaged runs usually at low frequency so while one may not want to invoke defrag algorithms synchronously during the page faults, it should be worth invoking defrag at least in khugepaged. However it's -also possible to disable defrag in khugepaged by writing 0 or enable -defrag in khugepaged by writing 1: +also possible to disable defrag in khugepaged: -echo 0 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag -echo 1 >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag +echo yes >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag +echo no >/sys/kernel/mm/transparent_hugepage/khugepaged/defrag You can also control how many pages khugepaged should scan at each pass: diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index ae8820e173a2..28f65c249b97 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -1278,6 +1278,7 @@ F: drivers/input/misc/ati_remote2.c ATLX ETHERNET DRIVERS M: Jay Cliburn M: Chris Snook +M: Jie Yang L: netdev@vger.kernel.org W: http://sourceforge.net/projects/atl1 W: http://atl1.sourceforge.net @@ -1573,6 +1574,7 @@ F: drivers/scsi/bfa/ BROCADE BNA 10 GIGABIT ETHERNET DRIVER M: Rasesh Mody +M: Debashis Dutt L: netdev@vger.kernel.org S: Supported F: drivers/net/bna/ @@ -1756,6 +1758,7 @@ F: Documentation/zh_CN/ CISCO VIC ETHERNET NIC DRIVER M: Christian Benvenuti +M: Vasanthy Kolluri M: Roopa Prabhu M: David Wang S: Supported @@ -3259,17 +3262,6 @@ F: Documentation/input/multi-touch-protocol.txt F: drivers/input/input-mt.c K: \b(ABS|SYN)_MT_ -INTEL C600 SERIES SAS CONTROLLER DRIVER -M: Intel SCU Linux support -M: Dan Williams -M: Dave Jiang -M: Ed Nadolski -L: linux-scsi@vger.kernel.org -T: git git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git -S: Maintained -F: drivers/scsi/isci/ -F: firmware/isci/ - INTEL IDLE DRIVER M: Len Brown L: linux-pm@lists.linux-foundation.org @@ -4412,8 +4404,7 @@ L: netfilter@vger.kernel.org L: coreteam@netfilter.org W: http://www.netfilter.org/ W: http://www.iptables.org/ -T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-2.6.git -T: git git://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next-2.6.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/kaber/nf-2.6.git S: Supported F: include/linux/netfilter* F: include/linux/netfilter/ @@ -4783,7 +4774,7 @@ F: drivers/net/wireless/orinoco/ OSD LIBRARY and FILESYSTEM M: Boaz Harrosh -M: Benny Halevy +M: Benny Halevy L: osd-dev@open-osd.org W: http://open-osd.org T: git git://git.open-osd.org/open-osd.git @@ -7209,9 +7200,6 @@ W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices S: Supported F: Documentation/hwmon/wm83?? F: drivers/leds/leds-wm83*.c -F: drivers/input/misc/wm831x-on.c -F: drivers/input/touchscreen/wm831x-ts.c -F: drivers/input/touchscreen/wm97*.c F: drivers/mfd/wm8*.c F: drivers/power/wm83*.c F: drivers/rtc/rtc-wm83*.c @@ -7221,7 +7209,6 @@ F: drivers/watchdog/wm83*_wdt.c F: include/linux/mfd/wm831x/ F: include/linux/mfd/wm8350/ F: include/linux/mfd/wm8400* -F: include/linux/wm97xx.h F: include/sound/wm????.h F: sound/soc/codecs/wm* diff --git a/trunk/Makefile b/trunk/Makefile index 73bb458ecfd3..522fa4784e69 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 1 SUBLEVEL = 0 -EXTRAVERSION = -rc8 +EXTRAVERSION = -rc6 NAME = "Divemaster Edition" # *DOCUMENTATION* diff --git a/trunk/arch/alpha/Kconfig b/trunk/arch/alpha/Kconfig index 8bb936226dee..60cde53d266c 100644 --- a/trunk/arch/alpha/Kconfig +++ b/trunk/arch/alpha/Kconfig @@ -51,7 +51,7 @@ config GENERIC_CMOS_UPDATE def_bool y config GENERIC_GPIO - bool + def_bool y config ZONE_DMA bool diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 3146ed3f6eca..3269576dbfa8 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -1283,20 +1283,6 @@ config ARM_ERRATA_364296 processor into full low interrupt latency mode. ARM11MPCore is not affected. -config ARM_ERRATA_764369 - bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" - depends on CPU_V7 && SMP - help - This option enables the workaround for erratum 764369 - affecting Cortex-A9 MPCore with two or more processors (all - current revisions). Under certain timing circumstances, a data - cache line maintenance operation by MVA targeting an Inner - Shareable memory region may fail to proceed up to either the - Point of Coherency or to the Point of Unification of the - system. This workaround adds a DSB instruction before the - relevant cache maintenance functions and sets a specific bit - in the diagnostic control register of the SCU. - endmenu source "arch/arm/common/Kconfig" diff --git a/trunk/arch/arm/boot/dts/tegra-harmony.dts b/trunk/arch/arm/boot/dts/tegra-harmony.dts index e5818668d091..4c053340ce33 100644 --- a/trunk/arch/arm/boot/dts/tegra-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra-harmony.dts @@ -57,14 +57,14 @@ }; sdhci@c8000200 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 155 0>; /* gpio PT3 */ + gpios = <&gpio 69 0>, /* cd, gpio PI5 */ + <&gpio 57 0>, /* wp, gpio PH1 */ + <&gpio 155 0>; /* power, gpio PT3 */ }; sdhci@c8000600 { - cd-gpios = <&gpio 58 0>; /* gpio PH2 */ - wp-gpios = <&gpio 59 0>; /* gpio PH3 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ + gpios = <&gpio 58 0>, /* cd, gpio PH2 */ + <&gpio 59 0>, /* wp, gpio PH3 */ + <&gpio 70 0>; /* power, gpio PI6 */ }; }; diff --git a/trunk/arch/arm/boot/dts/tegra-seaboard.dts b/trunk/arch/arm/boot/dts/tegra-seaboard.dts index 64cedca6fc79..1940cae00748 100644 --- a/trunk/arch/arm/boot/dts/tegra-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra-seaboard.dts @@ -21,8 +21,8 @@ }; sdhci@c8000400 { - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ - wp-gpios = <&gpio 57 0>; /* gpio PH1 */ - power-gpios = <&gpio 70 0>; /* gpio PI6 */ + gpios = <&gpio 69 0>, /* cd, gpio PI5 */ + <&gpio 57 0>, /* wp, gpio PH1 */ + <&gpio 70 0>; /* power, gpio PI6 */ }; }; diff --git a/trunk/arch/arm/configs/exynos4_defconfig b/trunk/arch/arm/configs/exynos4_defconfig index cd40bb56e568..da53ff3b4d70 100644 --- a/trunk/arch/arm/configs/exynos4_defconfig +++ b/trunk/arch/arm/configs/exynos4_defconfig @@ -11,7 +11,6 @@ CONFIG_MACH_SMDKV310=y CONFIG_MACH_ARMLEX4210=y CONFIG_MACH_UNIVERSAL_C210=y CONFIG_MACH_NURI=y -CONFIG_MACH_ORIGEN=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_SMP=y diff --git a/trunk/arch/arm/include/asm/futex.h b/trunk/arch/arm/include/asm/futex.h index 253cc86318bf..8c73900da9ed 100644 --- a/trunk/arch/arm/include/asm/futex.h +++ b/trunk/arch/arm/include/asm/futex.h @@ -25,17 +25,17 @@ #ifdef CONFIG_SMP -#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ smp_mb(); \ __asm__ __volatile__( \ - "1: ldrex %1, [%3]\n" \ + "1: ldrex %1, [%2]\n" \ " " insn "\n" \ - "2: strex %2, %0, [%3]\n" \ - " teq %2, #0\n" \ + "2: strex %1, %0, [%2]\n" \ + " teq %1, #0\n" \ " bne 1b\n" \ " mov %0, #0\n" \ - __futex_atomic_ex_table("%5") \ - : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ + __futex_atomic_ex_table("%4") \ + : "=&r" (ret), "=&r" (oldval) \ : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ : "cc", "memory") @@ -73,14 +73,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, #include #include -#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \ +#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ __asm__ __volatile__( \ - "1: " T(ldr) " %1, [%3]\n" \ + "1: " T(ldr) " %1, [%2]\n" \ " " insn "\n" \ - "2: " T(str) " %0, [%3]\n" \ + "2: " T(str) " %0, [%2]\n" \ " mov %0, #0\n" \ - __futex_atomic_ex_table("%5") \ - : "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \ + __futex_atomic_ex_table("%4") \ + : "=&r" (ret), "=&r" (oldval) \ : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \ : "cc", "memory") @@ -117,7 +117,7 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) int cmp = (encoded_op >> 24) & 15; int oparg = (encoded_op << 8) >> 20; int cmparg = (encoded_op << 20) >> 20; - int oldval = 0, ret, tmp; + int oldval = 0, ret; if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) oparg = 1 << oparg; @@ -129,19 +129,19 @@ futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) switch (op) { case FUTEX_OP_SET: - __futex_atomic_op("mov %0, %4", ret, oldval, tmp, uaddr, oparg); + __futex_atomic_op("mov %0, %3", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ADD: - __futex_atomic_op("add %0, %1, %4", ret, oldval, tmp, uaddr, oparg); + __futex_atomic_op("add %0, %1, %3", ret, oldval, uaddr, oparg); break; case FUTEX_OP_OR: - __futex_atomic_op("orr %0, %1, %4", ret, oldval, tmp, uaddr, oparg); + __futex_atomic_op("orr %0, %1, %3", ret, oldval, uaddr, oparg); break; case FUTEX_OP_ANDN: - __futex_atomic_op("and %0, %1, %4", ret, oldval, tmp, uaddr, ~oparg); + __futex_atomic_op("and %0, %1, %3", ret, oldval, uaddr, ~oparg); break; case FUTEX_OP_XOR: - __futex_atomic_op("eor %0, %1, %4", ret, oldval, tmp, uaddr, oparg); + __futex_atomic_op("eor %0, %1, %3", ret, oldval, uaddr, oparg); break; default: ret = -ENOSYS; diff --git a/trunk/arch/arm/include/asm/unistd.h b/trunk/arch/arm/include/asm/unistd.h index c60a2944f95b..2c04ed5efeb5 100644 --- a/trunk/arch/arm/include/asm/unistd.h +++ b/trunk/arch/arm/include/asm/unistd.h @@ -478,8 +478,8 @@ /* * Unimplemented (or alternatively implemented) syscalls */ -#define __IGNORE_fadvise64_64 -#define __IGNORE_migrate_pages +#define __IGNORE_fadvise64_64 1 +#define __IGNORE_migrate_pages 1 #endif /* __KERNEL__ */ #endif /* __ASM_ARM_UNISTD_H */ diff --git a/trunk/arch/arm/kernel/smp_scu.c b/trunk/arch/arm/kernel/smp_scu.c index 7fcddb75c877..79ed5e7f204a 100644 --- a/trunk/arch/arm/kernel/smp_scu.c +++ b/trunk/arch/arm/kernel/smp_scu.c @@ -13,7 +13,6 @@ #include #include -#include #define SCU_CTRL 0x00 #define SCU_CONFIG 0x04 @@ -38,15 +37,6 @@ void __init scu_enable(void __iomem *scu_base) { u32 scu_ctrl; -#ifdef CONFIG_ARM_ERRATA_764369 - /* Cortex-A9 only */ - if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) { - scu_ctrl = __raw_readl(scu_base + 0x30); - if (!(scu_ctrl & 1)) - __raw_writel(scu_ctrl | 0x1, scu_base + 0x30); - } -#endif - scu_ctrl = __raw_readl(scu_base + SCU_CTRL); /* already enabled? */ if (scu_ctrl & 1) diff --git a/trunk/arch/arm/kernel/vmlinux.lds.S b/trunk/arch/arm/kernel/vmlinux.lds.S index 4e66f62b8d41..bf977f8514f6 100644 --- a/trunk/arch/arm/kernel/vmlinux.lds.S +++ b/trunk/arch/arm/kernel/vmlinux.lds.S @@ -23,10 +23,8 @@ #if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK) #define ARM_EXIT_KEEP(x) x -#define ARM_EXIT_DISCARD(x) #else #define ARM_EXIT_KEEP(x) -#define ARM_EXIT_DISCARD(x) x #endif OUTPUT_ARCH(arm) @@ -41,11 +39,6 @@ jiffies = jiffies_64 + 4; SECTIONS { /* - * XXX: The linker does not define how output sections are - * assigned to input sections when there are multiple statements - * matching the same input section name. There is no documented - * order of matching. - * * unwind exit sections must be discarded before the rest of the * unwind sections get included. */ @@ -54,9 +47,6 @@ SECTIONS *(.ARM.extab.exit.text) ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text)) ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text)) - ARM_EXIT_DISCARD(EXIT_TEXT) - ARM_EXIT_DISCARD(EXIT_DATA) - EXIT_CALL #ifndef CONFIG_HOTPLUG *(.ARM.exidx.devexit.text) *(.ARM.extab.devexit.text) @@ -68,8 +58,6 @@ SECTIONS #ifndef CONFIG_SMP_ON_UP *(.alt.smp.init) #endif - *(.discard) - *(.discard.*) } #ifdef CONFIG_XIP_KERNEL @@ -291,6 +279,9 @@ SECTIONS STABS_DEBUG .comment 0 : { *(.comment) } + + /* Default discards */ + DISCARDS } /* diff --git a/trunk/arch/arm/mach-dove/common.c b/trunk/arch/arm/mach-dove/common.c index a9e0dae86a26..83dce859886d 100644 --- a/trunk/arch/arm/mach-dove/common.c +++ b/trunk/arch/arm/mach-dove/common.c @@ -158,7 +158,7 @@ void __init dove_spi0_init(void) void __init dove_spi1_init(void) { - orion_spi_1_init(DOVE_SPI1_PHYS_BASE, get_tclk()); + orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk()); } /***************************************************************************** diff --git a/trunk/arch/arm/mach-exynos4/Kconfig b/trunk/arch/arm/mach-exynos4/Kconfig index c595bb03f417..0c77ab99fa16 100644 --- a/trunk/arch/arm/mach-exynos4/Kconfig +++ b/trunk/arch/arm/mach-exynos4/Kconfig @@ -15,11 +15,6 @@ config CPU_EXYNOS4210 help Enable EXYNOS4210 CPU support -config SOC_EXYNOS4212 - bool - help - Enable EXYNOS4212 SoC support - config EXYNOS4_MCT bool default y @@ -116,11 +111,24 @@ config EXYNOS4_SETUP_USB_PHY menu "EXYNOS4 Machines" -comment "EXYNOS4210 Boards" - config MACH_SMDKC210 bool "SMDKC210" - select MACH_SMDKV310 + select CPU_EXYNOS4210 + select S5P_DEV_FIMD0 + select S3C_DEV_RTC + select S3C_DEV_WDT + select S3C_DEV_I2C1 + select S3C_DEV_HSMMC + select S3C_DEV_HSMMC1 + select S3C_DEV_HSMMC2 + select S3C_DEV_HSMMC3 + select SAMSUNG_DEV_PWM + select SAMSUNG_DEV_BACKLIGHT + select EXYNOS4_DEV_PD + select EXYNOS4_DEV_SYSMMU + select EXYNOS4_SETUP_FIMD0 + select EXYNOS4_SETUP_I2C1 + select EXYNOS4_SETUP_SDHCI help Machine support for Samsung SMDKC210 @@ -210,39 +218,6 @@ config MACH_NURI help Machine support for Samsung Mobile NURI Board. -config MACH_ORIGEN - bool "ORIGEN" - select CPU_EXYNOS4210 - select S3C_DEV_RTC - select S3C_DEV_WDT - select S3C_DEV_HSMMC2 - select EXYNOS4_SETUP_SDHCI - help - Machine support for ORIGEN based on Samsung EXYNOS4210 - -comment "EXYNOS4212 Boards" - -config MACH_SMDK4212 - bool "SMDK4212" - select SOC_EXYNOS4212 - select S3C_DEV_HSMMC2 - select S3C_DEV_HSMMC3 - select S3C_DEV_I2C1 - select S3C_DEV_I2C3 - select S3C_DEV_I2C7 - select S3C_DEV_RTC - select S3C_DEV_WDT - select SAMSUNG_DEV_BACKLIGHT - select SAMSUNG_DEV_KEYPAD - select SAMSUNG_DEV_PWM - select EXYNOS4_SETUP_I2C1 - select EXYNOS4_SETUP_I2C3 - select EXYNOS4_SETUP_I2C7 - select EXYNOS4_SETUP_KEYPAD - select EXYNOS4_SETUP_SDHCI - help - Machine support for Samsung SMDK4212 - endmenu comment "Configuration for HSMMC bus width" diff --git a/trunk/arch/arm/mach-exynos4/Makefile b/trunk/arch/arm/mach-exynos4/Makefile index e19cd12d264e..b7fe1d7b0b1f 100644 --- a/trunk/arch/arm/mach-exynos4/Makefile +++ b/trunk/arch/arm/mach-exynos4/Makefile @@ -12,10 +12,8 @@ obj- := # Core support for EXYNOS4 system -obj-$(CONFIG_ARCH_EXYNOS4) += cpu.o init.o clock.o irq-combiner.o -obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o irq-eint.o dma.o pmu.o -obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o -obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o +obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o +obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o obj-$(CONFIG_PM) += pm.o sleep.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o @@ -27,14 +25,11 @@ obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o # machine support -obj-$(CONFIG_MACH_SMDKC210) += mach-smdkv310.o +obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o obj-$(CONFIG_MACH_NURI) += mach-nuri.o -obj-$(CONFIG_MACH_ORIGEN) += mach-origen.o - -obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4212.o # device support diff --git a/trunk/arch/arm/mach-exynos4/clock-exynos4210.c b/trunk/arch/arm/mach-exynos4/clock-exynos4210.c deleted file mode 100644 index b9d5ef670eb4..000000000000 --- a/trunk/arch/arm/mach-exynos4/clock-exynos4210.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/clock-exynos4210.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4210 - Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static struct sleep_save exynos4210_clock_save[] = { - SAVE_ITEM(S5P_CLKSRC_IMAGE), - SAVE_ITEM(S5P_CLKSRC_LCD1), - SAVE_ITEM(S5P_CLKDIV_IMAGE), - SAVE_ITEM(S5P_CLKDIV_LCD1), - SAVE_ITEM(S5P_CLKSRC_MASK_LCD1), - SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4210), - SAVE_ITEM(S5P_CLKGATE_IP_LCD1), - SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4210), -}; - -static struct clksrc_clk *sysclks[] = { - /* nothing here yet */ -}; - -static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); -} - -static struct clksrc_clk clksrcs[] = { - { - .clk = { - .name = "sclk_sata", - .id = -1, - .enable = exynos4_clksrc_mask_fsys_ctrl, - .ctrlbit = (1 << 24), - }, - .sources = &clkset_mout_corebus, - .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, - .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, - }, { - .clk = { - .name = "sclk_fimd", - .devname = "exynos4-fb.1", - .enable = exynos4_clksrc_mask_lcd1_ctrl, - .ctrlbit = (1 << 0), - }, - .sources = &clkset_group, - .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, - .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, - }, -}; - -static struct clk init_clocks_off[] = { - { - .name = "sataphy", - .id = -1, - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 3), - }, { - .name = "sata", - .id = -1, - .parent = &clk_aclk_133.clk, - .enable = exynos4_clk_ip_fsys_ctrl, - .ctrlbit = (1 << 10), - }, { - .name = "fimd", - .devname = "exynos4-fb.1", - .enable = exynos4_clk_ip_lcd1_ctrl, - .ctrlbit = (1 << 0), - }, -}; - -#ifdef CONFIG_PM_SLEEP -static int exynos4210_clock_suspend(void) -{ - s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); - - return 0; -} - -static void exynos4210_clock_resume(void) -{ - s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save)); -} - -#else -#define exynos4210_clock_suspend NULL -#define exynos4210_clock_resume NULL -#endif - -struct syscore_ops exynos4210_clock_syscore_ops = { - .suspend = exynos4210_clock_suspend, - .resume = exynos4210_clock_resume, -}; - -void __init exynos4210_register_clocks(void) -{ - int ptr; - - clk_mout_mpll.reg_src.reg = S5P_CLKSRC_CPU; - clk_mout_mpll.reg_src.shift = 8; - clk_mout_mpll.reg_src.size = 1; - - for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) - s3c_register_clksrc(sysclks[ptr], 1); - - s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); - - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - - register_syscore_ops(&exynos4210_clock_syscore_ops); -} diff --git a/trunk/arch/arm/mach-exynos4/clock-exynos4212.c b/trunk/arch/arm/mach-exynos4/clock-exynos4212.c deleted file mode 100644 index 77d5decb34fd..000000000000 --- a/trunk/arch/arm/mach-exynos4/clock-exynos4212.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/clock-exynos4212.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4212 - Clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static struct sleep_save exynos4212_clock_save[] = { - SAVE_ITEM(S5P_CLKSRC_IMAGE), - SAVE_ITEM(S5P_CLKDIV_IMAGE), - SAVE_ITEM(S5P_CLKGATE_IP_IMAGE_4212), - SAVE_ITEM(S5P_CLKGATE_IP_PERIR_4212), -}; - -static struct clk *clk_src_mpll_user_list[] = { - [0] = &clk_fin_mpll, - [1] = &clk_mout_mpll.clk, -}; - -static struct clksrc_sources clk_src_mpll_user = { - .sources = clk_src_mpll_user_list, - .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list), -}; - -static struct clksrc_clk clk_mout_mpll_user = { - .clk = { - .name = "mout_mpll_user", - }, - .sources = &clk_src_mpll_user, - .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 24, .size = 1 }, -}; - -static struct clksrc_clk *sysclks[] = { - &clk_mout_mpll_user, -}; - -static struct clksrc_clk clksrcs[] = { - /* nothing here yet */ -}; - -static struct clk init_clocks_off[] = { - /* nothing here yet */ -}; - -#ifdef CONFIG_PM_SLEEP -static int exynos4212_clock_suspend(void) -{ - s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save)); - - return 0; -} - -static void exynos4212_clock_resume(void) -{ - s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save)); -} - -#else -#define exynos4212_clock_suspend NULL -#define exynos4212_clock_resume NULL -#endif - -struct syscore_ops exynos4212_clock_syscore_ops = { - .suspend = exynos4212_clock_suspend, - .resume = exynos4212_clock_resume, -}; - -void __init exynos4212_register_clocks(void) -{ - int ptr; - - /* usbphy1 is removed */ - clkset_group_list[4] = NULL; - - /* mout_mpll_user is used */ - clkset_group_list[6] = &clk_mout_mpll_user.clk; - clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk; - - clk_mout_mpll.reg_src.reg = S5P_CLKSRC_DMC; - clk_mout_mpll.reg_src.shift = 12; - clk_mout_mpll.reg_src.size = 1; - - for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) - s3c_register_clksrc(sysclks[ptr], 1); - - s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); - - s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - - register_syscore_ops(&exynos4212_clock_syscore_ops); -} diff --git a/trunk/arch/arm/mach-exynos4/clock.c b/trunk/arch/arm/mach-exynos4/clock.c index 413c7cc81979..1561b036a9bf 100644 --- a/trunk/arch/arm/mach-exynos4/clock.c +++ b/trunk/arch/arm/mach-exynos4/clock.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include @@ -21,93 +20,26 @@ #include #include #include -#include -#include #include #include #include -#include - -static struct sleep_save exynos4_clock_save[] = { - SAVE_ITEM(S5P_CLKDIV_LEFTBUS), - SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS), - SAVE_ITEM(S5P_CLKDIV_RIGHTBUS), - SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS), - SAVE_ITEM(S5P_CLKSRC_TOP0), - SAVE_ITEM(S5P_CLKSRC_TOP1), - SAVE_ITEM(S5P_CLKSRC_CAM), - SAVE_ITEM(S5P_CLKSRC_TV), - SAVE_ITEM(S5P_CLKSRC_MFC), - SAVE_ITEM(S5P_CLKSRC_G3D), - SAVE_ITEM(S5P_CLKSRC_LCD0), - SAVE_ITEM(S5P_CLKSRC_MAUDIO), - SAVE_ITEM(S5P_CLKSRC_FSYS), - SAVE_ITEM(S5P_CLKSRC_PERIL0), - SAVE_ITEM(S5P_CLKSRC_PERIL1), - SAVE_ITEM(S5P_CLKDIV_CAM), - SAVE_ITEM(S5P_CLKDIV_TV), - SAVE_ITEM(S5P_CLKDIV_MFC), - SAVE_ITEM(S5P_CLKDIV_G3D), - SAVE_ITEM(S5P_CLKDIV_LCD0), - SAVE_ITEM(S5P_CLKDIV_MAUDIO), - SAVE_ITEM(S5P_CLKDIV_FSYS0), - SAVE_ITEM(S5P_CLKDIV_FSYS1), - SAVE_ITEM(S5P_CLKDIV_FSYS2), - SAVE_ITEM(S5P_CLKDIV_FSYS3), - SAVE_ITEM(S5P_CLKDIV_PERIL0), - SAVE_ITEM(S5P_CLKDIV_PERIL1), - SAVE_ITEM(S5P_CLKDIV_PERIL2), - SAVE_ITEM(S5P_CLKDIV_PERIL3), - SAVE_ITEM(S5P_CLKDIV_PERIL4), - SAVE_ITEM(S5P_CLKDIV_PERIL5), - SAVE_ITEM(S5P_CLKDIV_TOP), - SAVE_ITEM(S5P_CLKSRC_MASK_TOP), - SAVE_ITEM(S5P_CLKSRC_MASK_CAM), - SAVE_ITEM(S5P_CLKSRC_MASK_TV), - SAVE_ITEM(S5P_CLKSRC_MASK_LCD0), - SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO), - SAVE_ITEM(S5P_CLKSRC_MASK_FSYS), - SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0), - SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1), - SAVE_ITEM(S5P_CLKDIV2_RATIO), - SAVE_ITEM(S5P_CLKGATE_SCLKCAM), - SAVE_ITEM(S5P_CLKGATE_IP_CAM), - SAVE_ITEM(S5P_CLKGATE_IP_TV), - SAVE_ITEM(S5P_CLKGATE_IP_MFC), - SAVE_ITEM(S5P_CLKGATE_IP_G3D), - SAVE_ITEM(S5P_CLKGATE_IP_LCD0), - SAVE_ITEM(S5P_CLKGATE_IP_FSYS), - SAVE_ITEM(S5P_CLKGATE_IP_GPS), - SAVE_ITEM(S5P_CLKGATE_IP_PERIL), - SAVE_ITEM(S5P_CLKGATE_BLOCK), - SAVE_ITEM(S5P_CLKSRC_MASK_DMC), - SAVE_ITEM(S5P_CLKSRC_DMC), - SAVE_ITEM(S5P_CLKDIV_DMC0), - SAVE_ITEM(S5P_CLKDIV_DMC1), - SAVE_ITEM(S5P_CLKGATE_IP_DMC), - SAVE_ITEM(S5P_CLKSRC_CPU), - SAVE_ITEM(S5P_CLKDIV_CPU), - SAVE_ITEM(S5P_CLKDIV_CPU + 0x4), - SAVE_ITEM(S5P_CLKGATE_SCLKCPU), - SAVE_ITEM(S5P_CLKGATE_IP_CPU), -}; - -struct clk clk_sclk_hdmi27m = { + +static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .rate = 27000000, }; -struct clk clk_sclk_hdmiphy = { +static struct clk clk_sclk_hdmiphy = { .name = "sclk_hdmiphy", }; -struct clk clk_sclk_usbphy0 = { +static struct clk clk_sclk_usbphy0 = { .name = "sclk_usbphy0", .rate = 27000000, }; -struct clk clk_sclk_usbphy1 = { +static struct clk clk_sclk_usbphy1 = { .name = "sclk_usbphy1", }; @@ -126,7 +58,12 @@ static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); } -int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) +static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); +} + +static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); } @@ -166,12 +103,12 @@ static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); } -int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) +static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); } -int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) +static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); } @@ -196,7 +133,7 @@ static struct clksrc_clk clk_mout_apll = { .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 }, }; -struct clksrc_clk clk_sclk_apll = { +static struct clksrc_clk clk_sclk_apll = { .clk = { .name = "sclk_apll", .parent = &clk_mout_apll.clk, @@ -204,7 +141,7 @@ struct clksrc_clk clk_sclk_apll = { .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 }, }; -struct clksrc_clk clk_mout_epll = { +static struct clksrc_clk clk_mout_epll = { .clk = { .name = "mout_epll", }, @@ -212,13 +149,12 @@ struct clksrc_clk clk_mout_epll = { .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 }, }; -struct clksrc_clk clk_mout_mpll = { +static struct clksrc_clk clk_mout_mpll = { .clk = { .name = "mout_mpll", }, .sources = &clk_src_mpll, - - /* reg_src will be added in each SoCs' clock */ + .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 }, }; static struct clk *clkset_moutcore_list[] = { @@ -288,12 +224,12 @@ static struct clksrc_clk clk_periphclk = { /* Core list of CMU_CORE side */ -struct clk *clkset_corebus_list[] = { +static struct clk *clkset_corebus_list[] = { [0] = &clk_mout_mpll.clk, [1] = &clk_sclk_apll.clk, }; -struct clksrc_sources clkset_mout_corebus = { +static struct clksrc_sources clkset_mout_corebus = { .sources = clkset_corebus_list, .nr_sources = ARRAY_SIZE(clkset_corebus_list), }; @@ -348,12 +284,12 @@ static struct clksrc_clk clk_pclk_acp = { /* Core list of CMU_TOP side */ -struct clk *clkset_aclk_top_list[] = { +static struct clk *clkset_aclk_top_list[] = { [0] = &clk_mout_mpll.clk, [1] = &clk_sclk_apll.clk, }; -struct clksrc_sources clkset_aclk = { +static struct clksrc_sources clkset_aclk = { .sources = clkset_aclk_top_list, .nr_sources = ARRAY_SIZE(clkset_aclk_top_list), }; @@ -385,7 +321,7 @@ static struct clksrc_clk clk_aclk_160 = { .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 }, }; -struct clksrc_clk clk_aclk_133 = { +static struct clksrc_clk clk_aclk_133 = { .clk = { .name = "aclk_133", }, @@ -424,7 +360,7 @@ static struct clksrc_sources clkset_sclk_vpll = { .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list), }; -struct clksrc_clk clk_sclk_vpll = { +static struct clksrc_clk clk_sclk_vpll = { .clk = { .name = "sclk_vpll", }, @@ -473,6 +409,16 @@ static struct clk init_clocks_off[] = { .devname = "exynos4-fb.0", .enable = exynos4_clk_ip_lcd0_ctrl, .ctrlbit = (1 << 0), + }, { + .name = "fimd", + .devname = "exynos4-fb.1", + .enable = exynos4_clk_ip_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, { + .name = "sataphy", + .parent = &clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 3), }, { .name = "hsmmc", .devname = "s3c-sdhci.0", @@ -502,6 +448,11 @@ static struct clk init_clocks_off[] = { .parent = &clk_aclk_133.clk, .enable = exynos4_clk_ip_fsys_ctrl, .ctrlbit = (1 << 9), + }, { + .name = "sata", + .parent = &clk_aclk_133.clk, + .enable = exynos4_clk_ip_fsys_ctrl, + .ctrlbit = (1 << 10), }, { .name = "pdma", .devname = "s3c-pl330.0", @@ -722,7 +673,7 @@ static struct clk init_clocks[] = { } }; -struct clk *clkset_group_list[] = { +static struct clk *clkset_group_list[] = { [0] = &clk_ext_xtal_mux, [1] = &clk_xusbxti, [2] = &clk_sclk_hdmi27m, @@ -734,7 +685,7 @@ struct clk *clkset_group_list[] = { [8] = &clk_sclk_vpll.clk, }; -struct clksrc_sources clkset_group = { +static struct clksrc_sources clkset_group = { .sources = clkset_group_list, .nr_sources = ARRAY_SIZE(clkset_group_list), }; @@ -948,7 +899,8 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 }, }, { .clk = { - .name = "sclk_cam0", + .name = "sclk_cam", + .devname = "exynos4-fimc.0", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 16), }, @@ -957,7 +909,8 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 }, }, { .clk = { - .name = "sclk_cam1", + .name = "sclk_cam", + .devname = "exynos4-fimc.1", .enable = exynos4_clksrc_mask_cam_ctrl, .ctrlbit = (1 << 20), }, @@ -1014,6 +967,25 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_group, .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 }, .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_fimd", + .devname = "exynos4-fb.1", + .enable = exynos4_clksrc_mask_lcd1_ctrl, + .ctrlbit = (1 << 0), + }, + .sources = &clkset_group, + .reg_src = { .reg = S5P_CLKSRC_LCD1, .shift = 0, .size = 4 }, + .reg_div = { .reg = S5P_CLKDIV_LCD1, .shift = 0, .size = 4 }, + }, { + .clk = { + .name = "sclk_sata", + .enable = exynos4_clksrc_mask_fsys_ctrl, + .ctrlbit = (1 << 24), + }, + .sources = &clkset_mout_corebus, + .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 24, .size = 1 }, + .reg_div = { .reg = S5P_CLKDIV_FSYS0, .shift = 20, .size = 4 }, }, { .clk = { .name = "sclk_spi", @@ -1144,13 +1116,7 @@ static int xtal_rate; static unsigned long exynos4_fout_apll_get_rate(struct clk *clk) { - if (soc_is_exynos4210()) - return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), - pll_4508); - else if (soc_is_exynos4212()) - return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0)); - else - return 0; + return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); } static struct clk_ops exynos4_fout_apll_ops = { @@ -1160,10 +1126,10 @@ static struct clk_ops exynos4_fout_apll_ops = { void __init_or_cpufreq exynos4_setup_clocks(void) { struct clk *xtal_clk; - unsigned long apll = 0; - unsigned long mpll = 0; - unsigned long epll = 0; - unsigned long vpll = 0; + unsigned long apll; + unsigned long mpll; + unsigned long epll; + unsigned long vpll; unsigned long vpllsrc; unsigned long xtal; unsigned long armclk; @@ -1187,29 +1153,14 @@ void __init_or_cpufreq exynos4_setup_clocks(void) printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); - if (soc_is_exynos4210()) { - apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), - pll_4508); - mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), - pll_4508); - epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), - __raw_readl(S5P_EPLL_CON1), pll_4600); - - vpllsrc = clk_get_rate(&clk_vpllsrc.clk); - vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1), pll_4650c); - } else if (soc_is_exynos4212()) { - apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0)); - mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0)); - epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0), - __raw_readl(S5P_EPLL_CON1)); - - vpllsrc = clk_get_rate(&clk_vpllsrc.clk); - vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), - __raw_readl(S5P_VPLL_CON1)); - } else { - /* nothing */ - } + apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508); + mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508); + epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0), + __raw_readl(S5P_EPLL_CON1), pll_4600); + + vpllsrc = clk_get_rate(&clk_vpllsrc.clk); + vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), + __raw_readl(S5P_VPLL_CON1), pll_4650); clk_fout_apll.ops = &exynos4_fout_apll_ops; clk_fout_mpll.rate = mpll; @@ -1244,28 +1195,6 @@ static struct clk *clks[] __initdata = { /* Nothing here yet */ }; -#ifdef CONFIG_PM_SLEEP -static int exynos4_clock_suspend(void) -{ - s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); - return 0; -} - -static void exynos4_clock_resume(void) -{ - s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save)); -} - -#else -#define exynos4_clock_suspend NULL -#define exynos4_clock_resume NULL -#endif - -struct syscore_ops exynos4_clock_syscore_ops = { - .suspend = exynos4_clock_suspend, - .resume = exynos4_clock_resume, -}; - void __init exynos4_register_clocks(void) { int ptr; @@ -1281,6 +1210,5 @@ void __init exynos4_register_clocks(void) s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); - register_syscore_ops(&exynos4_clock_syscore_ops); s3c_pwmclk_init(); } diff --git a/trunk/arch/arm/mach-exynos4/cpu.c b/trunk/arch/arm/mach-exynos4/cpu.c index 02ec52a99274..746d6fc6d397 100644 --- a/trunk/arch/arm/mach-exynos4/cpu.c +++ b/trunk/arch/arm/mach-exynos4/cpu.c @@ -43,6 +43,11 @@ static struct map_desc exynos4_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER), .length = SZ_4K, .type = MT_DEVICE, + }, { + .virtual = (unsigned long)S5P_VA_SYSRAM, + .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM), + .length = SZ_4K, + .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_CMU, .pfn = __phys_to_pfn(EXYNOS4_PA_CMU), @@ -116,24 +121,6 @@ static struct map_desc exynos4_iodesc[] __initdata = { }, }; -static struct map_desc exynos4_iodesc0[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM0), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static struct map_desc exynos4_iodesc1[] __initdata = { - { - .virtual = (unsigned long)S5P_VA_SYSRAM, - .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM1), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - static void exynos4_idle(void) { if (!need_resched()) @@ -156,11 +143,6 @@ void __init exynos4_map_io(void) { iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc)); - if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0) - iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0)); - else - iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1)); - /* initialize device information early */ exynos4_default_sdhci0(); exynos4_default_sdhci1(); @@ -188,12 +170,6 @@ void __init exynos4_init_clocks(int xtal) s3c24xx_register_baseclocks(xtal); s5p_register_clocks(xtal); - - if (soc_is_exynos4210()) - exynos4210_register_clocks(); - else if (soc_is_exynos4212()) - exynos4212_register_clocks(); - exynos4_register_clocks(); exynos4_setup_clocks(); } @@ -247,11 +223,7 @@ static int __init exynos4_l2x0_cache_init(void) { /* TAG, Data Latency Control: 2cycle */ __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); - - if (soc_is_exynos4210()) - __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); - else if (soc_is_exynos4212()) - __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); + __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL); /* L2X0 Prefetch Control */ __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL); diff --git a/trunk/arch/arm/mach-exynos4/include/mach/exynos4-clock.h b/trunk/arch/arm/mach-exynos4/include/mach/exynos4-clock.h deleted file mode 100644 index a07fcbf55251..000000000000 --- a/trunk/arch/arm/mach-exynos4/include/mach/exynos4-clock.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/include/mach/exynos4-clock.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Header file for exynos4 clock support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H __FILE__ - -#include - -extern struct clk clk_sclk_hdmi27m; -extern struct clk clk_sclk_usbphy0; -extern struct clk clk_sclk_usbphy1; -extern struct clk clk_sclk_hdmiphy; - -extern struct clksrc_clk clk_sclk_apll; -extern struct clksrc_clk clk_mout_mpll; -extern struct clksrc_clk clk_aclk_133; -extern struct clksrc_clk clk_mout_epll; -extern struct clksrc_clk clk_sclk_vpll; - -extern struct clk *clkset_corebus_list[]; -extern struct clksrc_sources clkset_mout_corebus; - -extern struct clk *clkset_aclk_top_list[]; -extern struct clksrc_sources clkset_aclk; - -extern struct clk *clkset_group_list[]; -extern struct clksrc_sources clkset_group; - -extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable); -extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable); -extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/trunk/arch/arm/mach-exynos4/include/mach/map.h b/trunk/arch/arm/mach-exynos4/include/mach/map.h index 7073ac730855..d32296dc65e2 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/map.h +++ b/trunk/arch/arm/mach-exynos4/include/mach/map.h @@ -23,8 +23,7 @@ #include -#define EXYNOS4_PA_SYSRAM0 0x02025000 -#define EXYNOS4_PA_SYSRAM1 0x02020000 +#define EXYNOS4_PA_SYSRAM 0x02020000 #define EXYNOS4_PA_FIMC0 0x11800000 #define EXYNOS4_PA_FIMC1 0x11810000 diff --git a/trunk/arch/arm/mach-exynos4/include/mach/regs-clock.h b/trunk/arch/arm/mach-exynos4/include/mach/regs-clock.h index 6c37ebe94829..d493fdb422ff 100644 --- a/trunk/arch/arm/mach-exynos4/include/mach/regs-clock.h +++ b/trunk/arch/arm/mach-exynos4/include/mach/regs-clock.h @@ -13,7 +13,6 @@ #ifndef __ASM_ARCH_REGS_CLOCK_H #define __ASM_ARCH_REGS_CLOCK_H __FILE__ -#include #include #define S5P_CLKREG(x) (S5P_VA_CMU + (x)) @@ -42,20 +41,12 @@ #define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C) #define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230) #define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234) +#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) #define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C) #define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240) #define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250) #define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254) -#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) -#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) -#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) -#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) -#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) -#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) -#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) -#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) - #define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510) #define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520) #define S5P_CLKDIV_TV S5P_CLKREG(0x0C524) @@ -63,6 +54,7 @@ #define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C) #define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530) #define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534) +#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) #define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C) #define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540) #define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544) @@ -76,6 +68,16 @@ #define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564) #define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580) +#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310) +#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320) +#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324) +#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334) +#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) +#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C) +#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340) +#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350) +#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354) + #define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610) #define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820) @@ -83,20 +85,13 @@ #define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924) #define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928) #define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C) -#define S5P_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ - S5P_CLKREG(0x0C930) : \ - S5P_CLKREG(0x04930)) -#define S5P_CLKGATE_IP_IMAGE_4210 S5P_CLKREG(0x0C930) -#define S5P_CLKGATE_IP_IMAGE_4212 S5P_CLKREG(0x04930) +#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930) #define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934) +#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) #define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940) #define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C) #define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950) -#define S5P_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ - S5P_CLKREG(0x0C960) : \ - S5P_CLKREG(0x08960)) -#define S5P_CLKGATE_IP_PERIR_4210 S5P_CLKREG(0x0C960) -#define S5P_CLKGATE_IP_PERIR_4212 S5P_CLKREG(0x08960) +#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960) #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970) #define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300) @@ -107,17 +102,11 @@ #define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900) #define S5P_APLL_LOCK S5P_CLKREG(0x14000) -#define S5P_MPLL_LOCK (soc_is_exynos4210() ? \ - S5P_CLKREG(0x14004) : \ - S5P_CLKREG(0x10008)) +#define S5P_MPLL_LOCK S5P_CLKREG(0x14004) #define S5P_APLL_CON0 S5P_CLKREG(0x14100) #define S5P_APLL_CON1 S5P_CLKREG(0x14104) -#define S5P_MPLL_CON0 (soc_is_exynos4210() ? \ - S5P_CLKREG(0x14108) : \ - S5P_CLKREG(0x10108)) -#define S5P_MPLL_CON1 (soc_is_exynos4210() ? \ - S5P_CLKREG(0x1410C) : \ - S5P_CLKREG(0x1010C)) +#define S5P_MPLL_CON0 S5P_CLKREG(0x14108) +#define S5P_MPLL_CON1 S5P_CLKREG(0x1410C) #define S5P_CLKSRC_CPU S5P_CLKREG(0x14200) #define S5P_CLKMUX_STATCPU S5P_CLKREG(0x14400) @@ -194,13 +183,6 @@ #define S5P_CLKDIV_BUS_GPLR_SHIFT (4) #define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT) -/* Only for EXYNOS4210 */ - -#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238) -#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338) -#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538) -#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938) - /* Compatibility defines and inclusion */ #include diff --git a/trunk/arch/arm/mach-exynos4/mach-origen.c b/trunk/arch/arm/mach-exynos4/mach-origen.c deleted file mode 100644 index ed59f86001ac..000000000000 --- a/trunk/arch/arm/mach-exynos4/mach-origen.c +++ /dev/null @@ -1,108 +0,0 @@ -/* linux/arch/arm/mach-exynos4/mach-origen.c - * - * Copyright (c) 2011 Insignal Co., Ltd. - * http://www.insignal.co.kr/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = ORIGEN_UCON_DEFAULT, - .ulcon = ORIGEN_ULCON_DEFAULT, - .ufcon = ORIGEN_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_GPIO, - .ext_cd_gpio = EXYNOS4_GPK2(2), - .ext_cd_gpio_invert = 1, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, -}; - -static struct platform_device *origen_devices[] __initdata = { - &s3c_device_hsmmc2, - &s3c_device_rtc, - &s3c_device_wdt, -}; - -static void __init origen_map_io(void) -{ - s5p_init_io(NULL, 0, S5P_VA_CHIPID); - s3c24xx_init_clocks(24000000); - s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); -} - -static void __init origen_machine_init(void) -{ - s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); - platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); -} - -MACHINE_START(ORIGEN, "ORIGEN") - /* Maintainer: JeongHyeon Kim */ - .boot_params = S5P_PA_SDRAM + 0x100, - .init_irq = exynos4_init_irq, - .map_io = origen_map_io, - .init_machine = origen_machine_init, - .timer = &exynos4_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-exynos4/mach-smdk4212.c b/trunk/arch/arm/mach-exynos4/mach-smdk4212.c deleted file mode 100644 index 3479a933a6de..000000000000 --- a/trunk/arch/arm/mach-exynos4/mach-smdk4212.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * linux/arch/arm/mach-exynos4/mach-smdk4212.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* Following are default values for UCON, ULCON and UFCON UART registers */ -#define SMDK4212_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ - S3C2410_UCON_RXILEVEL | \ - S3C2410_UCON_TXIRQMODE | \ - S3C2410_UCON_RXIRQMODE | \ - S3C2410_UCON_RXFIFO_TOI | \ - S3C2443_UCON_RXERR_IRQEN) - -#define SMDK4212_ULCON_DEFAULT S3C2410_LCON_CS8 - -#define SMDK4212_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ - S5PV210_UFCON_TXTRIG4 | \ - S5PV210_UFCON_RXTRIG4) - -static struct s3c2410_uartcfg smdk4212_uartcfgs[] __initdata = { - [0] = { - .hwport = 0, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, - [1] = { - .hwport = 1, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, - [2] = { - .hwport = 2, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, - [3] = { - .hwport = 3, - .flags = 0, - .ucon = SMDK4212_UCON_DEFAULT, - .ulcon = SMDK4212_ULCON_DEFAULT, - .ufcon = SMDK4212_UFCON_DEFAULT, - }, -}; - -static struct s3c_sdhci_platdata smdk4212_hsmmc2_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, -#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT - .max_width = 8, - .host_caps = MMC_CAP_8_BIT_DATA, -#endif -}; - -static struct s3c_sdhci_platdata smdk4212_hsmmc3_pdata __initdata = { - .cd_type = S3C_SDHCI_CD_INTERNAL, - .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, -}; - -static struct regulator_consumer_supply max8997_buck1 = - REGULATOR_SUPPLY("vdd_arm", NULL); - -static struct regulator_consumer_supply max8997_buck2 = - REGULATOR_SUPPLY("vdd_int", NULL); - -static struct regulator_consumer_supply max8997_buck3 = - REGULATOR_SUPPLY("vdd_g3d", NULL); - -static struct regulator_init_data max8997_buck1_data = { - .constraints = { - .name = "VDD_ARM_SMDK4212", - .min_uV = 925000, - .max_uV = 1350000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck1, -}; - -static struct regulator_init_data max8997_buck2_data = { - .constraints = { - .name = "VDD_INT_SMDK4212", - .min_uV = 950000, - .max_uV = 1150000, - .always_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck2, -}; - -static struct regulator_init_data max8997_buck3_data = { - .constraints = { - .name = "VDD_G3D_SMDK4212", - .min_uV = 950000, - .max_uV = 1150000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .state_mem = { - .disabled = 1, - }, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8997_buck3, -}; - -static struct max8997_regulator_data smdk4212_max8997_regulators[] = { - { MAX8997_BUCK1, &max8997_buck1_data }, - { MAX8997_BUCK2, &max8997_buck2_data }, - { MAX8997_BUCK3, &max8997_buck3_data }, -}; - -static struct max8997_platform_data smdk4212_max8997_pdata = { - .num_regulators = ARRAY_SIZE(smdk4212_max8997_regulators), - .regulators = smdk4212_max8997_regulators, - - .buck1_voltage[0] = 1100000, /* 1.1V */ - .buck1_voltage[1] = 1100000, /* 1.1V */ - .buck1_voltage[2] = 1100000, /* 1.1V */ - .buck1_voltage[3] = 1100000, /* 1.1V */ - .buck1_voltage[4] = 1100000, /* 1.1V */ - .buck1_voltage[5] = 1100000, /* 1.1V */ - .buck1_voltage[6] = 1000000, /* 1.0V */ - .buck1_voltage[7] = 950000, /* 0.95V */ - - .buck2_voltage[0] = 1100000, /* 1.1V */ - .buck2_voltage[1] = 1000000, /* 1.0V */ - .buck2_voltage[2] = 950000, /* 0.95V */ - .buck2_voltage[3] = 900000, /* 0.9V */ - .buck2_voltage[4] = 1100000, /* 1.1V */ - .buck2_voltage[5] = 1000000, /* 1.0V */ - .buck2_voltage[6] = 950000, /* 0.95V */ - .buck2_voltage[7] = 900000, /* 0.9V */ - - .buck5_voltage[0] = 1100000, /* 1.1V */ - .buck5_voltage[1] = 1100000, /* 1.1V */ - .buck5_voltage[2] = 1100000, /* 1.1V */ - .buck5_voltage[3] = 1100000, /* 1.1V */ - .buck5_voltage[4] = 1100000, /* 1.1V */ - .buck5_voltage[5] = 1100000, /* 1.1V */ - .buck5_voltage[6] = 1100000, /* 1.1V */ - .buck5_voltage[7] = 1100000, /* 1.1V */ -}; - -static struct i2c_board_info smdk4212_i2c_devs0[] __initdata = { - { - I2C_BOARD_INFO("max8997", 0x66), - .platform_data = &smdk4212_max8997_pdata, - } -}; - -static struct i2c_board_info smdk4212_i2c_devs1[] __initdata = { - { I2C_BOARD_INFO("wm8994", 0x1a), } -}; - -static struct i2c_board_info smdk4212_i2c_devs3[] __initdata = { - /* nothing here yet */ -}; - -static struct i2c_board_info smdk4212_i2c_devs7[] __initdata = { - /* nothing here yet */ -}; - -static struct samsung_bl_gpio_info smdk4212_bl_gpio_info = { - .no = EXYNOS4_GPD0(1), - .func = S3C_GPIO_SFN(2), -}; - -static struct platform_pwm_backlight_data smdk4212_bl_data = { - .pwm_id = 1, - .pwm_period_ns = 1000, -}; - -static uint32_t smdk4212_keymap[] __initdata = { - /* KEY(row, col, keycode) */ - KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B), - KEY(1, 3, KEY_E), KEY(1, 4, KEY_C) -}; - -static struct matrix_keymap_data smdk4212_keymap_data __initdata = { - .keymap = smdk4212_keymap, - .keymap_size = ARRAY_SIZE(smdk4212_keymap), -}; - -static struct samsung_keypad_platdata smdk4212_keypad_data __initdata = { - .keymap_data = &smdk4212_keymap_data, - .rows = 2, - .cols = 5, -}; - -static struct platform_device *smdk4212_devices[] __initdata = { - &s3c_device_hsmmc2, - &s3c_device_hsmmc3, - &s3c_device_i2c0, - &s3c_device_i2c1, - &s3c_device_i2c3, - &s3c_device_i2c7, - &s3c_device_rtc, - &s3c_device_wdt, - &samsung_device_keypad, -}; - -static void __init smdk4212_map_io(void) -{ - clk_xusbxti.rate = 24000000; - - s5p_init_io(NULL, 0, S5P_VA_CHIPID); - s3c24xx_init_clocks(clk_xusbxti.rate); - s3c24xx_init_uarts(smdk4212_uartcfgs, ARRAY_SIZE(smdk4212_uartcfgs)); -} - -static void __init smdk4212_machine_init(void) -{ - s3c_i2c0_set_platdata(NULL); - i2c_register_board_info(0, smdk4212_i2c_devs0, - ARRAY_SIZE(smdk4212_i2c_devs0)); - - s3c_i2c1_set_platdata(NULL); - i2c_register_board_info(1, smdk4212_i2c_devs1, - ARRAY_SIZE(smdk4212_i2c_devs1)); - - s3c_i2c3_set_platdata(NULL); - i2c_register_board_info(3, smdk4212_i2c_devs3, - ARRAY_SIZE(smdk4212_i2c_devs3)); - - s3c_i2c7_set_platdata(NULL); - i2c_register_board_info(7, smdk4212_i2c_devs7, - ARRAY_SIZE(smdk4212_i2c_devs7)); - - samsung_bl_set(&smdk4212_bl_gpio_info, &smdk4212_bl_data); - - samsung_keypad_set_platdata(&smdk4212_keypad_data); - - s3c_sdhci2_set_platdata(&smdk4212_hsmmc2_pdata); - s3c_sdhci3_set_platdata(&smdk4212_hsmmc3_pdata); - - platform_add_devices(smdk4212_devices, ARRAY_SIZE(smdk4212_devices)); -} - -MACHINE_START(SMDK4212, "SMDK4212") - /* Maintainer: Kukjin Kim */ - .boot_params = S5P_PA_SDRAM + 0x100, - .init_irq = exynos4_init_irq, - .map_io = smdk4212_map_io, - .init_machine = smdk4212_machine_init, - .timer = &exynos4_timer, -MACHINE_END diff --git a/trunk/arch/arm/mach-exynos4/mach-smdkc210.c b/trunk/arch/arm/mach-exynos4/mach-smdkc210.c new file mode 100644 index 000000000000..a7c65e05c1eb --- /dev/null +++ b/trunk/arch/arm/mach-exynos4/mach-smdkc210.c @@ -0,0 +1,309 @@ +/* linux/arch/arm/mach-exynos4/mach-smdkc210.c + * + * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include