From 7c1a43782983c0d07c33344d1911009d969ddf1f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 3 Nov 2009 03:14:38 +0000 Subject: [PATCH] --- yaml --- r: 169009 b: refs/heads/master c: f99e8c1d0f41011870d14d5990c65e65b123f2ef h: refs/heads/master i: 169007: afc49a5fd4ca5b5bb270491d5b1ab25d8f5782df v: v3 --- [refs] | 2 +- trunk/arch/blackfin/mach-bf561/atomic.S | 14 ++++++++++++-- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index a2e9606063dd..823e54467432 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: af5d7fc7e4d8e34bad42178f7011287e94eeb3ed +refs/heads/master: f99e8c1d0f41011870d14d5990c65e65b123f2ef diff --git a/trunk/arch/blackfin/mach-bf561/atomic.S b/trunk/arch/blackfin/mach-bf561/atomic.S index 0261a5e751b3..f99f174b129f 100644 --- a/trunk/arch/blackfin/mach-bf561/atomic.S +++ b/trunk/arch/blackfin/mach-bf561/atomic.S @@ -19,6 +19,16 @@ \reg\().h = _corelock; .endm +.macro safe_testset addr:req, scratch:req +#if ANOMALY_05000477 + cli \scratch; + testset (\addr); + sti \scratch; +#else + testset (\addr); +#endif +.endm + /* * r0 = address of atomic data to flush and invalidate (32bit). * @@ -33,7 +43,7 @@ ENTRY(_get_core_lock) cli r0; coreslot_loadaddr p0; .Lretry_corelock: - testset (p0); + safe_testset p0, r2; if cc jump .Ldone_corelock; SSYNC(r2); jump .Lretry_corelock @@ -56,7 +66,7 @@ ENTRY(_get_core_lock_noflush) cli r0; coreslot_loadaddr p0; .Lretry_corelock_noflush: - testset (p0); + safe_testset p0, r2; if cc jump .Ldone_corelock_noflush; SSYNC(r2); jump .Lretry_corelock_noflush