From 7d264a64fe5fd4da08ff6769f3989635d799a3de Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 7 May 2013 14:46:50 +0200 Subject: [PATCH] --- yaml --- r: 374206 b: refs/heads/master c: 0592c2189ece16f3e0c5a56245634aba93d0c9dd h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/Documentation/arm/sunxi/clocks.txt | 56 + trunk/Documentation/clk.txt | 4 +- .../devicetree/bindings/arm/primecell.txt | 19 +- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 67 +- .../devicetree/bindings/ata/pata-arasan.txt | 22 + .../devicetree/bindings/bus/ti-gpmc.txt | 103 +- .../devicetree/bindings/clock/axi-clkgen.txt | 22 + .../bindings/clock/nvidia,tegra114-car.txt | 303 +++ .../bindings/clock/nvidia,tegra20-car.txt | 4 +- .../devicetree/bindings/clock/sunxi.txt | 44 + .../samsung,s3c24xx-irq.txt | 53 + .../devicetree/bindings/mtd/gpmc-nor.txt | 98 + .../devicetree/bindings/mtd/gpmc-onenand.txt | 3 + .../devicetree/bindings/net/gpmc-eth.txt | 97 + .../devicetree/bindings/serial/pl011.txt | 17 + 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2 +- trunk/drivers/gpu/drm/i915/intel_crt.c | 40 +- trunk/drivers/gpu/drm/i915/intel_dp.c | 3 + .../gpu/drm/nouveau/core/subdev/bios/base.c | 17 + trunk/drivers/gpu/drm/nouveau/nouveau_abi16.c | 18 +- trunk/drivers/gpu/drm/nouveau/nouveau_drm.c | 32 +- trunk/drivers/gpu/drm/nouveau/nouveau_drm.h | 2 +- trunk/drivers/gpu/drm/radeon/radeon_bios.c | 26 + trunk/drivers/hid/hid-core.c | 13 +- trunk/drivers/hid/hid-ids.h | 5 +- trunk/drivers/hid/hid-magicmouse.c | 29 +- .../i2c/busses/i2c-designware-platdrv.c | 1 - trunk/drivers/infiniband/hw/qib/qib_sd7220.c | 2 +- trunk/drivers/irqchip/Makefile | 2 + .../irqchip}/irq-armada-370-xp.c | 114 +- .../irq.c => drivers/irqchip/irq-s3c24xx.c} | 523 ++++- trunk/drivers/md/dm-cache-target.c | 51 +- trunk/drivers/media/platform/Kconfig | 2 +- trunk/drivers/media/radio/radio-ma901.c | 11 + trunk/drivers/net/bonding/bond_main.c | 5 +- trunk/drivers/net/bonding/bond_sysfs.c | 92 +- trunk/drivers/net/can/sja1000/Kconfig | 1 + trunk/drivers/net/can/sja1000/plx_pci.c | 4 +- trunk/drivers/net/can/sja1000/sja1000.c | 6 +- trunk/drivers/net/can/sja1000/sja1000.h | 2 +- .../net/ethernet/atheros/atl1e/atl1e.h | 3 +- .../net/ethernet/atheros/atl1e/atl1e_main.c | 20 +- trunk/drivers/net/ethernet/broadcom/tg3.c | 7 +- trunk/drivers/net/ethernet/calxeda/xgmac.c | 9 +- trunk/drivers/net/ethernet/davicom/dm9000.c | 214 +- trunk/drivers/net/ethernet/davicom/dm9000.h | 11 +- trunk/drivers/net/ethernet/freescale/fec.c | 82 +- .../net/ethernet/intel/e1000/e1000_ethtool.c | 14 +- .../net/ethernet/intel/e1000e/netdev.c | 7 +- .../net/ethernet/intel/ixgb/ixgb_main.c | 7 +- .../net/ethernet/intel/ixgbe/ixgbe_main.c | 11 +- trunk/drivers/net/ethernet/marvell/sky2.c | 2 +- trunk/drivers/net/ethernet/marvell/sky2.h | 2 +- .../net/ethernet/mellanox/mlx4/en_netdev.c | 4 +- trunk/drivers/net/ethernet/micrel/ks8851.c | 2 +- trunk/drivers/net/ethernet/realtek/r8169.c | 28 +- trunk/drivers/net/ethernet/renesas/sh_eth.c | 28 +- trunk/drivers/net/ethernet/renesas/sh_eth.h | 2 +- trunk/drivers/net/ethernet/ti/cpsw.c | 2 +- trunk/drivers/net/ethernet/ti/davinci_emac.c | 2 +- trunk/drivers/net/usb/smsc75xx.c | 12 +- trunk/drivers/net/wireless/ath/ath9k/link.c | 3 +- trunk/drivers/net/wireless/b43/dma.c | 65 +- trunk/drivers/net/wireless/b43/phy_n.c | 8 +- .../wireless/brcm80211/brcmsmac/phy/phy_lcn.c | 369 +-- .../brcm80211/brcmsmac/phy/phytbl_lcn.c | 64 +- trunk/drivers/net/wireless/iwlegacy/4965-rs.c | 3 +- trunk/drivers/net/wireless/iwlwifi/dvm/lib.c | 9 + trunk/drivers/net/wireless/iwlwifi/dvm/rxon.c | 18 +- trunk/drivers/net/wireless/iwlwifi/dvm/tx.c | 2 +- .../drivers/net/wireless/iwlwifi/dvm/ucode.c | 4 +- .../drivers/net/wireless/iwlwifi/pcie/trans.c | 13 + trunk/drivers/net/wireless/iwlwifi/pcie/tx.c | 2 +- trunk/drivers/net/wireless/mwifiex/cfg80211.c | 3 +- trunk/drivers/net/wireless/mwifiex/pcie.c | 1 + trunk/drivers/nfc/microread/mei.c | 38 +- trunk/drivers/pci/pci-acpi.c | 15 +- trunk/drivers/pci/pci-driver.c | 5 +- trunk/drivers/pci/pcie/portdrv_pci.c | 13 - trunk/drivers/pci/rom.c | 67 +- trunk/drivers/rtc/rtc-at91rm9200.c | 50 +- trunk/drivers/rtc/rtc-at91rm9200.h | 1 + trunk/drivers/s390/block/scm_blk.c | 11 +- trunk/drivers/s390/block/scm_drv.c | 2 +- trunk/drivers/s390/char/tty3270.c | 16 +- trunk/drivers/scsi/bnx2fc/bnx2fc_fcoe.c | 6 +- trunk/drivers/scsi/fcoe/fcoe.c | 15 +- trunk/drivers/scsi/fcoe/fcoe_ctlr.c | 60 +- trunk/drivers/scsi/libfc/fc_disc.c | 26 +- trunk/drivers/spi/Kconfig | 3 +- trunk/drivers/spi/spi-bcm63xx.c | 3 +- trunk/drivers/spi/spi-mpc512x-psc.c | 2 +- trunk/drivers/spi/spi-pl022.c | 43 +- trunk/drivers/spi/spi-pxa2xx.c | 1 - trunk/drivers/spi/spi-s3c64xx.c | 41 +- trunk/drivers/spi/spi-tegra20-slink.c | 25 +- trunk/drivers/spi/spi.c | 17 +- trunk/drivers/tty/serial/amba-pl011.c | 64 +- trunk/drivers/usb/core/port.c | 1 - trunk/drivers/video/fbmon.c | 2 +- .../video/omap2/displays/panel-generic-dpi.c | 2 +- .../drivers/video/omap2/displays/panel-n8x0.c | 2 +- .../video/omap2/displays/panel-picodlp.c | 2 +- .../drivers/video/omap2/displays/panel-taal.c | 2 +- .../video/omap2/displays/panel-tfp410.c | 2 +- trunk/drivers/video/sh_mobile_lcdcfb.c | 1 + trunk/drivers/video/uvesafb.c | 3 +- trunk/firmware/Makefile | 2 +- .../firmware/{intel => qlogic}/sd7220.fw.ihex | 0 trunk/fs/block_dev.c | 1 + trunk/fs/ext4/extents.c | 11 +- trunk/fs/ext4/indirect.c | 4 +- trunk/fs/gfs2/file.c | 5 +- trunk/fs/gfs2/incore.h | 1 + trunk/fs/gfs2/lock_dlm.c | 39 +- trunk/fs/gfs2/rgrp.c | 32 +- trunk/fs/nfsd/nfs4xdr.c | 2 +- trunk/fs/reiserfs/xattr.c | 4 +- trunk/fs/ubifs/super.c | 12 +- trunk/include/clocksource/arm_arch_timer.h | 6 - trunk/include/linux/clk-private.h | 2 +- trunk/include/linux/clk-provider.h | 51 +- trunk/include/linux/clk/sunxi.h | 22 + trunk/include/linux/clk/tegra.h | 1 + trunk/include/linux/compat.h | 4 +- trunk/include/linux/devfreq.h | 16 +- trunk/include/linux/kvm_host.h | 2 +- trunk/include/linux/kvm_types.h | 1 + trunk/include/linux/netdevice.h | 4 +- trunk/include/linux/of.h | 5 + trunk/include/linux/pata_arasan_cf_data.h | 2 - trunk/include/linux/pci.h | 1 + trunk/include/linux/signal.h | 4 +- trunk/include/linux/skbuff.h | 7 + trunk/include/scsi/libfc.h | 3 +- trunk/include/sound/max98090.h | 0 trunk/include/sound/soc-dapm.h | 1 + trunk/include/video/omap-panel-data.h | 152 ++ trunk/include/video/omap-panel-generic-dpi.h | 37 - trunk/include/video/omap-panel-n8x0.h | 15 - trunk/include/video/omap-panel-nokia-dsi.h | 32 - trunk/include/video/omap-panel-picodlp.h | 23 - trunk/include/video/omap-panel-tfp410.h | 35 - trunk/ipc/msg.c | 1 + trunk/mm/mmap.c | 2 +- trunk/mm/nommu.c | 2 +- trunk/net/core/dev.c | 8 +- trunk/net/core/dev_addr_lists.c | 6 +- trunk/net/core/flow.c | 2 +- trunk/net/core/rtnetlink.c | 4 +- trunk/net/ipv4/devinet.c | 6 +- trunk/net/ipv6/addrconf.c | 27 + trunk/net/ipv6/ip6_input.c | 12 + trunk/net/ipv6/netfilter/ip6t_NPT.c | 2 +- trunk/net/key/af_key.c | 1 + trunk/net/mac80211/cfg.c | 6 +- trunk/net/mac80211/chan.c | 17 +- trunk/net/mac80211/ieee80211_i.h | 4 +- trunk/net/mac80211/iface.c | 37 +- trunk/net/mac80211/mesh.c | 3 +- trunk/net/mac80211/mlme.c | 6 +- trunk/net/mac80211/offchannel.c | 23 +- trunk/net/mac80211/rx.c | 14 +- trunk/net/mac80211/sta_info.c | 12 +- trunk/net/netfilter/nf_conntrack_standalone.c | 1 + trunk/net/netfilter/nfnetlink_acct.c | 2 + trunk/net/netfilter/nfnetlink_queue_core.c | 4 +- trunk/net/nfc/llcp/llcp.c | 8 - trunk/net/nfc/llcp/sock.c | 6 +- trunk/net/sched/sch_cbq.c | 5 +- trunk/net/sched/sch_fq_codel.c | 2 +- trunk/net/sched/sch_generic.c | 2 +- trunk/net/unix/af_unix.c | 6 +- trunk/net/vmw_vsock/af_vsock.c | 6 +- trunk/net/vmw_vsock/vmci_transport.c | 31 +- trunk/net/vmw_vsock/vsock_addr.c | 10 - trunk/net/vmw_vsock/vsock_addr.h | 2 - trunk/net/wireless/core.c | 64 +- trunk/net/wireless/core.h | 3 + trunk/net/wireless/nl80211.c | 52 +- trunk/net/wireless/scan.c | 24 +- trunk/net/wireless/sme.c | 6 +- trunk/net/wireless/trace.h | 5 +- trunk/net/wireless/wext-sme.c | 6 + trunk/net/xfrm/xfrm_replay.c | 66 +- trunk/sound/pci/hda/hda_codec.c | 2 +- trunk/sound/pci/hda/hda_eld.c | 2 +- trunk/sound/pci/hda/hda_generic.c | 2 +- trunk/sound/pci/hda/hda_intel.c | 6 +- trunk/sound/pci/hda/patch_hdmi.c | 2 +- trunk/sound/pci/hda/patch_realtek.c | 4 +- trunk/sound/soc/codecs/max98090.c | 0 trunk/sound/soc/codecs/max98090.h | 0 trunk/sound/soc/codecs/si476x.c | 1 + trunk/sound/soc/codecs/wm_adsp.c | 5 +- trunk/sound/soc/fsl/imx-ssi.c | 5 + trunk/sound/soc/fsl/pcm030-audio-fabric.c | 2 +- trunk/sound/soc/sh/dma-sh7760.c | 4 +- trunk/sound/soc/soc-core.c | 8 +- trunk/sound/soc/soc-dapm.c | 14 + trunk/sound/soc/spear/spear_pcm.c | 12 +- trunk/sound/usb/clock.c | 45 +- trunk/virt/kvm/kvm_main.c | 47 +- 573 files changed, 14981 insertions(+), 5536 deletions(-) create mode 100644 trunk/Documentation/arm/sunxi/clocks.txt create mode 100644 trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt create mode 100644 trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt create mode 100644 trunk/Documentation/devicetree/bindings/clock/sunxi.txt create mode 100644 trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt create mode 100644 trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt create mode 100644 trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt create mode 100644 trunk/Documentation/devicetree/bindings/serial/pl011.txt create mode 100644 trunk/Documentation/devicetree/bindings/timer/arm,sp804.txt create mode 100644 trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt create mode 100644 trunk/arch/arm/boot/dts/sama5d3.dtsi create mode 100644 trunk/arch/arm/boot/dts/sama5d31ek.dts create mode 100644 trunk/arch/arm/boot/dts/sama5d33ek.dts create mode 100644 trunk/arch/arm/boot/dts/sama5d34ek.dts create mode 100644 trunk/arch/arm/boot/dts/sama5d35ek.dts create mode 100644 trunk/arch/arm/boot/dts/sama5d3xcm.dtsi create mode 100644 trunk/arch/arm/boot/dts/sama5d3xdm.dtsi create mode 100644 trunk/arch/arm/boot/dts/sama5d3xmb.dtsi create mode 100644 trunk/arch/arm/configs/sama5_defconfig create mode 100644 trunk/arch/arm/mach-at91/Kconfig.non_dt rename trunk/arch/arm/mach-at91/{board-rm9200-dt.c => board-dt-rm9200.c} (100%) rename trunk/arch/arm/mach-at91/{board-dt.c => board-dt-sam9.c} (100%) create mode 100644 trunk/arch/arm/mach-at91/board-dt-sama5.c create mode 100644 trunk/arch/arm/mach-at91/include/mach/sama5d3.h create mode 100644 trunk/arch/arm/mach-at91/sama5d3.c delete mode 100644 trunk/arch/arm/mach-exynos/include/mach/regs-mct.h delete mode 100644 trunk/arch/arm/mach-s3c24xx/include/mach/entry-macro.S create mode 100644 trunk/arch/arm/mach-spear/Kconfig create mode 100644 trunk/arch/arm/mach-spear/Makefile rename trunk/arch/arm/{mach-spear13xx => mach-spear}/Makefile.boot (100%) rename trunk/arch/arm/{mach-spear13xx/include/mach => mach-spear}/generic.h (51%) rename trunk/arch/arm/{mach-spear13xx => mach-spear}/headsmp.S (100%) rename trunk/arch/arm/{mach-spear13xx => mach-spear}/hotplug.c (100%) rename trunk/arch/arm/{plat-spear/include/plat => mach-spear/include/mach}/debug-macro.S (100%) rename trunk/arch/arm/{mach-spear6xx => mach-spear}/include/mach/irqs.h (51%) rename trunk/arch/arm/{mach-spear3xx => mach-spear}/include/mach/misc_regs.h (90%) create mode 100644 trunk/arch/arm/mach-spear/include/mach/spear.h rename trunk/arch/arm/{plat-spear/include/plat => mach-spear/include/mach}/timex.h (100%) rename trunk/arch/arm/{plat-spear/include/plat => mach-spear/include/mach}/uncompress.h (100%) rename trunk/arch/arm/{plat-spear => mach-spear}/pl080.c (100%) rename trunk/arch/arm/{plat-spear/include/plat => mach-spear}/pl080.h (100%) rename trunk/arch/arm/{mach-spear13xx => mach-spear}/platsmp.c (99%) rename trunk/arch/arm/{plat-spear => mach-spear}/restart.c (90%) rename trunk/arch/arm/{mach-spear13xx => mach-spear}/spear1310.c (59%) rename trunk/arch/arm/{mach-spear13xx => mach-spear}/spear1340.c (82%) rename trunk/arch/arm/{mach-spear13xx => mach-spear}/spear13xx.c (69%) rename trunk/arch/arm/{mach-spear3xx => mach-spear}/spear300.c (98%) rename trunk/arch/arm/{mach-spear3xx => mach-spear}/spear310.c (98%) rename trunk/arch/arm/{mach-spear3xx => mach-spear}/spear320.c (97%) rename trunk/arch/arm/{mach-spear3xx => mach-spear}/spear3xx.c (88%) rename trunk/arch/arm/{mach-spear6xx => mach-spear}/spear6xx.c (93%) rename trunk/arch/arm/{plat-spear => mach-spear}/time.c (99%) delete mode 100644 trunk/arch/arm/mach-spear13xx/Kconfig delete mode 100644 trunk/arch/arm/mach-spear13xx/Makefile delete mode 100644 trunk/arch/arm/mach-spear13xx/include/mach/debug-macro.S delete mode 100644 trunk/arch/arm/mach-spear13xx/include/mach/dma.h delete mode 100644 trunk/arch/arm/mach-spear13xx/include/mach/hardware.h delete mode 100644 trunk/arch/arm/mach-spear13xx/include/mach/irqs.h delete mode 100644 trunk/arch/arm/mach-spear13xx/include/mach/spear.h delete mode 100644 trunk/arch/arm/mach-spear13xx/include/mach/timex.h delete mode 100644 trunk/arch/arm/mach-spear13xx/include/mach/uncompress.h delete mode 100644 trunk/arch/arm/mach-spear3xx/Kconfig delete mode 100644 trunk/arch/arm/mach-spear3xx/Makefile delete mode 100644 trunk/arch/arm/mach-spear3xx/Makefile.boot delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/debug-macro.S delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/generic.h delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/hardware.h delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/irqs.h delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/spear.h delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/timex.h delete mode 100644 trunk/arch/arm/mach-spear3xx/include/mach/uncompress.h delete mode 100644 trunk/arch/arm/mach-spear6xx/Kconfig delete mode 100644 trunk/arch/arm/mach-spear6xx/Makefile delete mode 100644 trunk/arch/arm/mach-spear6xx/Makefile.boot delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/debug-macro.S delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/generic.h delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/hardware.h delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/misc_regs.h delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/spear.h delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/timex.h delete mode 100644 trunk/arch/arm/mach-spear6xx/include/mach/uncompress.h delete mode 100644 trunk/arch/arm/mach-tegra/board-dt-tegra114.c delete mode 100644 trunk/arch/arm/mach-tegra/board-dt-tegra30.c rename trunk/arch/arm/mach-tegra/{board-dt-tegra20.c => tegra.c} (74%) create mode 100644 trunk/arch/arm/mach-tegra/tegra114_speedo.c delete mode 100644 trunk/arch/arm/plat-spear/Kconfig delete mode 100644 trunk/arch/arm/plat-spear/Makefile create mode 100644 trunk/drivers/clk/clk-axi-clkgen.c create mode 100644 trunk/drivers/clk/clk-composite.c create mode 100644 trunk/drivers/clk/sunxi/Makefile create mode 100644 trunk/drivers/clk/sunxi/clk-factors.c create mode 100644 trunk/drivers/clk/sunxi/clk-factors.h create mode 100644 trunk/drivers/clk/sunxi/clk-sunxi.c create mode 100644 trunk/drivers/clk/tegra/clk-tegra114.c rename trunk/{arch/arm/mach-exynos/mct.c => drivers/clocksource/exynos_mct.c} (67%) rename trunk/{arch/arm/mach-mvebu => drivers/irqchip}/irq-armada-370-xp.c (89%) rename trunk/{arch/arm/mach-s3c24xx/irq.c => drivers/irqchip/irq-s3c24xx.c} (75%) rename trunk/firmware/{intel => qlogic}/sd7220.fw.ihex (100%) create mode 100644 trunk/include/linux/clk/sunxi.h mode change 100755 => 100644 trunk/include/sound/max98090.h create mode 100644 trunk/include/video/omap-panel-data.h delete mode 100644 trunk/include/video/omap-panel-generic-dpi.h delete mode 100644 trunk/include/video/omap-panel-n8x0.h delete mode 100644 trunk/include/video/omap-panel-nokia-dsi.h delete mode 100644 trunk/include/video/omap-panel-picodlp.h delete mode 100644 trunk/include/video/omap-panel-tfp410.h mode change 100755 => 100644 trunk/sound/soc/codecs/max98090.c mode change 100755 => 100644 trunk/sound/soc/codecs/max98090.h diff --git a/[refs] b/[refs] index fedfafa26ff0..57f408d9c78d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 08a48be32ff31d38bcfec7d210c954cb62fd5cd7 +refs/heads/master: 0592c2189ece16f3e0c5a56245634aba93d0c9dd diff --git a/trunk/Documentation/arm/sunxi/clocks.txt b/trunk/Documentation/arm/sunxi/clocks.txt new file mode 100644 index 000000000000..e09a88aa3136 --- /dev/null +++ b/trunk/Documentation/arm/sunxi/clocks.txt @@ -0,0 +1,56 @@ +Frequently asked questions about the sunxi clock system +======================================================= + +This document contains useful bits of information that people tend to ask +about the sunxi clock system, as well as accompanying ASCII art when adequate. + +Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the + system? + +A: The 24MHz oscillator allows gating to save power. Indeed, if gated + carelessly the system would stop functioning, but with the right + steps, one can gate it and keep the system running. Consider this + simplified suspend example: + + While the system is operational, you would see something like + + 24MHz 32kHz + | + PLL1 + \ + \_ CPU Mux + | + [CPU] + + When you are about to suspend, you switch the CPU Mux to the 32kHz + oscillator: + + 24Mhz 32kHz + | | + PLL1 | + / + CPU Mux _/ + | + [CPU] + + Finally you can gate the main oscillator + + 32kHz + | + | + / + CPU Mux _/ + | + [CPU] + +Q: Were can I learn more about the sunxi clocks? + +A: The linux-sunxi wiki contains a page documenting the clock registers, + you can find it at + + http://linux-sunxi.org/A10/CCM + + The authoritative source for information at this time is the ccmu driver + released by Allwinner, you can find it at + + https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu diff --git a/trunk/Documentation/clk.txt b/trunk/Documentation/clk.txt index 1943fae014fd..4274a546eb57 100644 --- a/trunk/Documentation/clk.txt +++ b/trunk/Documentation/clk.txt @@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw) }; Below is a matrix detailing which clk_ops are mandatory based upon the -hardware capbilities of that clock. A cell marked as "y" means +hardware capabilities of that clock. A cell marked as "y" means mandatory, a cell marked as "n" implies that either including that -callback is invalid or otherwise uneccesary. Empty cells are either +callback is invalid or otherwise unnecessary. Empty cells are either optional or must be evaluated on a case-by-case basis. clock hardware characteristics diff --git a/trunk/Documentation/devicetree/bindings/arm/primecell.txt b/trunk/Documentation/devicetree/bindings/arm/primecell.txt index 64fc82bc8928..0df6acacfaea 100644 --- a/trunk/Documentation/devicetree/bindings/arm/primecell.txt +++ b/trunk/Documentation/devicetree/bindings/arm/primecell.txt @@ -16,14 +16,31 @@ Optional properties: - clocks : From common clock binding. First clock is phandle to clock for apb pclk. Additional clocks are optional and specific to those peripherals. - clock-names : From common clock binding. Shall be "apb_pclk" for first clock. +- dmas : From common DMA binding. If present, refers to one or more dma channels. +- dma-names : From common DMA binding, needs to match the 'dmas' property. + Devices with exactly one receive and transmit channel shall name + these "rx" and "tx", respectively. +- pinctrl- : Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt +- pinctrl-names : Names corresponding to the numbered pinctrl states +- interrupts : one or more interrupt specifiers +- interrupt-names : names corresponding to the interrupts properties Example: serial@fff36000 { compatible = "arm,pl011", "arm,primecell"; arm,primecell-periphid = <0x00341011>; + clocks = <&pclk>; clock-names = "apb_pclk"; - + + dmas = <&dma-controller 4>, <&dma-controller 5>; + dma-names = "rx", "tx"; + + pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; + pinctrl-names = "default","sleep"; + + interrupts = <0 11 0x4>; }; diff --git a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index b5846e21cc2e..1608a54e90e1 100644 --- a/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/trunk/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -1,19 +1,84 @@ NVIDIA Tegra Power Management Controller (PMC) -Properties: +The PMC block interacts with an external Power Management Unit. The PMC +mostly controls the entry and exit of the system from different sleep +modes. It provides power-gating controllers for SoC and CPU power-islands. + +Required properties: - name : Should be pmc - compatible : Should contain "nvidia,tegra-pmc". - reg : Offset and length of the register set for the device +- clocks : Must contain an entry for each entry in clock-names. +- clock-names : Must include the following entries: + "pclk" (The Tegra clock of that name), + "clk32k_in" (The 32KHz clock input to Tegra). + +Optional properties: - nvidia,invert-interrupt : If present, inverts the PMU interrupt signal. The PMU is an external Power Management Unit, whose interrupt output signal is fed into the PMC. This signal is optionally inverted, and then fed into the ARM GIC. The PMC is not involved in the detection or handling of this interrupt signal, merely its inversion. +- nvidia,suspend-mode : The suspend mode that the platform should use. + Valid values are 0, 1 and 2: + 0 (LP0): CPU + Core voltage off and DRAM in self-refresh + 1 (LP1): CPU voltage off and DRAM in self-refresh + 2 (LP2): CPU voltage off +- nvidia,core-power-req-active-high : Boolean, core power request active-high +- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high +- nvidia,combined-power-req : Boolean, combined power request for CPU & Core +- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC) + is enabled. + +Required properties when nvidia,suspend-mode is specified: +- nvidia,cpu-pwr-good-time : CPU power good time in uS. +- nvidia,cpu-pwr-off-time : CPU power off time in uS. +- nvidia,core-pwr-good-time : + Core power good time in uS. +- nvidia,core-pwr-off-time : Core power off time in uS. + +Required properties when nvidia,suspend-mode=<0>: +- nvidia,lp0-vec : Starting address and length of LP0 vector + The LP0 vector contains the warm boot code that is executed by AVP when + resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7 + processor and always being the first boot processor when chip is power on + or resume from deep sleep mode. When the system is resumed from the deep + sleep mode, the warm boot code will restore some PLLs, clocks and then + bring up CPU0 for resuming the system. Example: +/ SoC dts including file pmc@7000f400 { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car 110>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; nvidia,invert-interrupt; + nvidia,suspend-mode = <1>; + nvidia,cpu-pwr-good-time = <2000>; + nvidia,cpu-pwr-off-time = <100>; + nvidia,core-pwr-good-time = <3845 3845>; + nvidia,core-pwr-off-time = <458>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + nvidia,lp0-vec = <0xbdffd000 0x2000>; +}; + +/ Tegra board dts file +{ + ... + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + ... }; diff --git a/trunk/Documentation/devicetree/bindings/ata/pata-arasan.txt b/trunk/Documentation/devicetree/bindings/ata/pata-arasan.txt index 95ec7f825ede..2aff154be84e 100644 --- a/trunk/Documentation/devicetree/bindings/ata/pata-arasan.txt +++ b/trunk/Documentation/devicetree/bindings/ata/pata-arasan.txt @@ -6,6 +6,26 @@ Required properties: - interrupt-parent: Should be the phandle for the interrupt controller that services interrupts for this device - interrupt: Should contain the CF interrupt number +- clock-frequency: Interface clock rate, in Hz, one of + 25000000 + 33000000 + 40000000 + 50000000 + 66000000 + 75000000 + 100000000 + 125000000 + 150000000 + 166000000 + 200000000 + +Optional properties: +- arasan,broken-udma: if present, UDMA mode is unusable +- arasan,broken-mwdma: if present, MWDMA mode is unusable +- arasan,broken-pio: if present, PIO mode is unusable +- dmas: one DMA channel, as described in bindings/dma/dma.txt + required unless both UDMA and MWDMA mode are broken +- dma-names: the corresponding channel name, must be "data" Example: @@ -14,4 +34,6 @@ Example: reg = <0xfc000000 0x1000>; interrupt-parent = <&vic1>; interrupts = <12>; + dmas = <&dma-controller 23>; + dma-names = "data"; }; diff --git a/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt index 5ddb2e9efaaa..4b87ea1194e3 100644 --- a/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt +++ b/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt @@ -35,36 +35,83 @@ Required properties: Timing properties for child nodes. All are optional and default to 0. - - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds - - Chip-select signal timings corresponding to GPMC_CONFIG2: - - gpmc,cs-on: Assertion time - - gpmc,cs-rd-off: Read deassertion time - - gpmc,cs-wr-off: Write deassertion time - - ADV signal timings corresponding to GPMC_CONFIG3: - - gpmc,adv-on: Assertion time - - gpmc,adv-rd-off: Read deassertion time - - gpmc,adv-wr-off: Write deassertion time - - WE signals timings corresponding to GPMC_CONFIG4: - - gpmc,we-on: Assertion time - - gpmc,we-off: Deassertion time - - OE signals timings corresponding to GPMC_CONFIG4: - - gpmc,oe-on: Assertion time - - gpmc,oe-off: Deassertion time - - Access time and cycle time timings corresponding to GPMC_CONFIG5: - - gpmc,page-burst-access: Multiple access word delay - - gpmc,access: Start-cycle to first data valid delay - - gpmc,rd-cycle: Total read cycle time - - gpmc,wr-cycle: Total write cycle time + - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds + + Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2: + - gpmc,cs-on-ns: Assertion time + - gpmc,cs-rd-off-ns: Read deassertion time + - gpmc,cs-wr-off-ns: Write deassertion time + + ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3: + - gpmc,adv-on-ns: Assertion time + - gpmc,adv-rd-off-ns: Read deassertion time + - gpmc,adv-wr-off-ns: Write deassertion time + + WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: + - gpmc,we-on-ns Assertion time + - gpmc,we-off-ns: Deassertion time + + OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4: + - gpmc,oe-on-ns: Assertion time + - gpmc,oe-off-ns: Deassertion time + + Access time and cycle time timings (in nanoseconds) corresponding to + GPMC_CONFIG5: + - gpmc,page-burst-access-ns: Multiple access word delay + - gpmc,access-ns: Start-cycle to first data valid delay + - gpmc,rd-cycle-ns: Total read cycle time + - gpmc,wr-cycle-ns: Total write cycle time + - gpmc,bus-turnaround-ns: Turn-around time between successive accesses + - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses + - gpmc,clk-activation-ns: GPMC clock activation time + - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid + data + +Boolean timing parameters. If property is present parameter enabled and +disabled if omitted: + - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock + - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock + - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive + accesses to a different CS + - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive + accesses to the same CS + - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock + - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock + - gpmc,time-para-granularity: Multiply all access times by 2 The following are only applicable to OMAP3+ and AM335x: - - gpmc,wr-access - - gpmc,wr-data-mux-bus - + - gpmc,wr-access-ns: In synchronous write mode, for single or + burst accesses, defines the number of + GPMC_FCLK cycles from start access time + to the GPMC_CLK rising edge used by the + memory device for the first data capture. + - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies + the time when the first data is driven on + the address-data bus. + +GPMC chip-select settings properties for child nodes. All are optional. + +- gpmc,burst-length Page/burst length. Must be 4, 8 or 16. +- gpmc,burst-wrap Enables wrap bursting +- gpmc,burst-read Enables read page/burst mode +- gpmc,burst-write Enables write page/burst mode +- gpmc,device-nand Device is NAND +- gpmc,device-width Total width of device(s) connected to a GPMC + chip-select in bytes. The GPMC supports 8-bit + and 16-bit devices and so this property must be + 1 or 2. +- gpmc,mux-add-data Address and data multiplexing configuration. + Valid values are 1 for address-address-data + multiplexing mode and 2 for address-data + multiplexing mode. +- gpmc,sync-read Enables synchronous read. Defaults to asynchronous + is this is not set. +- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous + is this is not set. +- gpmc,wait-pin Wait-pin used by client. Must be less than + "gpmc,num-waitpins". +- gpmc,wait-on-read Enables wait monitoring on reads. +- gpmc,wait-on-write Enables wait monitoring on writes. Example for an AM33xx board: diff --git a/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt b/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt new file mode 100644 index 000000000000..028b493e97ff --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/clock/axi-clkgen.txt @@ -0,0 +1,22 @@ +Binding for the axi-clkgen clock generator + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be "adi,axi-clkgen". +- #clock-cells : from common clock binding; Should always be set to 0. +- reg : Address and length of the axi-clkgen register set. +- clocks : Phandle and clock specifier for the parent clock. + +Optional properties: +- clock-output-names : From common clock binding. + +Example: + clock@0xff000000 { + compatible = "adi,axi-clkgen"; + #clock-cells = <0>; + reg = <0xff000000 0x1000>; + clocks = <&osc 1>; + }; diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt new file mode 100644 index 000000000000..d6cb083b90a2 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt @@ -0,0 +1,303 @@ +NVIDIA Tegra114 Clock And Reset Controller + +This binding uses the common clock binding: +Documentation/devicetree/bindings/clock/clock-bindings.txt + +The CAR (Clock And Reset) Controller on Tegra is the HW module responsible +for muxing and gating Tegra's clocks, and setting their rates. + +Required properties : +- compatible : Should be "nvidia,tegra114-car" +- reg : Should contain CAR registers location and length +- clocks : Should contain phandle and clock specifiers for two clocks: + the 32 KHz "32k_in", and the board-specific oscillator "osc". +- #clock-cells : Should be 1. + In clock consumers, this cell represents the clock ID exposed by the CAR. + + The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + registers. These IDs often match those in the CAR's RST_DEVICES registers, + but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + this case, those clocks are assigned IDs above 160 in order to highlight + this issue. Implementations that interpret these clock IDs as bit values + within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + explicitly handle these special cases. + + The balance of the clocks controlled by the CAR are assigned IDs of 160 and + above. + + 0 unassigned + 1 unassigned + 2 unassigned + 3 unassigned + 4 rtc + 5 timer + 6 uarta + 7 unassigned (register bit affects uartb and vfir) + 8 unassigned + 9 sdmmc2 + 10 unassigned (register bit affects spdif_in and spdif_out) + 11 i2s1 + 12 i2c1 + 13 ndflash + 14 sdmmc1 + 15 sdmmc4 + 16 unassigned + 17 pwm + 18 i2s2 + 19 epp + 20 unassigned (register bit affects vi and vi_sensor) + 21 2d + 22 usbd + 23 isp + 24 3d + 25 unassigned + 26 disp2 + 27 disp1 + 28 host1x + 29 vcp + 30 i2s0 + 31 unassigned + + 32 unassigned + 33 unassigned + 34 apbdma + 35 unassigned + 36 kbc + 37 unassigned + 38 unassigned + 39 unassigned (register bit affects fuse and fuse_burn) + 40 kfuse + 41 sbc1 + 42 nor + 43 unassigned + 44 sbc2 + 45 unassigned + 46 sbc3 + 47 i2c5 + 48 dsia + 49 unassigned + 50 mipi + 51 hdmi + 52 csi + 53 unassigned + 54 i2c2 + 55 uartc + 56 mipi-cal + 57 emc + 58 usb2 + 59 usb3 + 60 msenc + 61 vde + 62 bsea + 63 bsev + + 64 unassigned + 65 uartd + 66 unassigned + 67 i2c3 + 68 sbc4 + 69 sdmmc3 + 70 unassigned + 71 owr + 72 afi + 73 csite + 74 unassigned + 75 unassigned + 76 la + 77 trace + 78 soc_therm + 79 dtv + 80 ndspeed + 81 i2cslow + 82 dsib + 83 tsec + 84 unassigned + 85 unassigned + 86 unassigned + 87 unassigned + 88 unassigned + 89 xusb_host + 90 unassigned + 91 msenc + 92 csus + 93 unassigned + 94 unassigned + 95 unassigned (bit affects xusb_dev and xusb_dev_src) + + 96 unassigned + 97 unassigned + 98 unassigned + 99 mselect + 100 tsensor + 101 i2s3 + 102 i2s4 + 103 i2c4 + 104 sbc5 + 105 sbc6 + 106 d_audio + 107 apbif + 108 dam0 + 109 dam1 + 110 dam2 + 111 hda2codec_2x + 112 unassigned + 113 audio0_2x + 114 audio1_2x + 115 audio2_2x + 116 audio3_2x + 117 audio4_2x + 118 spdif_2x + 119 actmon + 120 extern1 + 121 extern2 + 122 extern3 + 123 unassigned + 124 unassigned + 125 hda + 126 unassigned + 127 se + + 128 hda2hdmi + 129 unassigned + 130 unassigned + 131 unassigned + 132 unassigned + 133 unassigned + 134 unassigned + 135 unassigned + 136 unassigned + 137 unassigned + 138 unassigned + 139 unassigned + 140 unassigned + 141 unassigned + 142 unassigned + 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src, + xusb_host_src and xusb_ss_src) + 144 cilab + 145 cilcd + 146 cile + 147 dsialp + 148 dsiblp + 149 unassigned + 150 dds + 151 unassigned + 152 dp2 + 153 amx + 154 adx + 155 unassigned (bit affects dfll_ref and dfll_soc) + 156 xusb_ss + + 192 uartb + 193 vfir + 194 spdif_in + 195 spdif_out + 196 vi + 197 vi_sensor + 198 fuse + 199 fuse_burn + 200 clk_32k + 201 clk_m + 202 clk_m_div2 + 203 clk_m_div4 + 204 pll_ref + 205 pll_c + 206 pll_c_out1 + 207 pll_c2 + 208 pll_c3 + 209 pll_m + 210 pll_m_out1 + 211 pll_p + 212 pll_p_out1 + 213 pll_p_out2 + 214 pll_p_out3 + 215 pll_p_out4 + 216 pll_a + 217 pll_a_out0 + 218 pll_d + 219 pll_d_out0 + 220 pll_d2 + 221 pll_d2_out0 + 222 pll_u + 223 pll_u_480M + 224 pll_u_60M + 225 pll_u_48M + 226 pll_u_12M + 227 pll_x + 228 pll_x_out0 + 229 pll_re_vco + 230 pll_re_out + 231 pll_e_out0 + 232 spdif_in_sync + 233 i2s0_sync + 234 i2s1_sync + 235 i2s2_sync + 236 i2s3_sync + 237 i2s4_sync + 238 vimclk_sync + 239 audio0 + 240 audio1 + 241 audio2 + 242 audio3 + 243 audio4 + 244 spdif + 245 clk_out_1 + 246 clk_out_2 + 247 clk_out_3 + 248 blink + 252 xusb_host_src + 253 xusb_falcon_src + 254 xusb_fs_src + 255 xusb_ss_src + 256 xusb_dev_src + 257 xusb_dev + 258 xusb_hs_src + 259 sclk + 260 hclk + 261 pclk + 262 cclk_g + 263 cclk_lp + 264 dfll_ref + 265 dfll_soc + +Example SoC include file: + +/ { + tegra_car: clock { + compatible = "nvidia,tegra114-car"; + reg = <0x60006000 0x1000>; + #clock-cells = <1>; + }; + + usb@c5004000 { + clocks = <&tegra_car 58>; /* usb2 */ + }; +}; + +Example board file: + +/ { + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + osc: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <12000000>; + }; + + clk_32k: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + &tegra_car { + clocks = <&clk_32k> <&osc>; + }; +}; diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt index 0921fac73528..e885680f6b45 100644 --- a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt +++ b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt @@ -120,8 +120,8 @@ Required properties : 90 clk_d 91 unassigned 92 sus - 93 cdev1 - 94 cdev2 + 93 cdev2 + 94 cdev1 95 unassigned 96 uart2 diff --git a/trunk/Documentation/devicetree/bindings/clock/sunxi.txt b/trunk/Documentation/devicetree/bindings/clock/sunxi.txt new file mode 100644 index 000000000000..20b8479c2760 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/clock/sunxi.txt @@ -0,0 +1,44 @@ +Device Tree Clock bindings for arch-sunxi + +This binding uses the common clock binding[1]. + +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible : shall be one of the following: + "allwinner,sun4i-osc-clk" - for a gatable oscillator + "allwinner,sun4i-pll1-clk" - for the main PLL clock + "allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock + "allwinner,sun4i-axi-clk" - for the AXI clock + "allwinner,sun4i-ahb-clk" - for the AHB clock + "allwinner,sun4i-apb0-clk" - for the APB0 clock + "allwinner,sun4i-apb1-clk" - for the APB1 clock + "allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing + +Required properties for all clocks: +- reg : shall be the control register address for the clock. +- clocks : shall be the input parent clock(s) phandle for the clock +- #clock-cells : from common clock binding; shall be set to 0. + +For example: + +osc24M: osc24M@01c20050 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-osc-clk"; + reg = <0x01c20050 0x4>; + clocks = <&osc24M_fixed>; +}; + +pll1: pll1@01c20000 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-pll1-clk"; + reg = <0x01c20000 0x4>; + clocks = <&osc24M>; +}; + +cpu: cpu@01c20054 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-cpu-clk"; + reg = <0x01c20054 0x4>; + clocks = <&osc32k>, <&osc24M>, <&pll1>; +}; diff --git a/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt new file mode 100644 index 000000000000..c54c5a9a2a90 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt @@ -0,0 +1,53 @@ +Samsung S3C24XX Interrupt Controllers + +The S3C24XX SoCs contain a custom set of interrupt controllers providing a +varying number of interrupt sources. The set consists of a main- and sub- +controller and on newer SoCs even a second main controller. + +Required properties: +- compatible: Compatible property value should be "samsung,s3c2410-irq" + for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. + +- reg: Physical base address of the controller and length of memory mapped + region. + +- interrupt-controller : Identifies the node as an interrupt controller + +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 4 and interrupt descriptor shall + have the following format: + + + ctrl_num contains the controller to use: + - 0 ... main controller + - 1 ... sub controller + - 2 ... second main controller on s3c2416 and s3c2450 + parent_irq contains the parent bit in the main controller and will be + ignored in main controllers + ctrl_irq contains the interrupt bit of the controller + type contains the trigger type to use + +Example: + + interrupt-controller@4a000000 { + compatible = "samsung,s3c2410-irq"; + reg = <0x4a000000 0x100>; + interrupt-controller; + #interrupt-cells=<4>; + }; + + [...] + + serial@50000000 { + compatible = "samsung,s3c2410-uart"; + reg = <0x50000000 0x4000>; + interrupt-parent = <&subintc>; + interrupts = <1 28 0 4>, <1 28 1 4>; + }; + + rtc@57000000 { + compatible = "samsung,s3c2410-rtc"; + reg = <0x57000000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 30 0 3>, <0 8 0 3>; + }; diff --git a/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt new file mode 100644 index 000000000000..420b3ab18890 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt @@ -0,0 +1,98 @@ +Device tree bindings for NOR flash connect to TI GPMC + +NOR flash connected to the TI GPMC (found on OMAP boards) are represented as +child nodes of the GPMC controller with a name of "nor". + +All timing relevant properties as well as generic GPMC child properties are +explained in a separate documents. Please refer to +Documentation/devicetree/bindings/bus/ti-gpmc.txt + +Required properties: +- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and + 16-bit devices and so must be either 1 or 2 bytes. +- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt +- gpmc,cs-on-ns: Chip-select assertion time +- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads +- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes +- gpmc,oe-on-ns: Output-enable assertion time +- gpmc,oe-off-ns: Output-enable de-assertion time +- gpmc,we-on-ns Write-enable assertion time +- gpmc,we-off-ns: Write-enable de-assertion time +- gpmc,access-ns: Start cycle to first data capture (read access) +- gpmc,rd-cycle-ns: Total read cycle time +- gpmc,wr-cycle-ns: Total write cycle time +- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt +- reg: Chip-select, base address (relative to chip-select) + and size of NOR flash. Note that base address will be + typically 0 as this is the start of the chip-select. + +Optional properties: +- gpmc,XXX Additional GPMC timings and settings parameters. See + Documentation/devicetree/bindings/bus/ti-gpmc.txt + +Optional properties for partiton table parsing: +- #address-cells: should be set to 1 +- #size-cells: should be set to 1 + +Example: + +gpmc: gpmc@6e000000 { + compatible = "ti,omap3430-gpmc", "simple-bus"; + ti,hwmods = "gpmc"; + reg = <0x6e000000 0x1000>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0 0 0x10000000 0x08000000>; + + nor@0,0 { + compatible = "cfi-flash"; + linux,mtd-name= "intel,pf48f6000m0y1be"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0 0x08000000>; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <186>; + gpmc,cs-wr-off-ns = <186>; + gpmc,adv-on-ns = <12>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <54>; + gpmc,oe-off-ns = <168>; + gpmc,we-on-ns = <54>; + gpmc,we-off-ns = <168>; + gpmc,rd-cycle-ns = <186>; + gpmc,wr-cycle-ns = <186>; + gpmc,access-ns = <114>; + gpmc,page-burst-access-ns = <6>; + gpmc,bus-turnaround-ns = <12>; + gpmc,cycle2cycle-delay-ns = <18>; + gpmc,wr-data-mux-bus-ns = <90>; + gpmc,wr-access-ns = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + partition@0 { + label = "bootloader-nor"; + reg = <0 0x40000>; + }; + partition@0x40000 { + label = "params-nor"; + reg = <0x40000 0x40000>; + }; + partition@0x80000 { + label = "kernel-nor"; + reg = <0x80000 0x200000>; + }; + partition@0x280000 { + label = "filesystem-nor"; + reg = <0x240000 0x7d80000>; + }; + }; +}; diff --git a/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt index deec9da224a2..b7529424ac88 100644 --- a/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt +++ b/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt @@ -10,6 +10,8 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt Required properties: - reg: The CS line the peripheral is connected to + - gpmc,device-width Width of the ONENAND device connected to the GPMC + in bytes. Must be 1 or 2. Optional properties: @@ -34,6 +36,7 @@ Example for an OMAP3430 board: onenand@0 { reg = <0 0 0>; /* CS0, offset 0 */ + gpmc,device-width = <2>; #address-cells = <1>; #size-cells = <1>; diff --git a/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt b/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt new file mode 100644 index 000000000000..24cb4e46f675 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt @@ -0,0 +1,97 @@ +Device tree bindings for Ethernet chip connected to TI GPMC + +Besides being used to interface with external memory devices, the +General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices +such as ethernet controllers to processors using the TI GPMC as a data bus. + +Ethernet controllers connected to TI GPMC are represented as child nodes of +the GPMC controller with an "ethernet" name. + +All timing relevant properties as well as generic GPMC child properties are +explained in a separate documents. Please refer to +Documentation/devicetree/bindings/bus/ti-gpmc.txt + +For the properties relevant to the ethernet controller connected to the GPMC +refer to the binding documentation of the device. For example, the documentation +for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt + +Child nodes need to specify the GPMC bus address width using the "bank-width" +property but is possible that an ethernet controller also has a property to +specify the I/O registers address width. Even when the GPMC has a maximum 16-bit +address width, it supports devices with 32-bit word registers. +For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an +OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;". + +Required properties: +- bank-width: Address width of the device in bytes. GPMC supports 8-bit + and 16-bit devices and so must be either 1 or 2 bytes. +- compatible: Compatible string property for the ethernet child device. +- gpmc,cs-on: Chip-select assertion time +- gpmc,cs-rd-off: Chip-select de-assertion time for reads +- gpmc,cs-wr-off: Chip-select de-assertion time for writes +- gpmc,oe-on: Output-enable assertion time +- gpmc,oe-off Output-enable de-assertion time +- gpmc,we-on: Write-enable assertion time +- gpmc,we-off: Write-enable de-assertion time +- gpmc,access: Start cycle to first data capture (read access) +- gpmc,rd-cycle: Total read cycle time +- gpmc,wr-cycle: Total write cycle time +- reg: Chip-select, base address (relative to chip-select) + and size of the memory mapped for the device. + Note that base address will be typically 0 as this + is the start of the chip-select. + +Optional properties: +- gpmc,XXX Additional GPMC timings and settings parameters. See + Documentation/devicetree/bindings/bus/ti-gpmc.txt + +Example: + +gpmc: gpmc@6e000000 { + compatible = "ti,omap3430-gpmc"; + ti,hwmods = "gpmc"; + reg = <0x6e000000 0x1000>; + interrupts = <20>; + gpmc,num-cs = <8>; + gpmc,num-waitpins = <4>; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <5 0 0x2c000000 0x1000000>; + + ethernet@5,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <5 0 0xff>; + bank-width = <2>; + + gpmc,mux-add-data; + gpmc,cs-on = <0>; + gpmc,cs-rd-off = <186>; + gpmc,cs-wr-off = <186>; + gpmc,adv-on = <12>; + gpmc,adv-rd-off = <48>; + gpmc,adv-wr-off = <48>; + gpmc,oe-on = <54>; + gpmc,oe-off = <168>; + gpmc,we-on = <54>; + gpmc,we-off = <168>; + gpmc,rd-cycle = <186>; + gpmc,wr-cycle = <186>; + gpmc,access = <114>; + gpmc,page-burst-access = <6>; + gpmc,bus-turnaround = <12>; + gpmc,cycle2cycle-delay = <18>; + gpmc,wr-data-mux-bus = <90>; + gpmc,wr-access = <186>; + gpmc,cycle2cycle-samecsen; + gpmc,cycle2cycle-diffcsen; + + interrupt-parent = <&gpio6>; + interrupts = <16>; + vmmc-supply = <&vddvario>; + vmmc_aux-supply = <&vdd33a>; + reg-io-width = <4>; + + smsc,save-mac-address; + }; +}; diff --git a/trunk/Documentation/devicetree/bindings/serial/pl011.txt b/trunk/Documentation/devicetree/bindings/serial/pl011.txt new file mode 100644 index 000000000000..5d2e840ae65c --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/serial/pl011.txt @@ -0,0 +1,17 @@ +* ARM AMBA Primecell PL011 serial UART + +Required properties: +- compatible: must be "arm,primecell", "arm,pl011" +- reg: exactly one register range with length 0x1000 +- interrupts: exactly one interrupt specifier + +Optional properties: +- pinctrl: When present, must have one state named "sleep" + and one state named "default" +- clocks: When present, must refer to exactly one clock named + "apb_pclk" +- dmas: When present, may have one or two dma channels. + The first one must be named "rx", the second one + must be named "tx". + +See also bindings/arm/primecell.txt diff --git a/trunk/Documentation/devicetree/bindings/spi/spi_pl022.txt b/trunk/Documentation/devicetree/bindings/spi/spi_pl022.txt index f158fd31cfda..22ed6797216d 100644 --- a/trunk/Documentation/devicetree/bindings/spi/spi_pl022.txt +++ b/trunk/Documentation/devicetree/bindings/spi/spi_pl022.txt @@ -16,6 +16,11 @@ Optional properties: device will be suspended immediately - pl022,rt : indicates the controller should run the message pump with realtime priority to minimise the transfer latency on the bus (boolean) +- dmas : Two or more DMA channel specifiers following the convention outlined + in bindings/dma/dma.txt +- dma-names: Names for the dma channels, if present. There must be at + least one channel named "tx" for transmit and named "rx" for + receive. SPI slave nodes must be children of the SPI master node and can @@ -32,3 +37,34 @@ contain the following properties. - pl022,wait-state : Microwire interface: Wait state - pl022,duplex : Microwire interface: Full/Half duplex + +Example: + + spi@e0100000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xe0100000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 31 0x4>; + dmas = <&dma-controller 23 1>, + <&dma-controller 24 0>; + dma-names = "rx", "tx"; + + m25p80@1 { + compatible = "st,m25p80"; + reg = <1>; + spi-max-frequency = <12000000>; + spi-cpol; + spi-cpha; + pl022,hierarchy = <0>; + pl022,interface = <0>; + pl022,slave-tx-disable; + pl022,com-mode = <0x2>; + pl022,rx-level-trig = <0>; + pl022,tx-level-trig = <0>; + pl022,ctrl-len = <0x11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + }; + }; + diff --git a/trunk/Documentation/devicetree/bindings/timer/arm,sp804.txt b/trunk/Documentation/devicetree/bindings/timer/arm,sp804.txt new file mode 100644 index 000000000000..5cd8eee74af1 --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/timer/arm,sp804.txt @@ -0,0 +1,29 @@ +ARM sp804 Dual Timers +--------------------------------------- + +Required properties: +- compatible: Should be "arm,sp804" & "arm,primecell" +- interrupts: Should contain the list of Dual Timer interrupts. This is the + interrupt for timer 1 and timer 2. In the case of a single entry, it is + the combined interrupt or if "arm,sp804-has-irq" is present that + specifies which timer interrupt is connected. +- reg: Should contain location and length for dual timer register. +- clocks: clocks driving the dual timer hardware. This list should be 1 or 3 + clocks. With 3 clocks, the order is timer0 clock, timer1 clock, + apb_pclk. A single clock can also be specified if the same clock is + used for all clock inputs. + +Optional properties: +- arm,sp804-has-irq = <#>: In the case of only 1 timer irq line connected, this + specifies if the irq connection is for timer 1 or timer 2. A value of 1 + or 2 should be used. + +Example: + + timer0: timer@fc800000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0xfc800000 0x1000>; + interrupts = <0 0 4>, <0 1 4>; + clocks = <&timclk1 &timclk2 &pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; diff --git a/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt new file mode 100644 index 000000000000..cb47bfbcaeea --- /dev/null +++ b/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt @@ -0,0 +1,68 @@ +Samsung's Multi Core Timer (MCT) + +The Samsung's Multi Core Timer (MCT) module includes two main blocks, the +global timer and CPU local timers. The global timer is a 64-bit free running +up-counter and can generate 4 interrupts when the counter reaches one of the +four preset counter values. The CPU local timers are 32-bit free running +down-counters and generate an interrupt when the counter expires. There is +one CPU local timer instantiated in MCT for every CPU in the system. + +Required properties: + +- compatible: should be "samsung,exynos4210-mct". + (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct. + (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct. + +- reg: base address of the mct controller and length of the address space + it occupies. + +- interrupts: the list of interrupts generated by the controller. The following + should be the order of the interrupts specified. The local timer interrupts + should be specified after the four global timer interrupts have been + specified. + + 0: Global Timer Interrupt 0 + 1: Global Timer Interrupt 1 + 2: Global Timer Interrupt 2 + 3: Global Timer Interrupt 3 + 4: Local Timer Interrupt 0 + 5: Local Timer Interrupt 1 + 6: .. + 7: .. + i: Local Timer Interrupt n + +Example 1: In this example, the system uses only the first global timer + interrupt generated by MCT and the remaining three global timer + interrupts are unused. Two local timer interrupts have been + specified. + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>, + <0 42 0>, <0 48 0>; + }; + +Example 2: In this example, the MCT global and local timer interrupts are + connected to two seperate interrupt controllers. Hence, an + interrupt-map is created to map the interrupts to the respective + interrupt controllers. + + mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &combiner 23 3>, + <0x4 0 &gic 0 120 0>, + <0x5 0 &gic 0 121 0>; + }; + }; diff --git a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt index 4499bd948860..95731a08f257 100644 --- a/trunk/Documentation/sound/alsa/ALSA-Configuration.txt +++ b/trunk/Documentation/sound/alsa/ALSA-Configuration.txt @@ -890,9 +890,8 @@ Prior to version 0.9.0rc4 options had a 'snd_' prefix. This was removed. enable_msi - Enable Message Signaled Interrupt (MSI) (default = off) power_save - Automatic power-saving timeout (in second, 0 = disable) - power_save_controller - Support runtime D3 of HD-audio controller - (-1 = on for supported chip (default), false = off, - true = force to on even for unsupported hardware) + power_save_controller - Reset HD-audio controller in power-saving mode + (default = on) align_buffer_size - Force rounding of buffer/period sizes to multiples of 128 bytes. This is more efficient in terms of memory access but isn't required by the HDA spec and prevents diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 74e58a4d035b..836a6183c37f 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -5065,9 +5065,8 @@ S: Maintained F: drivers/net/ethernet/marvell/sk* MARVELL LIBERTAS WIRELESS DRIVER -M: Dan Williams L: libertas-dev@lists.infradead.org -S: Maintained +S: Orphan F: drivers/net/wireless/libertas/ MARVELL MV643XX ETHERNET DRIVER @@ -5569,6 +5568,7 @@ F: include/uapi/linux/if_* F: include/uapi/linux/netdevice.h NETXEN (1/10) GbE SUPPORT +M: Manish Chopra M: Sony Chacko M: Rajesh Borundia L: netdev@vger.kernel.org diff --git a/trunk/Makefile b/trunk/Makefile index 58a165b02af1..6db672b15bda 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,7 +1,7 @@ VERSION = 3 PATCHLEVEL = 9 SUBLEVEL = 0 -EXTRAVERSION = -rc5 +EXTRAVERSION = -rc6 NAME = Unicycling Gorilla # *DOCUMENTATION* diff --git a/trunk/arch/alpha/Makefile b/trunk/arch/alpha/Makefile index 4759fe751aa1..2cc3cc519c54 100644 --- a/trunk/arch/alpha/Makefile +++ b/trunk/arch/alpha/Makefile @@ -12,7 +12,7 @@ NM := $(NM) -B LDFLAGS_vmlinux := -static -N #-relax CHECKFLAGS += -D__alpha__ -m64 -cflags-y := -pipe -mno-fp-regs -ffixed-8 -msmall-data +cflags-y := -pipe -mno-fp-regs -ffixed-8 cflags-y += $(call cc-option, -fno-jump-tables) cpuflags-$(CONFIG_ALPHA_EV4) := -mcpu=ev4 diff --git a/trunk/arch/alpha/include/asm/floppy.h b/trunk/arch/alpha/include/asm/floppy.h index 46cefbd50e73..bae97eb19d26 100644 --- a/trunk/arch/alpha/include/asm/floppy.h +++ b/trunk/arch/alpha/include/asm/floppy.h @@ -26,7 +26,7 @@ #define fd_disable_irq() disable_irq(FLOPPY_IRQ) #define fd_cacheflush(addr,size) /* nothing */ #define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt,\ - IRQF_DISABLED, "floppy", NULL) + 0, "floppy", NULL) #define fd_free_irq() free_irq(FLOPPY_IRQ, NULL) #ifdef CONFIG_PCI diff --git a/trunk/arch/alpha/kernel/irq.c b/trunk/arch/alpha/kernel/irq.c index 2872accd2215..7b2be251c30f 100644 --- a/trunk/arch/alpha/kernel/irq.c +++ b/trunk/arch/alpha/kernel/irq.c @@ -117,13 +117,6 @@ handle_irq(int irq) return; } - /* - * From here we must proceed with IPL_MAX. Note that we do not - * explicitly enable interrupts afterwards - some MILO PALcode - * (namely LX164 one) seems to have severe problems with RTI - * at IPL 0. - */ - local_irq_disable(); irq_enter(); generic_handle_irq_desc(irq, desc); irq_exit(); diff --git a/trunk/arch/alpha/kernel/irq_alpha.c b/trunk/arch/alpha/kernel/irq_alpha.c index 772ddfdb71a8..f433fc11877a 100644 --- a/trunk/arch/alpha/kernel/irq_alpha.c +++ b/trunk/arch/alpha/kernel/irq_alpha.c @@ -45,6 +45,14 @@ do_entInt(unsigned long type, unsigned long vector, unsigned long la_ptr, struct pt_regs *regs) { struct pt_regs *old_regs; + + /* + * Disable interrupts during IRQ handling. + * Note that there is no matching local_irq_enable() due to + * severe problems with RTI at IPL0 and some MILO PALcode + * (namely LX164). + */ + local_irq_disable(); switch (type) { case 0: #ifdef CONFIG_SMP @@ -62,7 +70,6 @@ do_entInt(unsigned long type, unsigned long vector, { long cpu; - local_irq_disable(); smp_percpu_timer_interrupt(regs); cpu = smp_processor_id(); if (cpu != boot_cpuid) { @@ -222,7 +229,6 @@ process_mcheck_info(unsigned long vector, unsigned long la_ptr, struct irqaction timer_irqaction = { .handler = timer_interrupt, - .flags = IRQF_DISABLED, .name = "timer", }; diff --git a/trunk/arch/alpha/kernel/sys_nautilus.c b/trunk/arch/alpha/kernel/sys_nautilus.c index 4d4c046f708d..1383f8601a93 100644 --- a/trunk/arch/alpha/kernel/sys_nautilus.c +++ b/trunk/arch/alpha/kernel/sys_nautilus.c @@ -188,6 +188,10 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr) extern void free_reserved_mem(void *, void *); extern void pcibios_claim_one_bus(struct pci_bus *); +static struct resource irongate_io = { + .name = "Irongate PCI IO", + .flags = IORESOURCE_IO, +}; static struct resource irongate_mem = { .name = "Irongate PCI MEM", .flags = IORESOURCE_MEM, @@ -209,6 +213,7 @@ nautilus_init_pci(void) irongate = pci_get_bus_and_slot(0, 0); bus->self = irongate; + bus->resource[0] = &irongate_io; bus->resource[1] = &irongate_mem; pci_bus_size_bridges(bus); diff --git a/trunk/arch/alpha/kernel/sys_titan.c b/trunk/arch/alpha/kernel/sys_titan.c index 5cf4a481b8c5..a53cf03f49d5 100644 --- a/trunk/arch/alpha/kernel/sys_titan.c +++ b/trunk/arch/alpha/kernel/sys_titan.c @@ -280,15 +280,15 @@ titan_late_init(void) * all reported to the kernel as machine checks, so the handler * is a nop so it can be called to count the individual events. */ - titan_request_irq(63+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(63+16, titan_intr_nop, 0, "CChip Error", NULL); - titan_request_irq(62+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(62+16, titan_intr_nop, 0, "PChip 0 H_Error", NULL); - titan_request_irq(61+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(61+16, titan_intr_nop, 0, "PChip 1 H_Error", NULL); - titan_request_irq(60+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(60+16, titan_intr_nop, 0, "PChip 0 C_Error", NULL); - titan_request_irq(59+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(59+16, titan_intr_nop, 0, "PChip 1 C_Error", NULL); /* @@ -348,9 +348,9 @@ privateer_init_pci(void) * Hook a couple of extra err interrupts that the * common titan code won't. */ - titan_request_irq(53+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(53+16, titan_intr_nop, 0, "NMI", NULL); - titan_request_irq(50+16, titan_intr_nop, IRQF_DISABLED, + titan_request_irq(50+16, titan_intr_nop, 0, "Temperature Warning", NULL); /* diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index eb91022b90ba..38b5d5dad8e4 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -673,6 +673,7 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select SOC_BUS select SPARSE_IRQ select USE_OF help @@ -777,6 +778,7 @@ config ARCH_S3C24XX select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS + select MULTI_IRQ_HANDLER select NEED_MACH_GPIO_H select NEED_MACH_IO_H help @@ -938,16 +940,8 @@ config ARCH_NOMADIK help Support for the Nomadik platform by ST-Ericsson -config PLAT_SPEAR +config PLAT_SPEAR_SINGLE bool "ST SPEAr" - select ARCH_HAS_CPUFREQ - select ARCH_REQUIRE_GPIOLIB - select ARM_AMBA - select CLKDEV_LOOKUP - select CLKSRC_MMIO - select COMMON_CLK - select GENERIC_CLOCKEVENTS - select HAVE_CLK help Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). @@ -1109,7 +1103,7 @@ source "arch/arm/plat-samsung/Kconfig" source "arch/arm/mach-socfpga/Kconfig" -source "arch/arm/plat-spear/Kconfig" +source "arch/arm/mach-spear/Kconfig" source "arch/arm/mach-s3c24xx/Kconfig" @@ -1178,6 +1172,7 @@ config PLAT_VERSATILE config ARM_TIMER_SP804 bool select CLKSRC_MMIO + select CLKSRC_OF if OF select HAVE_SCHED_CLOCK source arch/arm/mm/Kconfig @@ -1188,9 +1183,9 @@ config ARM_NR_BANKS default 8 config IWMMXT - bool "Enable iWMMXt support" + bool "Enable iWMMXt support" if !CPU_PJ4 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 - default y if PXA27x || PXA3xx || ARCH_MMP + default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 help Enable support for iWMMXt context switching at run time if running on a CPU that supports it. @@ -1444,6 +1439,16 @@ config ARM_ERRATA_775420 to deadlock. This workaround puts DSB before executing ISB if an abort may occur on cache maintenance. +config ARM_ERRATA_798181 + bool "ARM errata: TLBI/DSB failure on Cortex-A15" + depends on CPU_V7 && SMP + help + On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not + adequately shooting down all use of the old entries. This + option enables the Linux kernel workaround for this erratum + which sends an IPI to the CPUs that are running the same ASID + as the one being invalidated. + endmenu source "arch/arm/common/Kconfig" @@ -1652,7 +1657,7 @@ config LOCAL_TIMERS bool "Use local timer interrupts" depends on SMP default y - select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT) + select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !CLKSRC_EXYNOS_MCT) help Enable support for local timers on SMP platforms, rather then the legacy IPI broadcast method. Local timers allows the system diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index ee4605f400b0..8276536815a8 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -191,9 +191,7 @@ machine-$(CONFIG_ARCH_VT8500) += vt8500 machine-$(CONFIG_ARCH_W90X900) += w90x900 machine-$(CONFIG_FOOTBRIDGE) += footbridge machine-$(CONFIG_ARCH_SOCFPGA) += socfpga -machine-$(CONFIG_ARCH_SPEAR13XX) += spear13xx -machine-$(CONFIG_ARCH_SPEAR3XX) += spear3xx -machine-$(CONFIG_MACH_SPEAR600) += spear6xx +machine-$(CONFIG_PLAT_SPEAR) += spear machine-$(CONFIG_ARCH_VIRT) += virt machine-$(CONFIG_ARCH_ZYNQ) += zynq machine-$(CONFIG_ARCH_SUNXI) += sunxi @@ -207,7 +205,6 @@ plat-$(CONFIG_PLAT_ORION) += orion plat-$(CONFIG_PLAT_PXA) += pxa plat-$(CONFIG_PLAT_S3C24XX) += samsung plat-$(CONFIG_PLAT_S5P) += samsung -plat-$(CONFIG_PLAT_SPEAR) += spear plat-$(CONFIG_PLAT_VERSATILE) += versatile ifeq ($(CONFIG_ARCH_EBSA110),y) diff --git a/trunk/arch/arm/boot/dts/Makefile b/trunk/arch/arm/boot/dts/Makefile index 9c6255884cbb..e35b0a7ac77b 100644 --- a/trunk/arch/arm/boot/dts/Makefile +++ b/trunk/arch/arm/boot/dts/Makefile @@ -31,6 +31,11 @@ dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9x25ek.dtb dtb-$(CONFIG_ARCH_AT91) += at91sam9x35ek.dtb +# sama5d3 +dtb-$(CONFIG_ARCH_AT91) += sama5d31ek.dtb +dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb +dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb +dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb @@ -165,6 +170,8 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra30-cardhu-a04.dtb \ tegra114-dalmore.dtb \ tegra114-pluto.dtb +dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ + versatile-pb.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ vexpress-v2p-ca9.dtb \ vexpress-v2p-ca15-tc1.dtb \ diff --git a/trunk/arch/arm/boot/dts/armada-370-mirabox.dts b/trunk/arch/arm/boot/dts/armada-370-mirabox.dts index dd0c57dd9f30..3234875824dc 100644 --- a/trunk/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/trunk/arch/arm/boot/dts/armada-370-mirabox.dts @@ -54,7 +54,7 @@ }; mvsdio@d00d4000 { - pinctrl-0 = <&sdio_pins2>; + pinctrl-0 = <&sdio_pins3>; pinctrl-names = "default"; status = "okay"; /* diff --git a/trunk/arch/arm/boot/dts/armada-370.dtsi b/trunk/arch/arm/boot/dts/armada-370.dtsi index 8188d138020e..a195debb67d3 100644 --- a/trunk/arch/arm/boot/dts/armada-370.dtsi +++ b/trunk/arch/arm/boot/dts/armada-370.dtsi @@ -59,6 +59,12 @@ "mpp50", "mpp51", "mpp52"; marvell,function = "sd0"; }; + + sdio_pins3: sdio-pins3 { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp51", "mpp52", "mpp53"; + marvell,function = "sd0"; + }; }; gpio0: gpio@d0018100 { diff --git a/trunk/arch/arm/boot/dts/at91sam9g45.dtsi b/trunk/arch/arm/boot/dts/at91sam9g45.dtsi index 6b1d4cab24c2..2b6e30cbc48b 100644 --- a/trunk/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9g45.dtsi @@ -108,6 +108,7 @@ compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; interrupts = <21 4 0>; + #dma-cells = <2>; }; pinctrl@fffff200 { @@ -512,6 +513,8 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <11 4 0>; + dmas = <&dma 1 0>; + dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -521,6 +524,8 @@ compatible = "atmel,hsmci"; reg = <0xfffd0000 0x600>; interrupts = <29 4 0>; + dmas = <&dma 1 13>; + dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/trunk/arch/arm/boot/dts/at91sam9n12.dtsi b/trunk/arch/arm/boot/dts/at91sam9n12.dtsi index 7750f98dd764..b0bd70485f87 100644 --- a/trunk/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9n12.dtsi @@ -89,6 +89,8 @@ compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; interrupts = <12 4 0>; + dmas = <&dma 1 0>; + dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -110,6 +112,7 @@ compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; interrupts = <20 4 0>; + #dma-cells = <2>; }; pinctrl@fffff400 { @@ -360,6 +363,9 @@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; interrupts = <9 4 6>; + dmas = <&dma 1 13>, + <&dma 1 14>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -369,6 +375,9 @@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x100>; interrupts = <10 4 6>; + dmas = <&dma 1 15>, + <&dma 1 16>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi index a98c0d50fbbe..cbb94732786c 100644 --- a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi @@ -104,12 +104,14 @@ compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; interrupts = <20 4 0>; + #dma-cells = <2>; }; dma1: dma-controller@ffffee00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffee00 0x200>; interrupts = <21 4 0>; + #dma-cells = <2>; }; pinctrl@fffff400 { @@ -399,6 +401,8 @@ compatible = "atmel,hsmci"; reg = <0xf0008000 0x600>; interrupts = <12 4 0>; + dmas = <&dma0 1 0>; + dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -408,6 +412,8 @@ compatible = "atmel,hsmci"; reg = <0xf000c000 0x600>; interrupts = <26 4 0>; + dmas = <&dma1 1 0>; + dma-names = "rxtx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -469,6 +475,9 @@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8010000 0x100>; interrupts = <9 4 6>; + dmas = <&dma0 1 7>, + <&dma0 1 8>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -478,6 +487,9 @@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8014000 0x100>; interrupts = <10 4 6>; + dmas = <&dma1 1 5>, + <&dma1 1 6>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -487,6 +499,9 @@ compatible = "atmel,at91sam9x5-i2c"; reg = <0xf8018000 0x100>; interrupts = <11 4 6>; + dmas = <&dma0 1 9>, + <&dma0 1 10>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/trunk/arch/arm/boot/dts/dbx5x0.dtsi b/trunk/arch/arm/boot/dts/dbx5x0.dtsi index 9de93096601a..aaa63d0a8096 100644 --- a/trunk/arch/arm/boot/dts/dbx5x0.dtsi +++ b/trunk/arch/arm/boot/dts/dbx5x0.dtsi @@ -191,8 +191,8 @@ prcmu: prcmu@80157000 { compatible = "stericsson,db8500-prcmu"; - reg = <0x80157000 0x1000>; - reg-names = "prcmu"; + reg = <0x80157000 0x1000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; + reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; interrupts = <0 47 0x4>; #address-cells = <1>; #size-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/exynos4210.dtsi b/trunk/arch/arm/boot/dts/exynos4210.dtsi index 2feffc70814c..49a2786e00b9 100644 --- a/trunk/arch/arm/boot/dts/exynos4210.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4210.dtsi @@ -47,6 +47,28 @@ <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>; }; + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &gic 0 57 0>, + <0x1 0 &gic 0 69 0>, + <0x2 0 &combiner 12 6>, + <0x3 0 &combiner 12 7>, + <0x4 0 &gic 0 42 0>, + <0x5 0 &gic 0 48 0>; + }; + }; + pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; diff --git a/trunk/arch/arm/boot/dts/exynos4212.dtsi b/trunk/arch/arm/boot/dts/exynos4212.dtsi index c6ae2005961f..36d4299789ef 100644 --- a/trunk/arch/arm/boot/dts/exynos4212.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4212.dtsi @@ -25,4 +25,26 @@ gic:interrupt-controller@10490000 { cpu-offset = <0x8000>; }; + + mct@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &gic 0 57 0>, + <0x1 0 &combiner 12 5>, + <0x2 0 &combiner 12 6>, + <0x3 0 &combiner 12 7>, + <0x4 0 &gic 1 12 0>, + <0x5 0 &gic 1 12 0>; + }; + }; }; diff --git a/trunk/arch/arm/boot/dts/exynos4412.dtsi b/trunk/arch/arm/boot/dts/exynos4412.dtsi index d7dfe312772a..821c9fdd1e3b 100644 --- a/trunk/arch/arm/boot/dts/exynos4412.dtsi +++ b/trunk/arch/arm/boot/dts/exynos4412.dtsi @@ -25,4 +25,28 @@ gic:interrupt-controller@10490000 { cpu-offset = <0x4000>; }; + + mct@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>, <6 0>, <7 0>; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &gic 0 57 0>, + <0x1 0 &combiner 12 5>, + <0x2 0 &combiner 12 6>, + <0x3 0 &combiner 12 7>, + <0x4 0 &gic 1 12 0>, + <0x5 0 &gic 1 12 0>, + <0x6 0 &gic 1 12 0>, + <0x7 0 &gic 1 12 0>; + }; + }; }; diff --git a/trunk/arch/arm/boot/dts/exynos5250.dtsi b/trunk/arch/arm/boot/dts/exynos5250.dtsi index b1ac73e21c80..c60108e0d27e 100644 --- a/trunk/arch/arm/boot/dts/exynos5250.dtsi +++ b/trunk/arch/arm/boot/dts/exynos5250.dtsi @@ -69,6 +69,28 @@ <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; }; + mct@101C0000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x101C0000 0x800>; + interrupt-controller; + #interrups-cells = <2>; + interrupt-parent = <&mct_map>; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>; + + mct_map: mct-map { + #interrupt-cells = <2>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = <0x0 0 &combiner 23 3>, + <0x1 0 &combiner 23 4>, + <0x2 0 &combiner 25 2>, + <0x3 0 &combiner 25 3>, + <0x4 0 &gic 0 120 0>, + <0x5 0 &gic 0 121 0>; + }; + }; + watchdog { compatible = "samsung,s3c2410-wdt"; reg = <0x101D0000 0x100>; diff --git a/trunk/arch/arm/boot/dts/integratorcp.dts b/trunk/arch/arm/boot/dts/integratorcp.dts index 8b119399025a..ff1aea0ee043 100644 --- a/trunk/arch/arm/boot/dts/integratorcp.dts +++ b/trunk/arch/arm/boot/dts/integratorcp.dts @@ -24,15 +24,15 @@ }; timer0: timer@13000000 { - compatible = "arm,sp804", "arm,primecell"; + compatible = "arm,integrator-cp-timer"; }; timer1: timer@13000100 { - compatible = "arm,sp804", "arm,primecell"; + compatible = "arm,integrator-cp-timer"; }; timer2: timer@13000200 { - compatible = "arm,sp804", "arm,primecell"; + compatible = "arm,integrator-cp-timer"; }; pic: pic@14000000 { diff --git a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts index bd83b8fc7c83..c3573be7b92c 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-goflexnet.dts @@ -77,6 +77,7 @@ }; nand@3000000 { + chip-delay = <40>; status = "okay"; partition@0 { diff --git a/trunk/arch/arm/boot/dts/orion5x.dtsi b/trunk/arch/arm/boot/dts/orion5x.dtsi index 8aad00f81ed9..f7bec3b1ba32 100644 --- a/trunk/arch/arm/boot/dts/orion5x.dtsi +++ b/trunk/arch/arm/boot/dts/orion5x.dtsi @@ -13,6 +13,9 @@ compatible = "marvell,orion5x"; interrupt-parent = <&intc>; + aliases { + gpio0 = &gpio0; + }; intc: interrupt-controller { compatible = "marvell,orion-intc", "marvell,intc"; interrupt-controller; @@ -32,7 +35,9 @@ #gpio-cells = <2>; gpio-controller; reg = <0x10100 0x40>; - ngpio = <32>; + ngpios = <32>; + interrupt-controller; + #interrupt-cells = <2>; interrupts = <6>, <7>, <8>, <9>; }; @@ -91,7 +96,7 @@ reg = <0x90000 0x10000>, <0xf2200000 0x800>; reg-names = "regs", "sram"; - interrupts = <22>; + interrupts = <28>; status = "okay"; }; }; diff --git a/trunk/arch/arm/boot/dts/sama5d3.dtsi b/trunk/arch/arm/boot/dts/sama5d3.dtsi new file mode 100644 index 000000000000..2e643ea51cce --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d3.dtsi @@ -0,0 +1,1046 @@ +/* + * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC + * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel SAMA5D3 family SoC"; + compatible = "atmel,sama5d3", "atmel,sama5"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + gpio4 = &pioE; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + ssc0 = &ssc0; + ssc1 = &ssc1; + }; + cpus { + cpu@0 { + compatible = "arm,cortex-a5"; + }; + }; + + memory { + reg = <0x20000000 0x8000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mmc0: mmc@f0000000 { + compatible = "atmel,hsmci"; + reg = <0xf0000000 0x600>; + interrupts = <21 4 0>; + dmas = <&dma0 2 0>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@f0004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9x5-spi"; + reg = <0xf0004000 0x100>; + interrupts = <24 4 3>; + cs-gpios = <&pioD 13 0 + &pioD 14 0 /* conflicts with SCK0 and CANRX0 */ + &pioD 15 0 /* conflicts with CTS0 and CANTX0 */ + &pioD 16 0 /* conflicts with RTS0 and PWMFI3 */ + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + status = "disabled"; + }; + + ssc0: ssc@f0008000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf0008000 0x4000>; + interrupts = <38 4 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + status = "disabled"; + }; + + can0: can@f000c000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf000c000 0x300>; + interrupts = <40 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + status = "disabled"; + }; + + tcb0: timer@f0010000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf0010000 0x100>; + interrupts = <26 4 0>; + }; + + i2c0: i2c@f0014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0014000 0x4000>; + interrupts = <18 4 6>; + dmas = <&dma0 2 7>, + <&dma0 2 8>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@f0018000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf0018000 0x4000>; + interrupts = <19 4 6>; + dmas = <&dma0 2 9>, + <&dma0 2 10>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usart0: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + interrupts = <12 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart0>; + status = "disabled"; + }; + + usart1: serial@f0020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf0020000 0x100>; + interrupts = <13 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; + status = "disabled"; + }; + + macb0: ethernet@f0028000 { + compatible = "cnds,pc302-gem", "cdns,gem"; + reg = <0xf0028000 0x100>; + interrupts = <34 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + status = "disabled"; + }; + + isi: isi@f0034000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xf0034000 0x4000>; + interrupts = <37 4 5>; + status = "disabled"; + }; + + mmc1: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <22 4 0>; + dmas = <&dma1 2 0>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@f8004000 { + compatible = "atmel,hsmci"; + reg = <0xf8004000 0x600>; + interrupts = <23 4 0>; + dmas = <&dma1 2 1>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@f8008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9x5-spi"; + reg = <0xf8008000 0x100>; + interrupts = <25 4 3>; + cs-gpios = <&pioC 25 0 + &pioC 26 0 /* conflitcs with TWD1 and ISI_D11 */ + &pioC 27 0 /* conflitcs with TWCK1 and ISI_D10 */ + &pioC 28 0 /* conflitcs with PWMFI0 and ISI_D9 */ + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + status = "disabled"; + }; + + ssc1: ssc@f800c000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0xf800c000 0x4000>; + interrupts = <39 4 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + status = "disabled"; + }; + + can1: can@f8010000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8010000 0x300>; + interrupts = <41 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + }; + + tcb1: timer@f8014000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8014000 0x100>; + interrupts = <27 4 0>; + }; + + adc0: adc@f8018000 { + compatible = "atmel,at91sam9260-adc"; + reg = <0xf8018000 0x100>; + interrupts = <29 4 5>; + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + &pinctrl_adc0_ad5 + &pinctrl_adc0_ad6 + &pinctrl_adc0_ad7 + &pinctrl_adc0_ad8 + &pinctrl_adc0_ad9 + &pinctrl_adc0_ad10 + &pinctrl_adc0_ad11 + >; + atmel,adc-channel-base = <0x50>; + atmel,adc-channels-used = <0xfff>; + atmel,adc-drdy-mask = <0x1000000>; + atmel,adc-num-channels = <12>; + atmel,adc-startup-time = <40>; + atmel,adc-status-register = <0x30>; + atmel,adc-trigger-register = <0xc0>; + atmel,adc-use-external; + atmel,adc-vref = <3000>; + atmel,adc-res = <10 12>; + atmel,adc-res-names = "lowres", "highres"; + status = "disabled"; + + trigger@0 { + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + }; + trigger@1 { + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + }; + trigger@2 { + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + }; + trigger@3 { + trigger-name = "continuous"; + trigger-value = <0x6>; + }; + }; + + tsadcc: tsadcc@f8018000 { + compatible = "atmel,at91sam9x5-tsadcc"; + reg = <0xf8018000 0x4000>; + interrupts = <29 4 5>; + atmel,tsadcc_clock = <300000>; + atmel,filtering_average = <0x03>; + atmel,pendet_debounce = <0x08>; + atmel,pendet_sensitivity = <0x02>; + atmel,ts_sample_hold_time = <0x0a>; + status = "disabled"; + }; + + i2c2: i2c@f801c000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf801c000 0x4000>; + interrupts = <20 4 6>; + dmas = <&dma1 2 11>, + <&dma1 2 12>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usart2: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x100>; + interrupts = <14 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2>; + status = "disabled"; + }; + + usart3: serial@f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x100>; + interrupts = <15 4 5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + status = "disabled"; + }; + + macb1: ethernet@f802c000 { + compatible = "cdns,at32ap7000-macb", "cdns,macb"; + reg = <0xf802c000 0x100>; + interrupts = <35 4 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb1_rmii>; + status = "disabled"; + }; + + sha@f8034000 { + compatible = "atmel,sam9g46-sha"; + reg = <0xf8034000 0x100>; + interrupts = <42 4 0>; + }; + + aes@f8038000 { + compatible = "atmel,sam9g46-aes"; + reg = <0xf8038000 0x100>; + interrupts = <43 4 0>; + }; + + tdes@f803c000 { + compatible = "atmel,sam9g46-tdes"; + reg = <0xf803c000 0x100>; + interrupts = <44 4 0>; + }; + + dma0: dma-controller@ffffe600 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe600 0x200>; + interrupts = <30 4 0>; + #dma-cells = <2>; + }; + + dma1: dma-controller@ffffe800 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffe800 0x200>; + interrupts = <31 4 0>; + #dma-cells = <2>; + }; + + ramc0: ramc@ffffea00 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffea00 0x200>; + }; + + dbgu: serial@ffffee00 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xffffee00 0x200>; + interrupts = <2 4 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + status = "disabled"; + }; + + aic: interrupt-controller@fffff000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d3-aic"; + interrupt-controller; + reg = <0xfffff000 0x200>; + atmel,external-irqs = <47>; + }; + + pinctrl@fffff200 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfffff200 0xfffff200 0xa00>; + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ + 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ + 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ + 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ + 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ + >; + + /* shared pinctrl settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + <3 19 0x1 0x0>; /* PD19 periph A ADTRG */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + <3 20 0x1 0x0>; /* PD20 periph A AD0 */ + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + <3 21 0x1 0x0>; /* PD21 periph A AD1 */ + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + <3 22 0x1 0x0>; /* PD22 periph A AD2 */ + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + <3 23 0x1 0x0>; /* PD23 periph A AD3 */ + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + <3 24 0x1 0x0>; /* PD24 periph A AD4 */ + }; + pinctrl_adc0_ad5: adc0_ad5 { + atmel,pins = + <3 25 0x1 0x0>; /* PD25 periph A AD5 */ + }; + pinctrl_adc0_ad6: adc0_ad6 { + atmel,pins = + <3 26 0x1 0x0>; /* PD26 periph A AD6 */ + }; + pinctrl_adc0_ad7: adc0_ad7 { + atmel,pins = + <3 27 0x1 0x0>; /* PD27 periph A AD7 */ + }; + pinctrl_adc0_ad8: adc0_ad8 { + atmel,pins = + <3 28 0x1 0x0>; /* PD28 periph A AD8 */ + }; + pinctrl_adc0_ad9: adc0_ad9 { + atmel,pins = + <3 29 0x1 0x0>; /* PD29 periph A AD9 */ + }; + pinctrl_adc0_ad10: adc0_ad10 { + atmel,pins = + <3 30 0x1 0x0>; /* PD30 periph A AD10, conflicts with PCK0 */ + }; + pinctrl_adc0_ad11: adc0_ad11 { + atmel,pins = + <3 31 0x1 0x0>; /* PD31 periph A AD11, conflicts with PCK1 */ + }; + }; + + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + <3 14 0x3 0x0 /* PD14 periph C RX, conflicts with SCK0, SPI0_NPCS1 */ + 3 15 0x3 0x0>; /* PD15 periph C TX, conflicts with CTS0, SPI0_NPCS2 */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + <1 14 0x2 0x0 /* PB14 periph B RX, conflicts with GCRS */ + 1 15 0x2 0x0>; /* PB15 periph B TX, conflicts with GCOL */ + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <1 30 0x1 0x0 /* PB30 periph A */ + 1 31 0x1 0x1>; /* PB31 periph A with pullup */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <0 30 0x1 0x0 /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ + 0 31 0x1 0x0>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ + }; + }; + + i2c1 { + pinctrl_i2c1: i2c1-0 { + atmel,pins = + <2 26 0x2 0x0 /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ + 2 27 0x2 0x0>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ + }; + }; + + isi { + pinctrl_isi: isi-0 { + atmel,pins = + <0 16 0x3 0x0 /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ + 0 17 0x3 0x0 /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ + 0 18 0x3 0x0 /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ + 0 19 0x3 0x0 /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ + 0 20 0x3 0x0 /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ + 0 21 0x3 0x0 /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ + 0 22 0x3 0x0 /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ + 0 23 0x3 0x0 /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ + 2 30 0x3 0x0 /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ + 0 31 0x3 0x0 /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ + 0 30 0x3 0x0 /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ + 2 29 0x3 0x0 /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ + 2 28 0x3 0x0>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ + }; + pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { + atmel,pins = + <3 31 0x2 0x0>; /* PD31 periph B ISI_MCK */ + }; + }; + + lcd { + pinctrl_lcd: lcd-0 { + atmel,pins = + <0 24 0x1 0x0 /* PA24 periph A LCDPWM */ + 0 26 0x1 0x0 /* PA26 periph A LCDVSYNC */ + 0 27 0x1 0x0 /* PA27 periph A LCDHSYNC */ + 0 25 0x1 0x0 /* PA25 periph A LCDDISP */ + 0 29 0x1 0x0 /* PA29 periph A LCDDEN */ + 0 28 0x1 0x0 /* PA28 periph A LCDPCK */ + 0 0 0x1 0x0 /* PA0 periph A LCDD0 pin */ + 0 1 0x1 0x0 /* PA1 periph A LCDD1 pin */ + 0 2 0x1 0x0 /* PA2 periph A LCDD2 pin */ + 0 3 0x1 0x0 /* PA3 periph A LCDD3 pin */ + 0 4 0x1 0x0 /* PA4 periph A LCDD4 pin */ + 0 5 0x1 0x0 /* PA5 periph A LCDD5 pin */ + 0 6 0x1 0x0 /* PA6 periph A LCDD6 pin */ + 0 7 0x1 0x0 /* PA7 periph A LCDD7 pin */ + 0 8 0x1 0x0 /* PA8 periph A LCDD8 pin */ + 0 9 0x1 0x0 /* PA9 periph A LCDD9 pin */ + 0 10 0x1 0x0 /* PA10 periph A LCDD10 pin */ + 0 11 0x1 0x0 /* PA11 periph A LCDD11 pin */ + 0 12 0x1 0x0 /* PA12 periph A LCDD12 pin */ + 0 13 0x1 0x0 /* PA13 periph A LCDD13 pin */ + 0 14 0x1 0x0 /* PA14 periph A LCDD14 pin */ + 0 15 0x1 0x0 /* PA15 periph A LCDD15 pin */ + 2 14 0x3 0x0 /* PC14 periph C LCDD16 pin */ + 2 13 0x3 0x0 /* PC13 periph C LCDD17 pin */ + 2 12 0x3 0x0 /* PC12 periph C LCDD18 pin */ + 2 11 0x3 0x0 /* PC11 periph C LCDD19 pin */ + 2 10 0x3 0x0 /* PC10 periph C LCDD20 pin */ + 2 15 0x3 0x0 /* PC15 periph C LCDD21 pin */ + 4 27 0x3 0x0 /* PE27 periph C LCDD22 pin */ + 4 28 0x3 0x0>; /* PE28 periph C LCDD23 pin */ + }; + }; + + macb0 { + pinctrl_macb0_data_rgmii: macb0_data_rgmii { + atmel,pins = + <1 0 0x1 0x0 /* PB0 periph A GTX0, conflicts with PWMH0 */ + 1 1 0x1 0x0 /* PB1 periph A GTX1, conflicts with PWML0 */ + 1 2 0x1 0x0 /* PB2 periph A GTX2, conflicts with TK1 */ + 1 3 0x1 0x0 /* PB3 periph A GTX3, conflicts with TF1 */ + 1 4 0x1 0x0 /* PB4 periph A GRX0, conflicts with PWMH1 */ + 1 5 0x1 0x0 /* PB5 periph A GRX1, conflicts with PWML1 */ + 1 6 0x1 0x0 /* PB6 periph A GRX2, conflicts with TD1 */ + 1 7 0x1 0x0>; /* PB7 periph A GRX3, conflicts with RK1 */ + }; + pinctrl_macb0_data_gmii: macb0_data_gmii { + atmel,pins = + <1 19 0x2 0x0 /* PB19 periph B GTX4, conflicts with MCI1_CDA */ + 1 20 0x2 0x0 /* PB20 periph B GTX5, conflicts with MCI1_DA0 */ + 1 21 0x2 0x0 /* PB21 periph B GTX6, conflicts with MCI1_DA1 */ + 1 22 0x2 0x0 /* PB22 periph B GTX7, conflicts with MCI1_DA2 */ + 1 23 0x2 0x0 /* PB23 periph B GRX4, conflicts with MCI1_DA3 */ + 1 24 0x2 0x0 /* PB24 periph B GRX5, conflicts with MCI1_CK */ + 1 25 0x2 0x0 /* PB25 periph B GRX6, conflicts with SCK1 */ + 1 26 0x2 0x0>; /* PB26 periph B GRX7, conflicts with CTS1 */ + }; + pinctrl_macb0_signal_rgmii: macb0_signal_rgmii { + atmel,pins = + <1 8 0x1 0x0 /* PB8 periph A GTXCK, conflicts with PWMH2 */ + 1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ + 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ + 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ + 1 16 0x1 0x0 /* PB16 periph A GMDC */ + 1 17 0x1 0x0 /* PB17 periph A GMDIO */ + 1 18 0x1 0x0>; /* PB18 periph A G125CK */ + }; + pinctrl_macb0_signal_gmii: macb0_signal_gmii { + atmel,pins = + <1 9 0x1 0x0 /* PB9 periph A GTXEN, conflicts with PWML2 */ + 1 10 0x1 0x0 /* PB10 periph A GTXER, conflicts with RF1 */ + 1 11 0x1 0x0 /* PB11 periph A GRXCK, conflicts with RD1 */ + 1 12 0x1 0x0 /* PB12 periph A GRXDV, conflicts with PWMH3 */ + 1 13 0x1 0x0 /* PB13 periph A GRXER, conflicts with PWML3 */ + 1 14 0x1 0x0 /* PB14 periph A GCRS, conflicts with CANRX1 */ + 1 15 0x1 0x0 /* PB15 periph A GCOL, conflicts with CANTX1 */ + 1 16 0x1 0x0 /* PB16 periph A GMDC */ + 1 17 0x1 0x0 /* PB17 periph A GMDIO */ + 1 27 0x2 0x0>; /* PB27 periph B G125CKO */ + }; + + }; + + macb1 { + pinctrl_macb1_rmii: macb1_rmii-0 { + atmel,pins = + <2 0 0x1 0x0 /* PC0 periph A ETX0, conflicts with TIOA3 */ + 2 1 0x1 0x0 /* PC1 periph A ETX1, conflicts with TIOB3 */ + 2 2 0x1 0x0 /* PC2 periph A ERX0, conflicts with TCLK3 */ + 2 3 0x1 0x0 /* PC3 periph A ERX1, conflicts with TIOA4 */ + 2 4 0x1 0x0 /* PC4 periph A ETXEN, conflicts with TIOB4 */ + 2 5 0x1 0x0 /* PC5 periph A ECRSDV,conflicts with TCLK4 */ + 2 6 0x1 0x0 /* PC6 periph A ERXER, conflicts with TIOA5 */ + 2 7 0x1 0x0 /* PC7 periph A EREFCK, conflicts with TIOB5 */ + 2 8 0x1 0x0 /* PC8 periph A EMDC, conflicts with TCLK5 */ + 2 9 0x1 0x0>; /* PC9 periph A EMDIO */ + }; + }; + + mmc0 { + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + atmel,pins = + <3 9 0x1 0x0 /* PD9 periph A MCI0_CK */ + 3 0 0x1 0x1 /* PD0 periph A MCI0_CDA with pullup */ + 3 1 0x1 0x1>; /* PD1 periph A MCI0_DA0 with pullup */ + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + atmel,pins = + <3 2 0x1 0x1 /* PD2 periph A MCI0_DA1 with pullup */ + 3 3 0x1 0x1 /* PD3 periph A MCI0_DA2 with pullup */ + 3 4 0x1 0x1>; /* PD4 periph A MCI0_DA3 with pullup */ + }; + pinctrl_mmc0_dat4_7: mmc0_dat4_7 { + atmel,pins = + <3 5 0x1 0x1 /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ + 3 6 0x1 0x1 /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ + 3 7 0x1 0x1 /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ + 3 8 0x1 0x1>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ + }; + }; + + mmc1 { + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + atmel,pins = + <1 24 0x1 0x0 /* PB24 periph A MCI1_CK, conflicts with GRX5 */ + 1 19 0x1 0x1 /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ + 1 20 0x1 0x1>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + atmel,pins = + <1 21 0x1 0x1 /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ + 1 22 0x1 0x1 /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ + 1 23 0x1 0x1>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ + }; + }; + + mmc2 { + pinctrl_mmc2_clk_cmd_dat0: mmc2_clk_cmd_dat0 { + atmel,pins = + <2 15 0x1 0x0 /* PC15 periph A MCI2_CK, conflicts with PCK2 */ + 2 10 0x1 0x1 /* PC10 periph A MCI2_CDA with pullup */ + 2 11 0x1 0x1>; /* PC11 periph A MCI2_DA0 with pullup */ + }; + pinctrl_mmc2_dat1_3: mmc2_dat1_3 { + atmel,pins = + <2 12 0x1 0x0 /* PC12 periph A MCI2_DA1 with pullup, conflicts with TIOA1 */ + 2 13 0x1 0x0 /* PC13 periph A MCI2_DA2 with pullup, conflicts with TIOB1 */ + 2 14 0x1 0x0>; /* PC14 periph A MCI2_DA3 with pullup, conflicts with TCLK1 */ + }; + }; + + nand0 { + pinctrl_nand0_ale_cle: nand0_ale_cle-0 { + atmel,pins = + <4 21 0x1 0x1 /* PE21 periph A with pullup */ + 4 22 0x1 0x1>; /* PE22 periph A with pullup */ + }; + }; + + pioA: gpio@fffff200 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff200 0x100>; + interrupts = <6 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioB: gpio@fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <7 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioC: gpio@fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <8 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioD: gpio@fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <9 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pioE: gpio@fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <10 4 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <3 10 0x1 0x0 /* PD10 periph A SPI0_MISO pin */ + 3 11 0x1 0x0 /* PD11 periph A SPI0_MOSI pin */ + 3 12 0x1 0x0 /* PD12 periph A SPI0_SPCK pin */ + 3 13 0x0 0x0>; /* PD13 GPIO SPI0_NPCS0 pin */ + }; + }; + + spi1 { + pinctrl_spi1: spi1-0 { + atmel,pins = + <2 22 0x1 0x0 /* PC22 periph A SPI1_MISO pin */ + 2 23 0x1 0x0 /* PC23 periph A SPI1_MOSI pin */ + 2 24 0x1 0x0 /* PC24 periph A SPI1_SPCK pin */ + 2 25 0x0 0x0>; /* PC25 GPIO SPI1_NPCS0 pin */ + }; + }; + + ssc0 { + pinctrl_ssc0_tx: ssc0_tx { + atmel,pins = + <2 16 0x1 0x0 /* PC16 periph A TK0 */ + 2 17 0x1 0x0 /* PC17 periph A TF0 */ + 2 18 0x1 0x0>; /* PC18 periph A TD0 */ + }; + + pinctrl_ssc0_rx: ssc0_rx { + atmel,pins = + <2 19 0x1 0x0 /* PC19 periph A RK0 */ + 2 20 0x1 0x0 /* PC20 periph A RF0 */ + 2 21 0x1 0x0>; /* PC21 periph A RD0 */ + }; + }; + + ssc1 { + pinctrl_ssc1_tx: ssc1_tx { + atmel,pins = + <1 2 0x2 0x0 /* PB2 periph B TK1, conflicts with GTX2 */ + 1 3 0x2 0x0 /* PB3 periph B TF1, conflicts with GTX3 */ + 1 6 0x2 0x0>; /* PB6 periph B TD1, conflicts with TD1 */ + }; + + pinctrl_ssc1_rx: ssc1_rx { + atmel,pins = + <1 7 0x2 0x0 /* PB7 periph B RK1, conflicts with EREFCK */ + 1 10 0x2 0x0 /* PB10 periph B RF1, conflicts with GTXER */ + 1 11 0x2 0x0>; /* PB11 periph B RD1, conflicts with GRXCK */ + }; + }; + + uart0 { + pinctrl_uart0: uart0-0 { + atmel,pins = + <2 29 0x1 0x0 /* PC29 periph A, conflicts with PWMFI2, ISI_D8 */ + 2 30 0x1 0x1>; /* PC30 periph A with pullup, conflicts with ISI_PCK */ + }; + }; + + uart1 { + pinctrl_uart1: uart1-0 { + atmel,pins = + <0 30 0x2 0x0 /* PA30 periph B, conflicts with TWD0, ISI_VSYNC */ + 0 31 0x2 0x1>; /* PA31 periph B with pullup, conflicts with TWCK0, ISI_HSYNC */ + }; + }; + + usart0 { + pinctrl_usart0: usart0-0 { + atmel,pins = + <3 17 0x1 0x0 /* PD17 periph A */ + 3 18 0x1 0x1>; /* PD18 periph A with pullup */ + }; + + pinctrl_usart0_rts_cts: usart0_rts_cts-0 { + atmel,pins = + <3 15 0x1 0x0 /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ + 3 16 0x1 0x0>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ + }; + }; + + usart1 { + pinctrl_usart1: usart1-0 { + atmel,pins = + <1 28 0x1 0x0 /* PB28 periph A */ + 1 29 0x1 0x1>; /* PB29 periph A with pullup */ + }; + + pinctrl_usart1_rts_cts: usart1_rts_cts-0 { + atmel,pins = + <1 26 0x1 0x0 /* PB26 periph A, conflicts with GRX7 */ + 1 27 0x1 0x0>; /* PB27 periph A, conflicts with G125CKO */ + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <4 25 0x2 0x0 /* PE25 periph B, conflicts with A25 */ + 4 26 0x2 0x1>; /* PE26 periph B with pullup, conflicts NCS0 */ + }; + + pinctrl_usart2_rts_cts: usart2_rts_cts-0 { + atmel,pins = + <4 23 0x2 0x0 /* PE23 periph B, conflicts with A23 */ + 4 24 0x2 0x0>; /* PE24 periph B, conflicts with A24 */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + <4 18 0x2 0x0 /* PE18 periph B, conflicts with A18 */ + 4 19 0x2 0x1>; /* PE19 periph B with pullup, conflicts with A19 */ + }; + + pinctrl_usart3_rts_cts: usart3_rts_cts-0 { + atmel,pins = + <4 16 0x2 0x0 /* PE16 periph B, conflicts with A16 */ + 4 17 0x2 0x0>; /* PE17 periph B, conflicts with A17 */ + }; + }; + }; + + pmc: pmc@fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x120>; + }; + + rstc@fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + }; + + pit: timer@fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <3 4 5>; + }; + + watchdog@fffffe40 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfffffe40 0x10>; + status = "disabled"; + }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x30>; + interrupts = <1 4 7>; + }; + }; + + usb0: gadget@00500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00500000 0x100000 + 0xf8030000 0x4000>; + interrupts = <33 4 2>; + status = "disabled"; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep7 { + reg = <7>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + }; + + ep8 { + reg = <8>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep9 { + reg = <9>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep10 { + reg = <10>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep11 { + reg = <11>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep12 { + reg = <12>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep13 { + reg = <13>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep14 { + reg = <14>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + + ep15 { + reg = <15>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + }; + }; + + usb1: ohci@00600000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00600000 0x100000>; + interrupts = <32 4 2>; + status = "disabled"; + }; + + usb2: ehci@00700000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00700000 0x100000>; + interrupts = <32 4 2>; + status = "disabled"; + }; + + nand0: nand@60000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = < 0x60000000 0x01000000 /* EBI CS3 */ + 0xffffc070 0x00000490 /* SMC PMECC regs */ + 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ + 0x00100000 0x00100000 /* ROM code */ + 0x70000000 0x10000000 /* NFC Command Registers */ + 0xffffc000 0x00000070 /* NFC HSMC regs */ + 0x00200000 0x00100000 /* NFC SRAM banks */ + >; + interrupts = <5 4 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand0_ale_cle>; + atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; + status = "disabled"; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/sama5d31ek.dts b/trunk/arch/arm/boot/dts/sama5d31ek.dts new file mode 100644 index 000000000000..fa5d216f1db7 --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d31ek.dts @@ -0,0 +1,51 @@ +/* + * sama5d31ek.dts - Device Tree file for SAMA5D31-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "sama5d3xmb.dtsi" +/include/ "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D31-EK"; + compatible = "atmel,sama5d31ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + leds { + d3 { + label = "d3"; + gpios = <&pioE 24 0>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/trunk/arch/arm/boot/dts/sama5d33ek.dts b/trunk/arch/arm/boot/dts/sama5d33ek.dts new file mode 100644 index 000000000000..c38c9433d7a5 --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d33ek.dts @@ -0,0 +1,44 @@ +/* + * sama5d33ek.dts - Device Tree file for SAMA5D33-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "sama5d3xmb.dtsi" +/include/ "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D33-EK"; + compatible = "atmel,sama5d33ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/trunk/arch/arm/boot/dts/sama5d34ek.dts b/trunk/arch/arm/boot/dts/sama5d34ek.dts new file mode 100644 index 000000000000..6bebfcdcb1d1 --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d34ek.dts @@ -0,0 +1,61 @@ +/* + * sama5d34ek.dts - Device Tree file for SAMA5D34-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "sama5d3xmb.dtsi" +/include/ "sama5d3xdm.dtsi" + +/ { + model = "Atmel SAMA5D34-EK"; + compatible = "atmel,sama5d34ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + ssc0: ssc@f0008000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c0: i2c@f0014000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + + 24c256@50 { + compatible = "24c256"; + reg = <0x50>; + pagesize = <64>; + }; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + }; + }; + + leds { + d3 { + label = "d3"; + gpios = <&pioE 24 0>; + }; + }; + + sound { + status = "okay"; + }; +}; diff --git a/trunk/arch/arm/boot/dts/sama5d35ek.dts b/trunk/arch/arm/boot/dts/sama5d35ek.dts new file mode 100644 index 000000000000..a488fc4e9777 --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d35ek.dts @@ -0,0 +1,56 @@ +/* + * sama5d35ek.dts - Device Tree file for SAMA5D35-EK board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/dts-v1/; +/include/ "sama5d3xmb.dtsi" + +/ { + model = "Atmel SAMA5D35-EK"; + compatible = "atmel,sama5d35ek", "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + spi0: spi@f0004000 { + status = "okay"; + }; + + can0: can@f000c000 { + status = "okay"; + }; + + i2c1: i2c@f0018000 { + status = "okay"; + }; + + macb0: ethernet@f0028000 { + status = "okay"; + }; + + isi: isi@f0034000 { + status = "okay"; + }; + + macb1: ethernet@f802c000 { + status = "okay"; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 27 0>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/sama5d3xcm.dtsi b/trunk/arch/arm/boot/dts/sama5d3xcm.dtsi new file mode 100644 index 000000000000..1f8ed404626c --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -0,0 +1,91 @@ +/* + * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/include/ "sama5d3.dtsi" + +/ { + compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; + + chosen { + bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + macb0: ethernet@f0028000 { + phy-mode = "rgmii"; + }; + }; + + nand0: nand@60000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + atmel,has-pmecc; + atmel,pmecc-cap = <4>; + atmel,pmecc-sector-size = <512>; + atmel,has-nfc; + atmel,use-nfc-sram; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + d2 { + label = "d2"; + gpios = <&pioE 25 1>; /* PE25, conflicts with A25, RXD2 */ + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/sama5d3xdm.dtsi b/trunk/arch/arm/boot/dts/sama5d3xdm.dtsi new file mode 100644 index 000000000000..4b8830eb2060 --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d3xdm.dtsi @@ -0,0 +1,42 @@ +/* + * sama5d3dm.dtsi - Device Tree file for SAMA5 display module + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ + +/ { + ahb { + apb { + i2c1: i2c@f0018000 { + qt1070: keyboard@1b { + compatible = "qt1070"; + reg = <0x1b>; + interrupt-parent = <&pioE>; + interrupts = <31 0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qt1070_irq>; + }; + }; + + adc0: adc@f8018000 { + status = "disabled"; + }; + + tsadcc: tsadcc@f8018000 { + status = "okay"; + }; + + pinctrl@fffff200 { + board { + pinctrl_qt1070_irq: qt1070_irq { + atmel,pins = + <4 31 0x0 0x5>; /* PE31 GPIO with pull up deglith */ + }; + }; + }; + }; + }; +}; diff --git a/trunk/arch/arm/boot/dts/sama5d3xmb.dtsi b/trunk/arch/arm/boot/dts/sama5d3xmb.dtsi new file mode 100644 index 000000000000..661d7ca9c309 --- /dev/null +++ b/trunk/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -0,0 +1,166 @@ +/* + * sama5d3xmb.dts - Device Tree file for SAMA5D3x mother board + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ +/include/ "sama5d3xcm.dtsi" + +/ { + compatible = "atmel,sama5d3xmb", "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; + + ahb { + apb { + mmc0: mmc@f0000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 17 0>; + }; + }; + + spi0: spi@f0004000 { + m25p80@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + /* + * i2c0 conflicts with ISI: + * disable it to allow the use of ISI + * can not enable audio when i2c0 disabled + */ + i2c0: i2c@f0014000 { + wm8904: wm8904@1a { + compatible = "wm8904"; + reg = <0x1a>; + }; + }; + + usart1: serial@f0020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; + status = "okay"; + }; + + isi: isi@f0034000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi &pinctrl_isi_pck_as_mck &pinctrl_isi_power &pinctrl_isi_reset>; + }; + + mmc1: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 18 0>; + }; + }; + + adc0: adc@f8018000 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_adc0_adtrg + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + status = "okay"; + }; + + macb1: ethernet@f802c000 { + phy-mode = "rmii"; + }; + + pinctrl@fffff200 { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + <3 17 0x0 0x5>; /* PD17 GPIO with pullup deglitch */ + }; + + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + <3 18 0x0 0x5>; /* PD18 GPIO with pullup deglitch */ + }; + + pinctrl_pck0_as_audio_mck: pck0_as_audio_mck { + atmel,pins = + <3 30 0x2 0x0>; /* PD30 periph B */ + }; + + pinctrl_isi_reset: isi_reset-0 { + atmel,pins = + <4 24 0x0 0x0>; /* PE24 gpio */ + }; + + pinctrl_isi_power: isi_power-0 { + atmel,pins = + <4 29 0x0 0x0>; /* PE29 gpio */ + }; + + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <3 29 0x0 0x4>; /* PD29 GPIO with deglitch */ + }; + }; + }; + + dbgu: serial@ffffee00 { + status = "okay"; + }; + + watchdog@fffffe40 { + status = "okay"; + }; + }; + + usb0: gadget@00500000 { + atmel,vbus-gpio = <&pioD 29 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00600000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioD 25 0 + &pioD 26 1 + &pioD 27 1 + >; + status = "okay"; + }; + + usb2: ehci@00700000 { + status = "okay"; + }; + }; + + sound { + compatible = "atmel,sama5d3ek-wm8904"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_audio_mck>; + + atmel,model = "wm8904 @ SAMA5D3EK"; + atmel,audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Mic"; + + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8904>; + }; +}; diff --git a/trunk/arch/arm/boot/dts/spear1340.dtsi b/trunk/arch/arm/boot/dts/spear1340.dtsi index 34da11aa6795..e1786a0b2fcd 100644 --- a/trunk/arch/arm/boot/dts/spear1340.dtsi +++ b/trunk/arch/arm/boot/dts/spear1340.dtsi @@ -113,6 +113,9 @@ reg = <0xb4100000 0x1000>; interrupts = <0 105 0x4>; status = "disabled"; + dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */ + <&dwdma0 0x680 0 1 0>; /* 0xD << 7 */ + dma-names = "tx", "rx"; }; thermal@e07008c4 { diff --git a/trunk/arch/arm/boot/dts/spear13xx.dtsi b/trunk/arch/arm/boot/dts/spear13xx.dtsi index b4ca60f4eb42..45597fd91050 100644 --- a/trunk/arch/arm/boot/dts/spear13xx.dtsi +++ b/trunk/arch/arm/boot/dts/spear13xx.dtsi @@ -98,13 +98,24 @@ reg = <0xb2800000 0x1000>; interrupts = <0 29 0x4>; status = "disabled"; + dmas = <&dwdma0 0 0 0 0>; + dma-names = "data"; }; - dma@ea800000 { + dwdma0: dma@ea800000 { compatible = "snps,dma-spear1340"; reg = <0xea800000 0x1000>; interrupts = <0 19 0x4>; status = "disabled"; + + dma-channels = <8>; + #dma-cells = <3>; + dma-requests = <32>; + chan_allocation_order = <1>; + chan_priority = <1>; + block_size = <0xfff>; + dma-masters = <2>; + data_width = <3 3 0 0>; }; dma@eb000000 { @@ -112,6 +123,15 @@ reg = <0xeb000000 0x1000>; interrupts = <0 59 0x4>; status = "disabled"; + + dma-requests = <32>; + dma-channels = <8>; + dma-masters = <2>; + #dma-cells = <3>; + chan_allocation_order = <1>; + chan_priority = <1>; + block_size = <0xfff>; + data_width = <3 3 0 0>; }; fsmc: flash@b0000000 { @@ -261,6 +281,9 @@ #size-cells = <0>; interrupts = <0 31 0x4>; status = "disabled"; + dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */ + <&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */ + dma-names = "tx", "rx"; }; rtc@e0580000 { diff --git a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts index a30aca62658a..616990dc92db 100644 --- a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts @@ -12,10 +12,22 @@ serial@70006300 { status = "okay"; - clock-frequency = <408000000>; }; pmc { nvidia,invert-interrupt; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114-pluto.dts b/trunk/arch/arm/boot/dts/tegra114-pluto.dts index 9bea8f57aa47..6bbc8efae9c0 100644 --- a/trunk/arch/arm/boot/dts/tegra114-pluto.dts +++ b/trunk/arch/arm/boot/dts/tegra114-pluto.dts @@ -12,10 +12,22 @@ serial@70006300 { status = "okay"; - clock-frequency = <408000000>; }; pmc { nvidia,invert-interrupt; }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; }; diff --git a/trunk/arch/arm/boot/dts/tegra114.dtsi b/trunk/arch/arm/boot/dts/tegra114.dtsi index 1dfaf2874c57..c1110a9b2a91 100644 --- a/trunk/arch/arm/boot/dts/tegra114.dtsi +++ b/trunk/arch/arm/boot/dts/tegra114.dtsi @@ -24,10 +24,11 @@ 0 42 0x04 0 121 0x04 0 122 0x04>; + clocks = <&tegra_car 5>; }; tegra_car: clock { - compatible = "nvidia,tegra114-car, nvidia,tegra30-car"; + compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; }; @@ -66,6 +67,7 @@ reg-shift = <2>; interrupts = <0 36 0x04>; status = "disabled"; + clocks = <&tegra_car 6>; }; serial@70006040 { @@ -74,6 +76,7 @@ reg-shift = <2>; interrupts = <0 37 0x04>; status = "disabled"; + clocks = <&tegra_car 192>; }; serial@70006200 { @@ -82,6 +85,7 @@ reg-shift = <2>; interrupts = <0 46 0x04>; status = "disabled"; + clocks = <&tegra_car 55>; }; serial@70006300 { @@ -90,17 +94,21 @@ reg-shift = <2>; interrupts = <0 90 0x04>; status = "disabled"; + clocks = <&tegra_car 65>; }; rtc { compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; }; pmc { - compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc"; + compatible = "nvidia,tegra114-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car 261>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; iommu { diff --git a/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi index 444162090042..4e3afdef28a8 100644 --- a/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-colibri-512.dtsi @@ -444,7 +444,20 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 23 0>; /* gpio PC7 */ + cd-gpios = <&gpio 23 1>; /* gpio PC7 */ + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; sound { diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra20-harmony.dts index 61d027f03617..ae9d5a20834e 100644 --- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra20-harmony.dts @@ -437,7 +437,7 @@ sdhci@c8000200 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <4>; @@ -445,12 +445,25 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + kbc { status = "okay"; nvidia,debounce-delay-ms = <2>; diff --git a/trunk/arch/arm/boot/dts/tegra20-paz00.dts b/trunk/arch/arm/boot/dts/tegra20-paz00.dts index 54d6fce00a59..fd60940e4063 100644 --- a/trunk/arch/arm/boot/dts/tegra20-paz00.dts +++ b/trunk/arch/arm/boot/dts/tegra20-paz00.dts @@ -436,7 +436,7 @@ sdhci@c8000000 { status = "okay"; - cd-gpios = <&gpio 173 0>; /* gpio PV5 */ + cd-gpios = <&gpio 173 1>; /* gpio PV5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 169 0>; /* gpio PV1 */ bus-width = <4>; @@ -447,6 +447,19 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts index 37b3a57ec0f1..4ee700a33ca5 100644 --- a/trunk/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/trunk/arch/arm/boot/dts/tegra20-seaboard.dts @@ -584,7 +584,7 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; @@ -595,6 +595,19 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi index 4766abae7a72..c19025725918 100644 --- a/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -465,12 +465,25 @@ }; sdhci@c8000600 { - cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + cd-gpios = <&gpio 58 1>; /* gpio PH2 */ wp-gpios = <&gpio 59 0>; /* gpio PH3 */ bus-width = <4>; status = "okay"; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; diff --git a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts index 5d79e4fc49a6..a9f3f06580f5 100644 --- a/trunk/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/trunk/arch/arm/boot/dts/tegra20-trimslice.dts @@ -325,11 +325,24 @@ sdhci@c8000600 { status = "okay"; - cd-gpios = <&gpio 121 0>; /* gpio PP1 */ + cd-gpios = <&gpio 121 1>; /* gpio PP1 */ wp-gpios = <&gpio 122 0>; /* gpio PP2 */ bus-width = <4>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + poweroff { compatible = "gpio-poweroff"; gpios = <&gpio 191 1>; /* gpio PX7, active low */ diff --git a/trunk/arch/arm/boot/dts/tegra20-ventana.dts b/trunk/arch/arm/boot/dts/tegra20-ventana.dts index 425c89000c20..f544806e9618 100644 --- a/trunk/arch/arm/boot/dts/tegra20-ventana.dts +++ b/trunk/arch/arm/boot/dts/tegra20-ventana.dts @@ -520,7 +520,7 @@ sdhci@c8000400 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 70 0>; /* gpio PI6 */ bus-width = <4>; @@ -531,6 +531,19 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra20-whistler.dts b/trunk/arch/arm/boot/dts/tegra20-whistler.dts index ea57c0f6dcce..258cf945f515 100644 --- a/trunk/arch/arm/boot/dts/tegra20-whistler.dts +++ b/trunk/arch/arm/boot/dts/tegra20-whistler.dts @@ -510,6 +510,7 @@ sdhci@c8000400 { status = "okay"; + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 173 0>; /* gpio PV5 */ bus-width = <8>; }; @@ -519,6 +520,19 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + kbc { status = "okay"; nvidia,debounce-delay-ms = <20>; diff --git a/trunk/arch/arm/boot/dts/tegra20.dtsi b/trunk/arch/arm/boot/dts/tegra20.dtsi index 3d3f64d2111a..fc7febc2b386 100644 --- a/trunk/arch/arm/boot/dts/tegra20.dtsi +++ b/trunk/arch/arm/boot/dts/tegra20.dtsi @@ -145,6 +145,7 @@ 0 1 0x04 0 41 0x04 0 42 0x04>; + clocks = <&tegra_car 5>; }; tegra_car: clock { @@ -304,6 +305,7 @@ compatible = "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; }; i2c@7000c000 { @@ -416,6 +418,8 @@ pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car 110>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; memory-controller@7000f000 { diff --git a/trunk/arch/arm/boot/dts/tegra30-beaver.dts b/trunk/arch/arm/boot/dts/tegra30-beaver.dts index 8ff2ff20e4a3..6248b2445b32 100644 --- a/trunk/arch/arm/boot/dts/tegra30-beaver.dts +++ b/trunk/arch/arm/boot/dts/tegra30-beaver.dts @@ -257,7 +257,7 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; @@ -268,6 +268,19 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi index 17499272a4ef..65bf2b63174e 100644 --- a/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -311,7 +311,7 @@ sdhci@78000000 { status = "okay"; - cd-gpios = <&gpio 69 0>; /* gpio PI5 */ + cd-gpios = <&gpio 69 1>; /* gpio PI5 */ wp-gpios = <&gpio 155 0>; /* gpio PT3 */ power-gpios = <&gpio 31 0>; /* gpio PD7 */ bus-width = <4>; @@ -322,6 +322,19 @@ bus-width = <8>; }; + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock { + compatible = "fixed-clock"; + reg=<0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/trunk/arch/arm/boot/dts/tegra30.dtsi b/trunk/arch/arm/boot/dts/tegra30.dtsi index dbf46c272562..9fe7a92b4c85 100644 --- a/trunk/arch/arm/boot/dts/tegra30.dtsi +++ b/trunk/arch/arm/boot/dts/tegra30.dtsi @@ -148,6 +148,7 @@ 0 42 0x04 0 121 0x04 0 122 0x04>; + clocks = <&tegra_car 5>; }; tegra_car: clock { @@ -291,6 +292,7 @@ compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>; interrupts = <0 2 0x04>; + clocks = <&tegra_car 4>; }; i2c@7000c000 { @@ -423,8 +425,10 @@ }; pmc { - compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; + compatible = "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>; + clocks = <&tegra_car 218>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; }; memory-controller { diff --git a/trunk/arch/arm/boot/dts/versatile-ab.dts b/trunk/arch/arm/boot/dts/versatile-ab.dts index e2fe3195c0d1..dde75ae8b4b1 100644 --- a/trunk/arch/arm/boot/dts/versatile-ab.dts +++ b/trunk/arch/arm/boot/dts/versatile-ab.dts @@ -121,6 +121,18 @@ interrupts = <0>; }; + timer@101e2000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x101e2000 0x1000>; + interrupts = <4>; + }; + + timer@101e3000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x101e3000 0x1000>; + interrupts = <5>; + }; + gpio0: gpio@101e4000 { compatible = "arm,pl061", "arm,primecell"; reg = <0x101e4000 0x1000>; diff --git a/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 1420bb14d95c..62d9b225dcce 100644 --- a/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/trunk/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -98,6 +98,7 @@ <0 49 4>; clocks = <&oscclk2>, <&oscclk2>; clock-names = "timclk", "apb_pclk"; + status = "disabled"; }; watchdog@100e5000 { diff --git a/trunk/arch/arm/common/timer-sp.c b/trunk/arch/arm/common/timer-sp.c index 9d2d3ba339ff..ddc740769601 100644 --- a/trunk/arch/arm/common/timer-sp.c +++ b/trunk/arch/arm/common/timer-sp.c @@ -25,33 +25,29 @@ #include #include #include +#include +#include +#include #include #include +#include -static long __init sp804_get_clock_rate(const char *name) +static long __init sp804_get_clock_rate(struct clk *clk) { - struct clk *clk; long rate; int err; - clk = clk_get_sys("sp804", name); - if (IS_ERR(clk)) { - pr_err("sp804: %s clock not found: %d\n", name, - (int)PTR_ERR(clk)); - return PTR_ERR(clk); - } - err = clk_prepare(clk); if (err) { - pr_err("sp804: %s clock failed to prepare: %d\n", name, err); + pr_err("sp804: clock failed to prepare: %d\n", err); clk_put(clk); return err; } err = clk_enable(clk); if (err) { - pr_err("sp804: %s clock failed to enable: %d\n", name, err); + pr_err("sp804: clock failed to enable: %d\n", err); clk_unprepare(clk); clk_put(clk); return err; @@ -59,7 +55,7 @@ static long __init sp804_get_clock_rate(const char *name) rate = clk_get_rate(clk); if (rate < 0) { - pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate); + pr_err("sp804: clock failed to get rate: %ld\n", rate); clk_disable(clk); clk_unprepare(clk); clk_put(clk); @@ -77,9 +73,21 @@ static u32 sp804_read(void) void __init __sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name, + struct clk *clk, int use_sched_clock) { - long rate = sp804_get_clock_rate(name); + long rate; + + if (!clk) { + clk = clk_get_sys("sp804", name); + if (IS_ERR(clk)) { + pr_err("sp804: clock not found: %d\n", + (int)PTR_ERR(clk)); + return; + } + } + + rate = sp804_get_clock_rate(clk); if (rate < 0) return; @@ -171,12 +179,20 @@ static struct irqaction sp804_timer_irq = { .dev_id = &sp804_clockevent, }; -void __init sp804_clockevents_init(void __iomem *base, unsigned int irq, - const char *name) +void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) { struct clock_event_device *evt = &sp804_clockevent; - long rate = sp804_get_clock_rate(name); + long rate; + if (!clk) + clk = clk_get_sys("sp804", name); + if (IS_ERR(clk)) { + pr_err("sp804: %s clock not found: %d\n", name, + (int)PTR_ERR(clk)); + return; + } + + rate = sp804_get_clock_rate(clk); if (rate < 0) return; @@ -186,6 +202,98 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq, evt->irq = irq; evt->cpumask = cpu_possible_mask; + writel(0, base + TIMER_CTRL); + setup_irq(irq, &sp804_timer_irq); clockevents_config_and_register(evt, rate, 0xf, 0xffffffff); } + +static void __init sp804_of_init(struct device_node *np) +{ + static bool initialized = false; + void __iomem *base; + int irq; + u32 irq_num = 0; + struct clk *clk1, *clk2; + const char *name = of_get_property(np, "compatible", NULL); + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + /* Ensure timers are disabled */ + writel(0, base + TIMER_CTRL); + writel(0, base + TIMER_2_BASE + TIMER_CTRL); + + if (initialized || !of_device_is_available(np)) + goto err; + + clk1 = of_clk_get(np, 0); + if (IS_ERR(clk1)) + clk1 = NULL; + + /* Get the 2nd clock if the timer has 2 timer clocks */ + if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) { + clk2 = of_clk_get(np, 1); + if (IS_ERR(clk2)) { + pr_err("sp804: %s clock not found: %d\n", np->name, + (int)PTR_ERR(clk2)); + goto err; + } + } else + clk2 = clk1; + + irq = irq_of_parse_and_map(np, 0); + if (irq <= 0) + goto err; + + of_property_read_u32(np, "arm,sp804-has-irq", &irq_num); + if (irq_num == 2) { + __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name); + __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1); + } else { + __sp804_clockevents_init(base, irq, clk1 , name); + __sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE, + name, clk2, 1); + } + initialized = true; + + return; +err: + iounmap(base); +} +CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init); + +static void __init integrator_cp_of_init(struct device_node *np) +{ + static int init_count = 0; + void __iomem *base; + int irq; + const char *name = of_get_property(np, "compatible", NULL); + + base = of_iomap(np, 0); + if (WARN_ON(!base)) + return; + + /* Ensure timer is disabled */ + writel(0, base + TIMER_CTRL); + + if (init_count == 2 || !of_device_is_available(np)) + goto err; + + if (!init_count) + sp804_clocksource_init(base, name); + else { + irq = irq_of_parse_and_map(np, 0); + if (irq <= 0) + goto err; + + sp804_clockevents_init(base, irq, name); + } + + init_count++; + return; +err: + iounmap(base); +} +CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init); diff --git a/trunk/arch/arm/configs/at91_dt_defconfig b/trunk/arch/arm/configs/at91_dt_defconfig index 1ea959019fcd..047f2a415309 100644 --- a/trunk/arch/arm/configs/at91_dt_defconfig +++ b/trunk/arch/arm/configs/at91_dt_defconfig @@ -20,7 +20,7 @@ CONFIG_SOC_AT91SAM9263=y CONFIG_SOC_AT91SAM9G45=y CONFIG_SOC_AT91SAM9X5=y CONFIG_SOC_AT91SAM9N12=y -CONFIG_MACH_AT91SAM_DT=y +CONFIG_MACH_AT91SAM9_DT=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=128 CONFIG_AEABI=y diff --git a/trunk/arch/arm/configs/at91sam9260_defconfig b/trunk/arch/arm/configs/at91sam9260_defconfig index 0ea5d2c97fc4..05618eb694f8 100644 --- a/trunk/arch/arm/configs/at91sam9260_defconfig +++ b/trunk/arch/arm/configs/at91sam9260_defconfig @@ -22,7 +22,7 @@ CONFIG_MACH_QIL_A9260=y CONFIG_MACH_CPU9260=y CONFIG_MACH_FLEXIBITY=y CONFIG_MACH_SNAPPER_9260=y -CONFIG_MACH_AT91SAM_DT=y +CONFIG_MACH_AT91SAM9_DT=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_ZBOOT_ROM_TEXT=0x0 diff --git a/trunk/arch/arm/configs/at91sam9g20_defconfig b/trunk/arch/arm/configs/at91sam9g20_defconfig index 3b1881033ad8..892e8287ed73 100644 --- a/trunk/arch/arm/configs/at91sam9g20_defconfig +++ b/trunk/arch/arm/configs/at91sam9g20_defconfig @@ -22,7 +22,7 @@ CONFIG_MACH_PCONTROL_G20=y CONFIG_MACH_GSIA18S=y CONFIG_MACH_USB_A9G20=y CONFIG_MACH_SNAPPER_9260=y -CONFIG_MACH_AT91SAM_DT=y +CONFIG_MACH_AT91SAM9_DT=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y diff --git a/trunk/arch/arm/configs/at91sam9g45_defconfig b/trunk/arch/arm/configs/at91sam9g45_defconfig index 606d48f3b8f8..5f551b76cb65 100644 --- a/trunk/arch/arm/configs/at91sam9g45_defconfig +++ b/trunk/arch/arm/configs/at91sam9g45_defconfig @@ -18,7 +18,7 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9G45=y CONFIG_MACH_AT91SAM9M10G45EK=y -CONFIG_MACH_AT91SAM_DT=y +CONFIG_MACH_AT91SAM9_DT=y CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_SLOW_CLOCK=y CONFIG_AEABI=y diff --git a/trunk/arch/arm/configs/multi_v7_defconfig b/trunk/arch/arm/configs/multi_v7_defconfig index e31d442343c8..3bf0c543216a 100644 --- a/trunk/arch/arm/configs/multi_v7_defconfig +++ b/trunk/arch/arm/configs/multi_v7_defconfig @@ -10,6 +10,10 @@ CONFIG_ARCH_SUNXI=y # CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA is not set CONFIG_ARCH_ZYNQ=y CONFIG_ARM_ERRATA_754322=y +CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR13XX=y +CONFIG_MACH_SPEAR1310=y +CONFIG_MACH_SPEAR1340=y CONFIG_SMP=y CONFIG_ARM_ARCH_TIMER=y CONFIG_AEABI=y @@ -23,6 +27,7 @@ CONFIG_BLK_DEV_SD=y CONFIG_ATA=y CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y +CONFIG_SATA_AHCI_PLATFORM=y CONFIG_NETDEVICES=y CONFIG_NET_CALXEDA_XGMAC=y CONFIG_SMSC911X=y @@ -31,6 +36,7 @@ CONFIG_SERIO_AMBAKMI=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y +CONFIG_KEYBOARD_SPEAR=y CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y @@ -40,6 +46,7 @@ CONFIG_I2C=y CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_SPI=y CONFIG_SPI_PL022=y +CONFIG_GPIO_PL061=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -50,6 +57,7 @@ CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_SPEAR=y CONFIG_EDAC=y CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_HIGHBANK_MC=y @@ -58,3 +66,4 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PL031=y CONFIG_DMADEVICES=y CONFIG_PL330_DMA=y +CONFIG_DW_DMAC=y diff --git a/trunk/arch/arm/configs/omap2plus_defconfig b/trunk/arch/arm/configs/omap2plus_defconfig index bd07864f14a0..33903ca0d879 100644 --- a/trunk/arch/arm/configs/omap2plus_defconfig +++ b/trunk/arch/arm/configs/omap2plus_defconfig @@ -93,6 +93,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_SENSORS_LIS3LV02D=m CONFIG_SENSORS_TSL2550=m CONFIG_SENSORS_LIS3_I2C=m +CONFIG_BMP085_I2C=m CONFIG_SCSI=y CONFIG_BLK_DEV_SD=y CONFIG_SCSI_MULTI_LUN=y diff --git a/trunk/arch/arm/configs/sama5_defconfig b/trunk/arch/arm/configs/sama5_defconfig new file mode 100644 index 000000000000..4d0dc3c16063 --- /dev/null +++ b/trunk/arch/arm/configs/sama5_defconfig @@ -0,0 +1,181 @@ +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_IRQ_DOMAIN_DEBUG=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_ARCH_AT91=y +CONFIG_SOC_SAM_V7=y +CONFIG_SOC_SAMA5D3=y +CONFIG_MACH_SAMA5_DT=y +CONFIG_AT91_PROGRAMMABLE_CLOCKS=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw" +CONFIG_AUTO_ZRELADDR=y +CONFIG_VFP=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +CONFIG_IPV6=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT_6RD=y +CONFIG_CAN=y +CONFIG_CAN_AT91=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ATMEL=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_ATMEL_TCLIB=y +CONFIG_ATMEL_SSC=y +CONFIG_EEPROM_AT24=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_MACB=y +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_QT1070=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y +# CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=4 +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_AT91=y +CONFIG_I2C_GPIO=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +CONFIG_SPI_GPIO=y +CONFIG_GPIO_SYSFS=y +# CONFIG_HWMON is not set +CONFIG_SSB=m +CONFIG_FB=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_HID_GENERIC is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ACM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_AT91=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_MMC=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_MMC_ATMELMCI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AT91RM9200=y +CONFIG_DMADEVICES=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IIO=y +CONFIG_AT91_ADC=y +CONFIG_EXT2_FS=y +CONFIG_FANOTIFY=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_DEV_ATMEL_AES=y +CONFIG_CRYPTO_DEV_ATMEL_TDES=y +CONFIG_CRYPTO_DEV_ATMEL_SHA=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_ITU_T=m diff --git a/trunk/arch/arm/configs/spear3xx_defconfig b/trunk/arch/arm/configs/spear3xx_defconfig index 865980c5f212..7ff23a077f5d 100644 --- a/trunk/arch/arm/configs/spear3xx_defconfig +++ b/trunk/arch/arm/configs/spear3xx_defconfig @@ -6,7 +6,9 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_PLAT_SPEAR=y +CONFIG_ARCH_SPEAR3XX=y CONFIG_MACH_SPEAR300=y CONFIG_MACH_SPEAR310=y CONFIG_MACH_SPEAR320=y diff --git a/trunk/arch/arm/configs/spear6xx_defconfig b/trunk/arch/arm/configs/spear6xx_defconfig index a2a1265f86b6..7822980d7d55 100644 --- a/trunk/arch/arm/configs/spear6xx_defconfig +++ b/trunk/arch/arm/configs/spear6xx_defconfig @@ -6,6 +6,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y +# CONFIG_ARCH_MULTI_V7 is not set CONFIG_PLAT_SPEAR=y CONFIG_ARCH_SPEAR6XX=y CONFIG_BINFMT_MISC=y diff --git a/trunk/arch/arm/include/asm/arch_timer.h b/trunk/arch/arm/include/asm/arch_timer.h index 7ade91d8cc6f..7c1bfc0aea0c 100644 --- a/trunk/arch/arm/include/asm/arch_timer.h +++ b/trunk/arch/arm/include/asm/arch_timer.h @@ -10,8 +10,7 @@ #include #ifdef CONFIG_ARM_ARCH_TIMER -int arch_timer_of_register(void); -int arch_timer_sched_clock_init(void); +int arch_timer_arch_init(void); /* * These register accessors are marked inline so the compiler can @@ -110,16 +109,6 @@ static inline void __cpuinit arch_counter_set_user_access(void) asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); } -#else -static inline int arch_timer_of_register(void) -{ - return -ENXIO; -} - -static inline int arch_timer_sched_clock_init(void) -{ - return -ENXIO; -} #endif #endif diff --git a/trunk/arch/arm/include/asm/delay.h b/trunk/arch/arm/include/asm/delay.h index 720799fd3a81..dff714d886d5 100644 --- a/trunk/arch/arm/include/asm/delay.h +++ b/trunk/arch/arm/include/asm/delay.h @@ -24,7 +24,7 @@ extern struct arm_delay_ops { void (*delay)(unsigned long); void (*const_udelay)(unsigned long); void (*udelay)(unsigned long); - bool const_clock; + unsigned long ticks_per_jiffy; } arm_delay_ops; #define __delay(n) arm_delay_ops.delay(n) diff --git a/trunk/arch/arm/include/asm/hardware/timer-sp.h b/trunk/arch/arm/include/asm/hardware/timer-sp.h index 2dd9d3f83f29..bb28af7c32de 100644 --- a/trunk/arch/arm/include/asm/hardware/timer-sp.h +++ b/trunk/arch/arm/include/asm/hardware/timer-sp.h @@ -1,15 +1,23 @@ +struct clk; + void __sp804_clocksource_and_sched_clock_init(void __iomem *, - const char *, int); + const char *, struct clk *, int); +void __sp804_clockevents_init(void __iomem *, unsigned int, + struct clk *, const char *); static inline void sp804_clocksource_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, 0); + __sp804_clocksource_and_sched_clock_init(base, name, NULL, 0); } static inline void sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name) { - __sp804_clocksource_and_sched_clock_init(base, name, 1); + __sp804_clocksource_and_sched_clock_init(base, name, NULL, 1); } -void sp804_clockevents_init(void __iomem *, unsigned int, const char *); +static inline void sp804_clockevents_init(void __iomem *base, unsigned int irq, const char *name) +{ + __sp804_clockevents_init(base, irq, NULL, name); + +} diff --git a/trunk/arch/arm/include/asm/highmem.h b/trunk/arch/arm/include/asm/highmem.h index 8c5e828f484d..91b99abe7a95 100644 --- a/trunk/arch/arm/include/asm/highmem.h +++ b/trunk/arch/arm/include/asm/highmem.h @@ -41,6 +41,13 @@ extern void kunmap_high(struct page *page); #endif #endif +/* + * Needed to be able to broadcast the TLB invalidation for kmap. + */ +#ifdef CONFIG_ARM_ERRATA_798181 +#undef ARCH_NEEDS_KMAP_HIGH_GET +#endif + #ifdef ARCH_NEEDS_KMAP_HIGH_GET extern void *kmap_high_get(struct page *page); #else diff --git a/trunk/arch/arm/include/asm/mmu_context.h b/trunk/arch/arm/include/asm/mmu_context.h index 863a6611323c..a7b85e0d0cc1 100644 --- a/trunk/arch/arm/include/asm/mmu_context.h +++ b/trunk/arch/arm/include/asm/mmu_context.h @@ -27,6 +27,8 @@ void __check_vmalloc_seq(struct mm_struct *mm); void check_and_switch_context(struct mm_struct *mm, struct task_struct *tsk); #define init_new_context(tsk,mm) ({ atomic64_set(&mm->context.id, 0); 0; }) +DECLARE_PER_CPU(atomic64_t, active_asids); + #else /* !CONFIG_CPU_HAS_ASID */ #ifdef CONFIG_MMU diff --git a/trunk/arch/arm/include/asm/sched_clock.h b/trunk/arch/arm/include/asm/sched_clock.h index e3f757263438..3d520ddca61b 100644 --- a/trunk/arch/arm/include/asm/sched_clock.h +++ b/trunk/arch/arm/include/asm/sched_clock.h @@ -11,4 +11,6 @@ extern void sched_clock_postinit(void); extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate); +extern unsigned long long (*sched_clock_func)(void); + #endif diff --git a/trunk/arch/arm/include/asm/tlbflush.h b/trunk/arch/arm/include/asm/tlbflush.h index 4db8c8820f0d..9e9c041358ca 100644 --- a/trunk/arch/arm/include/asm/tlbflush.h +++ b/trunk/arch/arm/include/asm/tlbflush.h @@ -450,6 +450,21 @@ static inline void local_flush_bp_all(void) isb(); } +#ifdef CONFIG_ARM_ERRATA_798181 +static inline void dummy_flush_tlb_a15_erratum(void) +{ + /* + * Dummy TLBIMVAIS. Using the unmapped address 0 and ASID 0. + */ + asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); + dsb(); +} +#else +static inline void dummy_flush_tlb_a15_erratum(void) +{ +} +#endif + /* * flush_pmd_entry * diff --git a/trunk/arch/arm/kernel/arch_timer.c b/trunk/arch/arm/kernel/arch_timer.c index d957a51435d8..59dcdced6e30 100644 --- a/trunk/arch/arm/kernel/arch_timer.c +++ b/trunk/arch/arm/kernel/arch_timer.c @@ -22,9 +22,11 @@ static unsigned long arch_timer_read_counter_long(void) return arch_timer_read_counter(); } -static u32 arch_timer_read_counter_u32(void) +static u32 sched_clock_mult __read_mostly; + +static unsigned long long notrace arch_timer_sched_clock(void) { - return arch_timer_read_counter(); + return arch_timer_read_counter() * sched_clock_mult; } static struct delay_timer arch_delay_timer; @@ -37,25 +39,20 @@ static void __init arch_timer_delay_timer_register(void) register_current_timer_delay(&arch_delay_timer); } -int __init arch_timer_of_register(void) +int __init arch_timer_arch_init(void) { - int ret; + u32 arch_timer_rate = arch_timer_get_rate(); - ret = arch_timer_init(); - if (ret) - return ret; + if (arch_timer_rate == 0) + return -ENXIO; arch_timer_delay_timer_register(); - return 0; -} - -int __init arch_timer_sched_clock_init(void) -{ - if (arch_timer_get_rate() == 0) - return -ENXIO; + /* Cache the sched_clock multiplier to save a divide in the hot path. */ + sched_clock_mult = NSEC_PER_SEC / arch_timer_rate; + sched_clock_func = arch_timer_sched_clock; + pr_info("sched_clock: ARM arch timer >56 bits at %ukHz, resolution %uns\n", + arch_timer_rate / 1000, sched_clock_mult); - setup_sched_clock(arch_timer_read_counter_u32, - 32, arch_timer_get_rate()); return 0; } diff --git a/trunk/arch/arm/kernel/entry-common.S b/trunk/arch/arm/kernel/entry-common.S index 3248cde504ed..fefd7f971437 100644 --- a/trunk/arch/arm/kernel/entry-common.S +++ b/trunk/arch/arm/kernel/entry-common.S @@ -276,7 +276,13 @@ ENDPROC(ftrace_graph_caller_old) */ .macro mcount_enter +/* + * This pad compensates for the push {lr} at the call site. Note that we are + * unable to unwind through a function which does not otherwise save its lr. + */ + UNWIND(.pad #4) stmdb sp!, {r0-r3, lr} + UNWIND(.save {r0-r3, lr}) .endm .macro mcount_get_lr reg @@ -289,6 +295,7 @@ ENDPROC(ftrace_graph_caller_old) .endm ENTRY(__gnu_mcount_nc) +UNWIND(.fnstart) #ifdef CONFIG_DYNAMIC_FTRACE mov ip, lr ldmia sp!, {lr} @@ -296,17 +303,22 @@ ENTRY(__gnu_mcount_nc) #else __mcount #endif +UNWIND(.fnend) ENDPROC(__gnu_mcount_nc) #ifdef CONFIG_DYNAMIC_FTRACE ENTRY(ftrace_caller) +UNWIND(.fnstart) __ftrace_caller +UNWIND(.fnend) ENDPROC(ftrace_caller) #endif #ifdef CONFIG_FUNCTION_GRAPH_TRACER ENTRY(ftrace_graph_caller) +UNWIND(.fnstart) __ftrace_graph_caller +UNWIND(.fnend) ENDPROC(ftrace_graph_caller) #endif diff --git a/trunk/arch/arm/kernel/head.S b/trunk/arch/arm/kernel/head.S index e0eb9a1cae77..8bac553fe213 100644 --- a/trunk/arch/arm/kernel/head.S +++ b/trunk/arch/arm/kernel/head.S @@ -267,7 +267,7 @@ __create_page_tables: addne r6, r6, #1 << SECTION_SHIFT strne r6, [r3] -#if defined(CONFIG_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) +#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) sub r4, r4, #4 @ Fixup page table pointer @ for 64-bit descriptors #endif diff --git a/trunk/arch/arm/kernel/hw_breakpoint.c b/trunk/arch/arm/kernel/hw_breakpoint.c index 96093b75ab90..5dc1aa6f0f7d 100644 --- a/trunk/arch/arm/kernel/hw_breakpoint.c +++ b/trunk/arch/arm/kernel/hw_breakpoint.c @@ -966,7 +966,7 @@ static void reset_ctrl_regs(void *unused) } if (err) { - pr_warning("CPU %d debug is powered down!\n", cpu); + pr_warn_once("CPU %d debug is powered down!\n", cpu); cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); return; } @@ -987,7 +987,7 @@ static void reset_ctrl_regs(void *unused) isb(); if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { - pr_warning("CPU %d failed to disable vector catch\n", cpu); + pr_warn_once("CPU %d failed to disable vector catch\n", cpu); return; } @@ -1007,7 +1007,7 @@ static void reset_ctrl_regs(void *unused) } if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { - pr_warning("CPU %d failed to clear debug register pairs\n", cpu); + pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu); return; } diff --git a/trunk/arch/arm/kernel/sched_clock.c b/trunk/arch/arm/kernel/sched_clock.c index bd6f56b9ec21..880584852fca 100644 --- a/trunk/arch/arm/kernel/sched_clock.c +++ b/trunk/arch/arm/kernel/sched_clock.c @@ -20,6 +20,7 @@ struct clock_data { u64 epoch_ns; u32 epoch_cyc; u32 epoch_cyc_copy; + unsigned long rate; u32 mult; u32 shift; bool suspended; @@ -113,11 +114,14 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate) u64 res, wrap; char r_unit; + if (cd.rate > rate) + return; + BUG_ON(bits > 32); WARN_ON(!irqs_disabled()); - WARN_ON(read_sched_clock != jiffy_sched_clock_read); read_sched_clock = read; sched_clock_mask = (1 << bits) - 1; + cd.rate = rate; /* calculate the mult/shift to convert counter ticks to ns. */ clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0); @@ -161,12 +165,19 @@ void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate) pr_debug("Registered %pF as sched_clock source\n", read); } -unsigned long long notrace sched_clock(void) +static unsigned long long notrace sched_clock_32(void) { u32 cyc = read_sched_clock(); return cyc_to_sched_clock(cyc, sched_clock_mask); } +unsigned long long __read_mostly (*sched_clock_func)(void) = sched_clock_32; + +unsigned long long notrace sched_clock(void) +{ + return sched_clock_func(); +} + void __init sched_clock_postinit(void) { /* diff --git a/trunk/arch/arm/kernel/setup.c b/trunk/arch/arm/kernel/setup.c index 3f6cbb2e3eda..d343a6c3a6d1 100644 --- a/trunk/arch/arm/kernel/setup.c +++ b/trunk/arch/arm/kernel/setup.c @@ -353,6 +353,23 @@ void __init early_print(const char *str, ...) printk("%s", buf); } +static void __init cpuid_init_hwcaps(void) +{ + unsigned int divide_instrs; + + if (cpu_architecture() < CPU_ARCH_ARMv7) + return; + + divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24; + + switch (divide_instrs) { + case 2: + elf_hwcap |= HWCAP_IDIVA; + case 1: + elf_hwcap |= HWCAP_IDIVT; + } +} + static void __init feat_v6_fixup(void) { int id = read_cpuid_id(); @@ -483,8 +500,11 @@ static void __init setup_processor(void) snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c", list->elf_name, ENDIANNESS); elf_hwcap = list->elf_hwcap; + + cpuid_init_hwcaps(); + #ifndef CONFIG_ARM_THUMB - elf_hwcap &= ~HWCAP_THUMB; + elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT); #endif feat_v6_fixup(); @@ -524,7 +544,7 @@ int __init arm_add_memory(phys_addr_t start, phys_addr_t size) size -= start & ~PAGE_MASK; bank->start = PAGE_ALIGN(start); -#ifndef CONFIG_LPAE +#ifndef CONFIG_ARM_LPAE if (bank->start + size < bank->start) { printk(KERN_CRIT "Truncating memory at 0x%08llx to fit in " "32-bit physical address space\n", (long long)start); diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c index 79078edbb9bc..1f2ccccaf009 100644 --- a/trunk/arch/arm/kernel/smp.c +++ b/trunk/arch/arm/kernel/smp.c @@ -673,9 +673,6 @@ static int cpufreq_callback(struct notifier_block *nb, if (freq->flags & CPUFREQ_CONST_LOOPS) return NOTIFY_OK; - if (arm_delay_ops.const_clock) - return NOTIFY_OK; - if (!per_cpu(l_p_j_ref, cpu)) { per_cpu(l_p_j_ref, cpu) = per_cpu(cpu_data, cpu).loops_per_jiffy; diff --git a/trunk/arch/arm/kernel/smp_tlb.c b/trunk/arch/arm/kernel/smp_tlb.c index bd0300531399..e82e1d248772 100644 --- a/trunk/arch/arm/kernel/smp_tlb.c +++ b/trunk/arch/arm/kernel/smp_tlb.c @@ -12,6 +12,7 @@ #include #include +#include /**********************************************************************/ @@ -69,12 +70,72 @@ static inline void ipi_flush_bp_all(void *ignored) local_flush_bp_all(); } +#ifdef CONFIG_ARM_ERRATA_798181 +static int erratum_a15_798181(void) +{ + unsigned int midr = read_cpuid_id(); + + /* Cortex-A15 r0p0..r3p2 affected */ + if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2) + return 0; + return 1; +} +#else +static int erratum_a15_798181(void) +{ + return 0; +} +#endif + +static void ipi_flush_tlb_a15_erratum(void *arg) +{ + dmb(); +} + +static void broadcast_tlb_a15_erratum(void) +{ + if (!erratum_a15_798181()) + return; + + dummy_flush_tlb_a15_erratum(); + smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum, + NULL, 1); +} + +static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm) +{ + int cpu; + cpumask_t mask = { CPU_BITS_NONE }; + + if (!erratum_a15_798181()) + return; + + dummy_flush_tlb_a15_erratum(); + for_each_online_cpu(cpu) { + if (cpu == smp_processor_id()) + continue; + /* + * We only need to send an IPI if the other CPUs are running + * the same ASID as the one being invalidated. There is no + * need for locking around the active_asids check since the + * switch_mm() function has at least one dmb() (as required by + * this workaround) in case a context switch happens on + * another CPU after the condition below. + */ + if (atomic64_read(&mm->context.id) == + atomic64_read(&per_cpu(active_asids, cpu))) + cpumask_set_cpu(cpu, &mask); + } + smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1); +} + void flush_tlb_all(void) { if (tlb_ops_need_broadcast()) on_each_cpu(ipi_flush_tlb_all, NULL, 1); else local_flush_tlb_all(); + broadcast_tlb_a15_erratum(); } void flush_tlb_mm(struct mm_struct *mm) @@ -83,6 +144,7 @@ void flush_tlb_mm(struct mm_struct *mm) on_each_cpu_mask(mm_cpumask(mm), ipi_flush_tlb_mm, mm, 1); else local_flush_tlb_mm(mm); + broadcast_tlb_mm_a15_erratum(mm); } void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) @@ -95,6 +157,7 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) &ta, 1); } else local_flush_tlb_page(vma, uaddr); + broadcast_tlb_mm_a15_erratum(vma->vm_mm); } void flush_tlb_kernel_page(unsigned long kaddr) @@ -105,6 +168,7 @@ void flush_tlb_kernel_page(unsigned long kaddr) on_each_cpu(ipi_flush_tlb_kernel_page, &ta, 1); } else local_flush_tlb_kernel_page(kaddr); + broadcast_tlb_a15_erratum(); } void flush_tlb_range(struct vm_area_struct *vma, @@ -119,6 +183,7 @@ void flush_tlb_range(struct vm_area_struct *vma, &ta, 1); } else local_flush_tlb_range(vma, start, end); + broadcast_tlb_mm_a15_erratum(vma->vm_mm); } void flush_tlb_kernel_range(unsigned long start, unsigned long end) @@ -130,6 +195,7 @@ void flush_tlb_kernel_range(unsigned long start, unsigned long end) on_each_cpu(ipi_flush_tlb_kernel_range, &ta, 1); } else local_flush_tlb_kernel_range(start, end); + broadcast_tlb_a15_erratum(); } void flush_bp_all(void) diff --git a/trunk/arch/arm/kernel/time.c b/trunk/arch/arm/kernel/time.c index 955d92d265e5..abff4e9aaee0 100644 --- a/trunk/arch/arm/kernel/time.c +++ b/trunk/arch/arm/kernel/time.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -115,6 +116,10 @@ int __init register_persistent_clock(clock_access_fn read_boot, void __init time_init(void) { - machine_desc->init_time(); + if (machine_desc->init_time) + machine_desc->init_time(); + else + clocksource_of_init(); + sched_clock_postinit(); } diff --git a/trunk/arch/arm/kvm/vgic.c b/trunk/arch/arm/kvm/vgic.c index c9a17316e9fe..0e4cfe123b38 100644 --- a/trunk/arch/arm/kvm/vgic.c +++ b/trunk/arch/arm/kvm/vgic.c @@ -883,8 +883,7 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) lr, irq, vgic_cpu->vgic_lr[lr]); BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); vgic_cpu->vgic_lr[lr] |= GICH_LR_PENDING_BIT; - - goto out; + return true; } /* Try to use another LR for this interrupt */ @@ -898,7 +897,6 @@ static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) vgic_cpu->vgic_irq_lr_map[irq] = lr; set_bit(lr, vgic_cpu->lr_used); -out: if (!vgic_irq_is_edge(vcpu, irq)) vgic_cpu->vgic_lr[lr] |= GICH_LR_EOI; @@ -1018,21 +1016,6 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) kvm_debug("MISR = %08x\n", vgic_cpu->vgic_misr); - /* - * We do not need to take the distributor lock here, since the only - * action we perform is clearing the irq_active_bit for an EOIed - * level interrupt. There is a potential race with - * the queuing of an interrupt in __kvm_vgic_flush_hwstate(), where we - * check if the interrupt is already active. Two possibilities: - * - * - The queuing is occurring on the same vcpu: cannot happen, - * as we're already in the context of this vcpu, and - * executing the handler - * - The interrupt has been migrated to another vcpu, and we - * ignore this interrupt for this run. Big deal. It is still - * pending though, and will get considered when this vcpu - * exits. - */ if (vgic_cpu->vgic_misr & GICH_MISR_EOI) { /* * Some level interrupts have been EOIed. Clear their @@ -1054,6 +1037,13 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) } else { vgic_cpu_irq_clear(vcpu, irq); } + + /* + * Despite being EOIed, the LR may not have + * been marked as empty. + */ + set_bit(lr, (unsigned long *)vgic_cpu->vgic_elrsr); + vgic_cpu->vgic_lr[lr] &= ~GICH_LR_ACTIVE_BIT; } } @@ -1064,9 +1054,8 @@ static bool vgic_process_maintenance(struct kvm_vcpu *vcpu) } /* - * Sync back the VGIC state after a guest run. We do not really touch - * the distributor here (the irq_pending_on_cpu bit is safe to set), - * so there is no need for taking its lock. + * Sync back the VGIC state after a guest run. The distributor lock is + * needed so we don't get preempted in the middle of the state processing. */ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) { @@ -1112,10 +1101,14 @@ void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) { + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + if (!irqchip_in_kernel(vcpu->kvm)) return; + spin_lock(&dist->lock); __kvm_vgic_sync_hwstate(vcpu); + spin_unlock(&dist->lock); } int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu) diff --git a/trunk/arch/arm/lib/delay.c b/trunk/arch/arm/lib/delay.c index 6b93f6a1a3c7..64dbfa57204a 100644 --- a/trunk/arch/arm/lib/delay.c +++ b/trunk/arch/arm/lib/delay.c @@ -58,7 +58,7 @@ static void __timer_delay(unsigned long cycles) static void __timer_const_udelay(unsigned long xloops) { unsigned long long loops = xloops; - loops *= loops_per_jiffy; + loops *= arm_delay_ops.ticks_per_jiffy; __timer_delay(loops >> UDELAY_SHIFT); } @@ -73,11 +73,13 @@ void __init register_current_timer_delay(const struct delay_timer *timer) pr_info("Switching to timer-based delay loop\n"); delay_timer = timer; lpj_fine = timer->freq / HZ; - loops_per_jiffy = lpj_fine; + + /* cpufreq may scale loops_per_jiffy, so keep a private copy */ + arm_delay_ops.ticks_per_jiffy = lpj_fine; arm_delay_ops.delay = __timer_delay; arm_delay_ops.const_udelay = __timer_const_udelay; arm_delay_ops.udelay = __timer_udelay; - arm_delay_ops.const_clock = true; + delay_calibrated = true; } else { pr_info("Ignoring duplicate/late registration of read_current_timer delay\n"); diff --git a/trunk/arch/arm/mach-at91/Kconfig b/trunk/arch/arm/mach-at91/Kconfig index 6071f4c3d654..02802386b894 100644 --- a/trunk/arch/arm/mach-at91/Kconfig +++ b/trunk/arch/arm/mach-at91/Kconfig @@ -1,14 +1,15 @@ if ARCH_AT91 -config HAVE_AT91_DATAFLASH_CARD - bool - config HAVE_AT91_DBGU0 bool config HAVE_AT91_DBGU1 bool +config AT91_PMC_UNIT + bool + default !ARCH_AT91X40 + config AT91_SAM9_ALT_RESET bool default !ARCH_AT91X40 @@ -17,17 +18,59 @@ config AT91_SAM9G45_RESET bool default !ARCH_AT91X40 +config AT91_SAM9_TIME + bool + config SOC_AT91SAM9 bool + select AT91_SAM9_TIME select CPU_ARM926T select GENERIC_CLOCKEVENTS select MULTI_IRQ_HANDLER select SPARSE_IRQ +config SOC_SAMA5 + bool + select AT91_SAM9_TIME + select CPU_V7 + select GENERIC_CLOCKEVENTS + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + menu "Atmel AT91 System-on-Chip" +choice + + prompt "Core type" + +config SOC_SAM_V4_V5 + bool "ARM7/ARM9" + help + Select this if you are using one of Atmel's AT91SAM9, AT91RM9200 + or AT91X40 SoC. + +config SOC_SAM_V7 + bool "Cortex A5" + help + Select this if you are using one of Atmel's SAMA5D3 SoC. + +endchoice + comment "Atmel AT91 Processor" +if SOC_SAM_V7 +config SOC_SAMA5D3 + bool "SAMA5D3 family" + depends on SOC_SAM_V7 + select SOC_SAMA5 + select HAVE_FB_ATMEL + select HAVE_AT91_DBGU1 + help + Select this if you are using one of Atmel's SAMA5D3 family SoC. + This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. +endif + +if SOC_SAM_V4_V5 config SOC_AT91RM9200 bool "AT91RM9200" select CPU_ARM920T @@ -93,394 +136,10 @@ config SOC_AT91SAM9N12 help Select this if you are using Atmel's AT91SAM9N12 SoC. -choice - prompt "Atmel AT91 Processor Devices for non DT boards" - -config ARCH_AT91_NONE - bool "None" - -config ARCH_AT91RM9200 - bool "AT91RM9200" - select SOC_AT91RM9200 - -config ARCH_AT91SAM9260 - bool "AT91SAM9260 or AT91SAM9XE" - select SOC_AT91SAM9260 - -config ARCH_AT91SAM9261 - bool "AT91SAM9261" - select SOC_AT91SAM9261 - -config ARCH_AT91SAM9G10 - bool "AT91SAM9G10" - select SOC_AT91SAM9261 - -config ARCH_AT91SAM9263 - bool "AT91SAM9263" - select SOC_AT91SAM9263 - -config ARCH_AT91SAM9RL - bool "AT91SAM9RL" - select SOC_AT91SAM9RL - -config ARCH_AT91SAM9G20 - bool "AT91SAM9G20" - select SOC_AT91SAM9260 - -config ARCH_AT91SAM9G45 - bool "AT91SAM9G45" - select SOC_AT91SAM9G45 - -config ARCH_AT91X40 - bool "AT91x40" - depends on !MMU - select ARCH_USES_GETTIMEOFFSET - select MULTI_IRQ_HANDLER - select SPARSE_IRQ - -endchoice - -config AT91_PMC_UNIT - bool - default !ARCH_AT91X40 - -# ---------------------------------------------------------- - -if ARCH_AT91RM9200 - -comment "AT91RM9200 Board Type" - -config MACH_ONEARM - bool "Ajeco 1ARM Single Board Computer" - help - Select this if you are using Ajeco's 1ARM Single Board Computer. - - -config ARCH_AT91RM9200DK - bool "Atmel AT91RM9200-DK Development board" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91RM9200-DK Development board. - (Discontinued) - -config MACH_AT91RM9200EK - bool "Atmel AT91RM9200-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. - - -config MACH_CSB337 - bool "Cogent CSB337" - help - Select this if you are using Cogent's CSB337 board. - - -config MACH_CSB637 - bool "Cogent CSB637" - help - Select this if you are using Cogent's CSB637 board. - - -config MACH_CARMEVA - bool "Conitec ARM&EVA" - help - Select this if you are using Conitec's AT91RM9200-MCU-Module. - - -config MACH_ATEB9200 - bool "Embest ATEB9200" - help - Select this if you are using Embest's ATEB9200 board. - - -config MACH_KB9200 - bool "KwikByte KB920x" - help - Select this if you are using KwikByte's KB920x board. - - -config MACH_PICOTUX2XX - bool "picotux 200" - help - Select this if you are using a picotux 200. - - -config MACH_KAFA - bool "Sperry-Sun KAFA board" - help - Select this if you are using Sperry-Sun's KAFA board. - -config MACH_ECBAT91 - bool "emQbit ECB_AT91 SBC" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using emQbit's ECB_AT91 board. - - -config MACH_YL9200 - bool "ucDragon YL-9200" - help - Select this if you are using the ucDragon YL-9200 board. - -config MACH_CPUAT91 - bool "Eukrea CPUAT91" - help - Select this if you are using the Eukrea Electromatique's - CPUAT91 board . - -config MACH_ECO920 - bool "eco920" - help - Select this if you are using the eco920 board - -config MACH_RSI_EWS - bool "RSI Embedded Webserver" - depends on ARCH_AT91RM9200 - help - Select this if you are using RSIs EWS board. -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9260 - -comment "AT91SAM9260 Variants" - -comment "AT91SAM9260 / AT91SAM9XE Board Type" - -config MACH_AT91SAM9260EK - bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit - - -config MACH_CAM60 - bool "KwikByte KB9260 (CAM60) board" - help - Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. - - -config MACH_SAM9_L9260 - bool "Olimex SAM9-L9260 board" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. - - -config MACH_AFEB9260 - bool "Custom afeb9260 board v1" - help - Select this if you are using custom afeb9260 board based on - open hardware design. Select this for revision 1 of the board. - - - -config MACH_USB_A9260 - bool "CALAO USB-A9260" - help - Select this if you are using a Calao Systems USB-A9260. - - -config MACH_QIL_A9260 - bool "CALAO QIL-A9260 board" - help - Select this if you are using a Calao Systems QIL-A9260 Board. - - -config MACH_CPU9260 - bool "Eukrea CPU9260 board" - help - Select this if you are using a Eukrea Electromatique's - CPU9260 Board - -config MACH_FLEXIBITY - bool "Flexibity Connect board" - help - Select this if you are using Flexibity Connect board - - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9261 - -comment "AT91SAM9261 Board Type" - -config MACH_AT91SAM9261EK - bool "Atmel AT91SAM9261-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. - - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9G10 - -comment "AT91SAM9G10 Board Type" - -config MACH_AT91SAM9G10EK - bool "Atmel AT91SAM9G10-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. - - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9263 - -comment "AT91SAM9263 Board Type" - -config MACH_AT91SAM9263EK - bool "Atmel AT91SAM9263-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. - - -config MACH_USB_A9263 - bool "CALAO USB-A9263" - help - Select this if you are using a Calao Systems USB-A9263. - - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9RL - -comment "AT91SAM9RL Board Type" - -config MACH_AT91SAM9RLEK - bool "Atmel AT91SAM9RL-EK Evaluation Kit" - help - Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. - -endif - # ---------------------------------------------------------- -if ARCH_AT91SAM9G20 - -comment "AT91SAM9G20 Board Type" - -config MACH_AT91SAM9G20EK - bool "Atmel AT91SAM9G20-EK Evaluation Kit" - select HAVE_AT91_DATAFLASH_CARD - help - Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit - that embeds only one SD/MMC slot. - -config MACH_AT91SAM9G20EK_2MMC - depends on MACH_AT91SAM9G20EK - bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" - help - Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit - with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and - onwards. - - -config MACH_CPU9G20 - bool "Eukrea CPU9G20 board" - help - Select this if you are using a Eukrea Electromatique's - CPU9G20 Board - -config MACH_ACMENETUSFOXG20 - bool "Acme Systems srl FOX Board G20" - help - Select this if you are using Acme Systems - FOX Board G20 - -config MACH_PORTUXG20 - bool "taskit PortuxG20" - help - Select this if you are using taskit's PortuxG20. - - -config MACH_STAMP9G20 - bool "taskit Stamp9G20 CPU module" - help - Select this if you are using taskit's Stamp9G20 CPU module on its - evaluation board. - - -config MACH_PCONTROL_G20 - bool "PControl G20 CPU module" - help - Select this if you are using taskit's Stamp9G20 CPU module on this - carrier board, beeing the decentralized unit of a building automation - system; featuring nvram, eth-switch, iso-rs485, display, io - -config MACH_GSIA18S - bool "GS_IA18_S board" - help - This enables support for the GS_IA18_S board - produced by GeoSIG Ltd company. This is an internet accelerograph. - - -config MACH_USB_A9G20 - bool "CALAO USB-A9G20" - depends on ARCH_AT91SAM9G20 - help - Select this if you are using a Calao Systems USB-A9G20. - - -endif - -if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) -comment "AT91SAM9260/AT91SAM9G20 boards" - -config MACH_SNAPPER_9260 - bool "Bluewater Systems Snapper 9260/9G20 module" - help - Select this if you are using the Bluewater Systems Snapper 9260 or - Snapper 9G20 modules. - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91SAM9G45 - -comment "AT91SAM9G45 Board Type" - -config MACH_AT91SAM9M10G45EK - bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" - help - Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. - Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 - families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. - - -endif - -# ---------------------------------------------------------- - -if ARCH_AT91X40 - -comment "AT91X40 Board Type" - -config MACH_AT91EB01 - bool "Atmel AT91EB01 Evaluation Kit" - help - Select this if you are using Atmel's AT91EB01 Evaluation Kit. - It is also a popular target for simulators such as GDB's - ARM simulator (commonly known as the ARMulator) and the - Skyeye simulator. - -endif - -# ---------------------------------------------------------- +source arch/arm/mach-at91/Kconfig.non_dt +endif # SOC_SAM_V4_V5 comment "Generic Board Type" @@ -492,7 +151,7 @@ config MACH_AT91RM9200_DT Select this if you want to experiment device-tree with an Atmel RM9200 Evaluation Kit. -config MACH_AT91SAM_DT +config MACH_AT91SAM9_DT bool "Atmel AT91SAM Evaluation Kits with device-tree support" depends on SOC_AT91SAM9 select USE_OF @@ -500,15 +159,13 @@ config MACH_AT91SAM_DT Select this if you want to experiment device-tree with an Atmel Evaluation Kit. -# ---------------------------------------------------------- - -comment "AT91 Board Options" - -config MTD_AT91_DATAFLASH_CARD - bool "Enable DataFlash Card support" - depends on HAVE_AT91_DATAFLASH_CARD +config MACH_SAMA5_DT + bool "Atmel SAMA5 Evaluation Kits with device-tree support" + depends on SOC_SAMA5 + select USE_OF help - Enable support for the DataFlash card. + Select this if you want to experiment device-tree with + an Atmel Evaluation Kit. # ---------------------------------------------------------- diff --git a/trunk/arch/arm/mach-at91/Kconfig.non_dt b/trunk/arch/arm/mach-at91/Kconfig.non_dt new file mode 100644 index 000000000000..6c24985515a2 --- /dev/null +++ b/trunk/arch/arm/mach-at91/Kconfig.non_dt @@ -0,0 +1,399 @@ +menu "Atmel Non-DT world" + +config HAVE_AT91_DATAFLASH_CARD + bool + +choice + prompt "Atmel AT91 Processor Devices for non DT boards" + +config ARCH_AT91_NONE + bool "None" + +config ARCH_AT91RM9200 + bool "AT91RM9200" + select SOC_AT91RM9200 + +config ARCH_AT91SAM9260 + bool "AT91SAM9260 or AT91SAM9XE" + select SOC_AT91SAM9260 + +config ARCH_AT91SAM9261 + bool "AT91SAM9261" + select SOC_AT91SAM9261 + +config ARCH_AT91SAM9G10 + bool "AT91SAM9G10" + select SOC_AT91SAM9261 + +config ARCH_AT91SAM9263 + bool "AT91SAM9263" + select SOC_AT91SAM9263 + +config ARCH_AT91SAM9RL + bool "AT91SAM9RL" + select SOC_AT91SAM9RL + +config ARCH_AT91SAM9G20 + bool "AT91SAM9G20" + select SOC_AT91SAM9260 + +config ARCH_AT91SAM9G45 + bool "AT91SAM9G45" + select SOC_AT91SAM9G45 + +config ARCH_AT91X40 + bool "AT91x40" + depends on !MMU + select ARCH_USES_GETTIMEOFFSET + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + +endchoice + +# ---------------------------------------------------------- + +if ARCH_AT91RM9200 + +comment "AT91RM9200 Board Type" + +config MACH_ONEARM + bool "Ajeco 1ARM Single Board Computer" + help + Select this if you are using Ajeco's 1ARM Single Board Computer. + + +config ARCH_AT91RM9200DK + bool "Atmel AT91RM9200-DK Development board" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91RM9200-DK Development board. + (Discontinued) + +config MACH_AT91RM9200EK + bool "Atmel AT91RM9200-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit. + + +config MACH_CSB337 + bool "Cogent CSB337" + help + Select this if you are using Cogent's CSB337 board. + + +config MACH_CSB637 + bool "Cogent CSB637" + help + Select this if you are using Cogent's CSB637 board. + + +config MACH_CARMEVA + bool "Conitec ARM&EVA" + help + Select this if you are using Conitec's AT91RM9200-MCU-Module. + + +config MACH_ATEB9200 + bool "Embest ATEB9200" + help + Select this if you are using Embest's ATEB9200 board. + + +config MACH_KB9200 + bool "KwikByte KB920x" + help + Select this if you are using KwikByte's KB920x board. + + +config MACH_PICOTUX2XX + bool "picotux 200" + help + Select this if you are using a picotux 200. + + +config MACH_KAFA + bool "Sperry-Sun KAFA board" + help + Select this if you are using Sperry-Sun's KAFA board. + +config MACH_ECBAT91 + bool "emQbit ECB_AT91 SBC" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using emQbit's ECB_AT91 board. + + +config MACH_YL9200 + bool "ucDragon YL-9200" + help + Select this if you are using the ucDragon YL-9200 board. + +config MACH_CPUAT91 + bool "Eukrea CPUAT91" + help + Select this if you are using the Eukrea Electromatique's + CPUAT91 board . + +config MACH_ECO920 + bool "eco920" + help + Select this if you are using the eco920 board + +config MACH_RSI_EWS + bool "RSI Embedded Webserver" + depends on ARCH_AT91RM9200 + help + Select this if you are using RSIs EWS board. +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9260 + +comment "AT91SAM9260 Variants" + +comment "AT91SAM9260 / AT91SAM9XE Board Type" + +config MACH_AT91SAM9260EK + bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit + + +config MACH_CAM60 + bool "KwikByte KB9260 (CAM60) board" + help + Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260. + + +config MACH_SAM9_L9260 + bool "Olimex SAM9-L9260 board" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. + + +config MACH_AFEB9260 + bool "Custom afeb9260 board v1" + help + Select this if you are using custom afeb9260 board based on + open hardware design. Select this for revision 1 of the board. + + + +config MACH_USB_A9260 + bool "CALAO USB-A9260" + help + Select this if you are using a Calao Systems USB-A9260. + + +config MACH_QIL_A9260 + bool "CALAO QIL-A9260 board" + help + Select this if you are using a Calao Systems QIL-A9260 Board. + + +config MACH_CPU9260 + bool "Eukrea CPU9260 board" + help + Select this if you are using a Eukrea Electromatique's + CPU9260 Board + +config MACH_FLEXIBITY + bool "Flexibity Connect board" + help + Select this if you are using Flexibity Connect board + + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9261 + +comment "AT91SAM9261 Board Type" + +config MACH_AT91SAM9261EK + bool "Atmel AT91SAM9261-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. + + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9G10 + +comment "AT91SAM9G10 Board Type" + +config MACH_AT91SAM9G10EK + bool "Atmel AT91SAM9G10-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. + + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9263 + +comment "AT91SAM9263 Board Type" + +config MACH_AT91SAM9263EK + bool "Atmel AT91SAM9263-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. + + +config MACH_USB_A9263 + bool "CALAO USB-A9263" + help + Select this if you are using a Calao Systems USB-A9263. + + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9RL + +comment "AT91SAM9RL Board Type" + +config MACH_AT91SAM9RLEK + bool "Atmel AT91SAM9RL-EK Evaluation Kit" + help + Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit. + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9G20 + +comment "AT91SAM9G20 Board Type" + +config MACH_AT91SAM9G20EK + bool "Atmel AT91SAM9G20-EK Evaluation Kit" + select HAVE_AT91_DATAFLASH_CARD + help + Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit + that embeds only one SD/MMC slot. + +config MACH_AT91SAM9G20EK_2MMC + depends on MACH_AT91SAM9G20EK + bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" + help + Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit + with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and + onwards. + + +config MACH_CPU9G20 + bool "Eukrea CPU9G20 board" + help + Select this if you are using a Eukrea Electromatique's + CPU9G20 Board + +config MACH_ACMENETUSFOXG20 + bool "Acme Systems srl FOX Board G20" + help + Select this if you are using Acme Systems + FOX Board G20 + +config MACH_PORTUXG20 + bool "taskit PortuxG20" + help + Select this if you are using taskit's PortuxG20. + + +config MACH_STAMP9G20 + bool "taskit Stamp9G20 CPU module" + help + Select this if you are using taskit's Stamp9G20 CPU module on its + evaluation board. + + +config MACH_PCONTROL_G20 + bool "PControl G20 CPU module" + help + Select this if you are using taskit's Stamp9G20 CPU module on this + carrier board, beeing the decentralized unit of a building automation + system; featuring nvram, eth-switch, iso-rs485, display, io + +config MACH_GSIA18S + bool "GS_IA18_S board" + help + This enables support for the GS_IA18_S board + produced by GeoSIG Ltd company. This is an internet accelerograph. + + +config MACH_USB_A9G20 + bool "CALAO USB-A9G20" + depends on ARCH_AT91SAM9G20 + help + Select this if you are using a Calao Systems USB-A9G20. + + +endif + +if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) +comment "AT91SAM9260/AT91SAM9G20 boards" + +config MACH_SNAPPER_9260 + bool "Bluewater Systems Snapper 9260/9G20 module" + help + Select this if you are using the Bluewater Systems Snapper 9260 or + Snapper 9G20 modules. + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91SAM9G45 + +comment "AT91SAM9G45 Board Type" + +config MACH_AT91SAM9M10G45EK + bool "Atmel AT91SAM9M10G45-EK Evaluation Kits" + help + Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. + Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10 + families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. + + +endif + +# ---------------------------------------------------------- + +if ARCH_AT91X40 + +comment "AT91X40 Board Type" + +config MACH_AT91EB01 + bool "Atmel AT91EB01 Evaluation Kit" + help + Select this if you are using Atmel's AT91EB01 Evaluation Kit. + It is also a popular target for simulators such as GDB's + ARM simulator (commonly known as the ARMulator) and the + Skyeye simulator. + +endif + +# ---------------------------------------------------------- + +comment "AT91 Board Options" + +config MTD_AT91_DATAFLASH_CARD + bool "Enable DataFlash Card support" + depends on HAVE_AT91_DATAFLASH_CARD + help + Enable support for the DataFlash card. + +endmenu diff --git a/trunk/arch/arm/mach-at91/Makefile b/trunk/arch/arm/mach-at91/Makefile index 39218ca6d8e8..788562dccb43 100644 --- a/trunk/arch/arm/mach-at91/Makefile +++ b/trunk/arch/arm/mach-at91/Makefile @@ -10,7 +10,8 @@ obj- := obj-$(CONFIG_AT91_PMC_UNIT) += clock.o obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o -obj-$(CONFIG_SOC_AT91SAM9) += at91sam926x_time.o sam9_smc.o +obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o +obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o # CPU-specific support obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o at91rm9200_time.o @@ -21,6 +22,7 @@ obj-$(CONFIG_SOC_AT91SAM9G45) += at91sam9g45.o obj-$(CONFIG_SOC_AT91SAM9N12) += at91sam9n12.o obj-$(CONFIG_SOC_AT91SAM9X5) += at91sam9x5.o obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o +obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260_devices.o @@ -87,8 +89,11 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o # AT91SAM board with device-tree -obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o -obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o +obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o +obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o + +# SAMA5 board with device-tree +obj-$(CONFIG_MACH_SAMA5_DT) += board-dt-sama5.o # AT91X40 board-specific support obj-$(CONFIG_MACH_AT91EB01) += board-eb01.o diff --git a/trunk/arch/arm/mach-at91/at91rm9200.c b/trunk/arch/arm/mach-at91/at91rm9200.c index 9706c000f294..ccce7592dbd3 100644 --- a/trunk/arch/arm/mach-at91/at91rm9200.c +++ b/trunk/arch/arm/mach-at91/at91rm9200.c @@ -384,7 +384,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { 0 /* Advanced Interrupt Controller (IRQ6) */ }; -AT91_SOC_START(rm9200) +AT91_SOC_START(at91rm9200) .map_io = at91rm9200_map_io, .default_irq_priority = at91rm9200_default_irq_priority, .ioremap_registers = at91rm9200_ioremap_registers, diff --git a/trunk/arch/arm/mach-at91/at91sam9260.c b/trunk/arch/arm/mach-at91/at91sam9260.c index b67cd5374117..1833b4c365df 100644 --- a/trunk/arch/arm/mach-at91/at91sam9260.c +++ b/trunk/arch/arm/mach-at91/at91sam9260.c @@ -395,7 +395,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -AT91_SOC_START(sam9260) +AT91_SOC_START(at91sam9260) .map_io = at91sam9260_map_io, .default_irq_priority = at91sam9260_default_irq_priority, .ioremap_registers = at91sam9260_ioremap_registers, diff --git a/trunk/arch/arm/mach-at91/at91sam9261.c b/trunk/arch/arm/mach-at91/at91sam9261.c index 0204f4cc9ebf..25efb5ac30f1 100644 --- a/trunk/arch/arm/mach-at91/at91sam9261.c +++ b/trunk/arch/arm/mach-at91/at91sam9261.c @@ -339,7 +339,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -AT91_SOC_START(sam9261) +AT91_SOC_START(at91sam9261) .map_io = at91sam9261_map_io, .default_irq_priority = at91sam9261_default_irq_priority, .ioremap_registers = at91sam9261_ioremap_registers, diff --git a/trunk/arch/arm/mach-at91/at91sam9263.c b/trunk/arch/arm/mach-at91/at91sam9263.c index 2282fd7ad3e3..f44ffd2105a7 100644 --- a/trunk/arch/arm/mach-at91/at91sam9263.c +++ b/trunk/arch/arm/mach-at91/at91sam9263.c @@ -375,7 +375,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; -AT91_SOC_START(sam9263) +AT91_SOC_START(at91sam9263) .map_io = at91sam9263_map_io, .default_irq_priority = at91sam9263_default_irq_priority, .ioremap_registers = at91sam9263_ioremap_registers, diff --git a/trunk/arch/arm/mach-at91/at91sam9g45.c b/trunk/arch/arm/mach-at91/at91sam9g45.c index c68960d82247..dc49c2c45d49 100644 --- a/trunk/arch/arm/mach-at91/at91sam9g45.c +++ b/trunk/arch/arm/mach-at91/at91sam9g45.c @@ -420,7 +420,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ0) */ }; -AT91_SOC_START(sam9g45) +AT91_SOC_START(at91sam9g45) .map_io = at91sam9g45_map_io, .default_irq_priority = at91sam9g45_default_irq_priority, .ioremap_registers = at91sam9g45_ioremap_registers, diff --git a/trunk/arch/arm/mach-at91/at91sam9n12.c b/trunk/arch/arm/mach-at91/at91sam9n12.c index 5dfc8fd87103..2c7a2f4a7568 100644 --- a/trunk/arch/arm/mach-at91/at91sam9n12.c +++ b/trunk/arch/arm/mach-at91/at91sam9n12.c @@ -226,7 +226,7 @@ void __init at91sam9n12_initialize(void) at91_extern_irq = (1 << AT91SAM9N12_ID_IRQ0); } -AT91_SOC_START(sam9n12) +AT91_SOC_START(at91sam9n12) .map_io = at91sam9n12_map_io, .register_clocks = at91sam9n12_register_clocks, .init = at91sam9n12_initialize, diff --git a/trunk/arch/arm/mach-at91/at91sam9rl.c b/trunk/arch/arm/mach-at91/at91sam9rl.c index 3de3e04d0f81..f77fae5591bc 100644 --- a/trunk/arch/arm/mach-at91/at91sam9rl.c +++ b/trunk/arch/arm/mach-at91/at91sam9rl.c @@ -341,7 +341,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -AT91_SOC_START(sam9rl) +AT91_SOC_START(at91sam9rl) .map_io = at91sam9rl_map_io, .default_irq_priority = at91sam9rl_default_irq_priority, .ioremap_registers = at91sam9rl_ioremap_registers, diff --git a/trunk/arch/arm/mach-at91/at91sam9x5.c b/trunk/arch/arm/mach-at91/at91sam9x5.c index 44a9a62dcc13..3a1a7993c125 100644 --- a/trunk/arch/arm/mach-at91/at91sam9x5.c +++ b/trunk/arch/arm/mach-at91/at91sam9x5.c @@ -320,7 +320,7 @@ static void __init at91sam9x5_map_io(void) * Interrupt initialization * -------------------------------------------------------------------- */ -AT91_SOC_START(sam9x5) +AT91_SOC_START(at91sam9x5) .map_io = at91sam9x5_map_io, .register_clocks = at91sam9x5_register_clocks, AT91_SOC_END diff --git a/trunk/arch/arm/mach-at91/board-rm9200-dt.c b/trunk/arch/arm/mach-at91/board-dt-rm9200.c similarity index 100% rename from trunk/arch/arm/mach-at91/board-rm9200-dt.c rename to trunk/arch/arm/mach-at91/board-dt-rm9200.c diff --git a/trunk/arch/arm/mach-at91/board-dt.c b/trunk/arch/arm/mach-at91/board-dt-sam9.c similarity index 100% rename from trunk/arch/arm/mach-at91/board-dt.c rename to trunk/arch/arm/mach-at91/board-dt-sam9.c diff --git a/trunk/arch/arm/mach-at91/board-dt-sama5.c b/trunk/arch/arm/mach-at91/board-dt-sama5.c new file mode 100644 index 000000000000..705305e62bbc --- /dev/null +++ b/trunk/arch/arm/mach-at91/board-dt-sama5.c @@ -0,0 +1,86 @@ +/* + * Setup code for SAMA5 Evaluation Kits with Device Tree support + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "at91_aic.h" +#include "generic.h" + + +static const struct of_device_id irq_of_match[] __initconst = { + + { .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init }, + { /*sentinel*/ } +}; + +static void __init at91_dt_init_irq(void) +{ + of_irq_init(irq_of_match); +} + +static int ksz9021rn_phy_fixup(struct phy_device *phy) +{ + int value; + +#define GMII_RCCPSR 260 +#define GMII_RRDPSR 261 +#define GMII_ERCR 11 +#define GMII_ERDWR 12 + + /* Set delay values */ + value = GMII_RCCPSR | 0x8000; + phy_write(phy, GMII_ERCR, value); + value = 0xF2F4; + phy_write(phy, GMII_ERDWR, value); + value = GMII_RRDPSR | 0x8000; + phy_write(phy, GMII_ERCR, value); + value = 0x2222; + phy_write(phy, GMII_ERDWR, value); + + return 0; +} + +static void __init sama5_dt_device_init(void) +{ + if (of_machine_is_compatible("atmel,sama5d3xcm")) + phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, + ksz9021rn_phy_fixup); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char *sama5_dt_board_compat[] __initdata = { + "atmel,sama5", + NULL +}; + +DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") + /* Maintainer: Atmel */ + .init_time = at91sam926x_pit_init, + .map_io = at91_map_io, + .handle_irq = at91_aic5_handle_irq, + .init_early = at91_dt_initialize, + .init_irq = at91_dt_init_irq, + .init_machine = sama5_dt_device_init, + .dt_compat = sama5_dt_board_compat, +MACHINE_END diff --git a/trunk/arch/arm/mach-at91/clock.c b/trunk/arch/arm/mach-at91/clock.c index 33361505c0cd..da841885d01c 100644 --- a/trunk/arch/arm/mach-at91/clock.c +++ b/trunk/arch/arm/mach-at91/clock.c @@ -54,7 +54,10 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); */ #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3()) + +#define cpu_has_1056M_plla() (cpu_is_sama5d3()) #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ || cpu_is_at91sam9g45() \ @@ -75,7 +78,8 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); || cpu_is_at91sam9n12())) #define cpu_has_upll() (cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3()) /* USB host HS & FS */ #define cpu_has_uhp() (!cpu_is_at91sam9rl()) @@ -83,18 +87,22 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); /* USB device FS only */ #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5())) + || cpu_is_at91sam9x5() \ + || cpu_is_sama5d3())) #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ - || cpu_is_at91sam9n12()) + || cpu_is_at91sam9n12() \ + || cpu_is_sama5d3()) static LIST_HEAD(clocks); static DEFINE_SPINLOCK(clk_lock); @@ -210,10 +218,26 @@ struct clk mck = { static void pmc_periph_mode(struct clk *clk, int is_on) { - if (is_on) - at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); - else - at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); + u32 regval = 0; + + /* + * With sama5d3 devices, we are managing clock division so we have to + * use the Peripheral Control Register introduced from at91sam9x5 + * devices. + */ + if (cpu_is_sama5d3()) { + regval |= AT91_PMC_PCR_CMD; /* write command */ + regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ + regval |= AT91_PMC_PCR_DIV(clk->div); + if (is_on) + regval |= AT91_PMC_PCR_EN; /* enable clock */ + at91_pmc_write(AT91_PMC_PCR, regval); + } else { + if (is_on) + at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); + else + at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); + } } static struct clk __init *at91_css_to_clk(unsigned long css) @@ -443,14 +467,18 @@ static void __init init_programmable_clock(struct clk *clk) static int at91_clk_show(struct seq_file *s, void *unused) { - u32 scsr, pcsr, uckr = 0, sr; + u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr; struct clk *clk; scsr = at91_pmc_read(AT91_PMC_SCSR); pcsr = at91_pmc_read(AT91_PMC_PCSR); + if (cpu_is_sama5d3()) + pcsr1 = at91_pmc_read(AT91_PMC_PCSR1); sr = at91_pmc_read(AT91_PMC_SR); seq_printf(s, "SCSR = %8x\n", scsr); seq_printf(s, "PCSR = %8x\n", pcsr); + if (cpu_is_sama5d3()) + seq_printf(s, "PCSR1 = %8x\n", pcsr1); seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); @@ -470,20 +498,30 @@ static int at91_clk_show(struct seq_file *s, void *unused) list_for_each_entry(clk, &clocks, node) { char *state; - if (clk->mode == pmc_sys_mode) + if (clk->mode == pmc_sys_mode) { state = (scsr & clk->pmc_mask) ? "on" : "off"; - else if (clk->mode == pmc_periph_mode) - state = (pcsr & clk->pmc_mask) ? "on" : "off"; - else if (clk->mode == pmc_uckr_mode) + } else if (clk->mode == pmc_periph_mode) { + if (cpu_is_sama5d3()) { + u32 pmc_mask = 1 << (clk->pid % 32); + + if (clk->pid > 31) + state = (pcsr1 & pmc_mask) ? "on" : "off"; + else + state = (pcsr & pmc_mask) ? "on" : "off"; + } else { + state = (pcsr & clk->pmc_mask) ? "on" : "off"; + } + } else if (clk->mode == pmc_uckr_mode) { state = (uckr & clk->pmc_mask) ? "on" : "off"; - else if (clk->pmc_mask) + } else if (clk->pmc_mask) { state = (sr & clk->pmc_mask) ? "on" : "off"; - else if (clk == &clk32k || clk == &main_clk) + } else if (clk == &clk32k || clk == &main_clk) { state = "on"; - else + } else { state = ""; + } - seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n", + seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n", clk->name, clk->users, state, clk_get_rate(clk), clk->parent ? clk->parent->name : ""); } @@ -530,6 +568,9 @@ int __init clk_register(struct clk *clk) if (clk_is_peripheral(clk)) { if (!clk->parent) clk->parent = &mck; + if (cpu_is_sama5d3()) + clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, + 1 << clk->div); clk->mode = pmc_periph_mode; } else if (clk_is_sys(clk)) { @@ -555,7 +596,11 @@ static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) unsigned mul, div; div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; + if (cpu_is_sama5d3()) + mul = AT91_PMC3_MUL_GET(reg); + else + mul = AT91_PMC_MUL_GET(reg); + if (div && mul) { freq /= div; freq *= mul + 1; @@ -706,12 +751,15 @@ static int __init at91_pmc_init(unsigned long main_clock) /* report if PLLA is more than mildly overclocked */ plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); - if (cpu_has_300M_plla()) { - if (plla.rate_hz > 300000000) + if (cpu_has_1056M_plla()) { + if (plla.rate_hz > 1056000000) pll_overclock = true; } else if (cpu_has_800M_plla()) { if (plla.rate_hz > 800000000) pll_overclock = true; + } else if (cpu_has_300M_plla()) { + if (plla.rate_hz > 300000000) + pll_overclock = true; } else if (cpu_has_240M_plla()) { if (plla.rate_hz > 240000000) pll_overclock = true; @@ -872,6 +920,7 @@ int __init at91_clock_init(unsigned long main_clock) static int __init at91_clock_reset(void) { unsigned long pcdr = 0; + unsigned long pcdr1 = 0; unsigned long scdr = 0; struct clk *clk; @@ -879,8 +928,17 @@ static int __init at91_clock_reset(void) if (clk->users > 0) continue; - if (clk->mode == pmc_periph_mode) - pcdr |= clk->pmc_mask; + if (clk->mode == pmc_periph_mode) { + if (cpu_is_sama5d3()) { + u32 pmc_mask = 1 << (clk->pid % 32); + + if (clk->pid > 31) + pcdr1 |= pmc_mask; + else + pcdr |= pmc_mask; + } else + pcdr |= clk->pmc_mask; + } if (clk->mode == pmc_sys_mode) scdr |= clk->pmc_mask; @@ -888,8 +946,9 @@ static int __init at91_clock_reset(void) pr_debug("Clocks: disable unused %s\n", clk->name); } - at91_pmc_write(AT91_PMC_PCDR, pcdr); at91_pmc_write(AT91_PMC_SCDR, scdr); + if (cpu_is_sama5d3()) + at91_pmc_write(AT91_PMC_PCDR1, pcdr1); return 0; } diff --git a/trunk/arch/arm/mach-at91/clock.h b/trunk/arch/arm/mach-at91/clock.h index c2e63e47dcbe..a98a39bbd883 100644 --- a/trunk/arch/arm/mach-at91/clock.h +++ b/trunk/arch/arm/mach-at91/clock.h @@ -20,7 +20,9 @@ struct clk { const char *name; /* unique clock name */ struct clk_lookup cl; unsigned long rate_hz; + unsigned div; /* parent clock divider */ struct clk *parent; + unsigned pid; /* peripheral ID */ u32 pmc_mask; void (*mode)(struct clk *, int); unsigned id:3; /* PCK0..4, or 32k/main/a/b */ diff --git a/trunk/arch/arm/mach-at91/cpuidle.c b/trunk/arch/arm/mach-at91/cpuidle.c index 0c6381516a5a..4c6794603780 100644 --- a/trunk/arch/arm/mach-at91/cpuidle.c +++ b/trunk/arch/arm/mach-at91/cpuidle.c @@ -38,6 +38,8 @@ static int at91_enter_idle(struct cpuidle_device *dev, at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam9g45_standby(); + else if (cpu_is_at91sam9263()) + at91sam9263_standby(); else at91sam9_standby(); diff --git a/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h b/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h index ea2c57a86ca6..31df12029c4e 100644 --- a/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/trunk/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -75,6 +75,9 @@ extern void __iomem *at91_pmc_base; #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) +#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ +#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ #define AT91_PMC_USBDIV_1 (0 << 28) #define AT91_PMC_USBDIV_2 (1 << 28) @@ -167,11 +170,18 @@ extern void __iomem *at91_pmc_base; #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ -#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9] */ +#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ +#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ +#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ + +#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ -#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command */ -#define AT91_PMC_PCR_DIV (0x3 << 16) /* Divisor Value */ -#define AT91_PMC_PCRDIV(n) (((n) << 16) & AT91_PMC_PCR_DIV) +#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ +#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ +#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ +#define AT91_PMC_PCR_DIV2 0x2 /* Peripheral clock is MCK/2 */ +#define AT91_PMC_PCR_DIV4 0x4 /* Peripheral clock is MCK/4 */ +#define AT91_PMC_PCR_DIV8 0x8 /* Peripheral clock is MCK/8 */ #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ #endif diff --git a/trunk/arch/arm/mach-at91/include/mach/cpu.h b/trunk/arch/arm/mach-at91/include/mach/cpu.h index b6504c19d55c..d3d7b993846b 100644 --- a/trunk/arch/arm/mach-at91/include/mach/cpu.h +++ b/trunk/arch/arm/mach-at91/include/mach/cpu.h @@ -36,6 +36,8 @@ #define ARCH_ID_AT91M40807 0x14080745 #define ARCH_ID_AT91R40008 0x44000840 +#define ARCH_ID_SAMA5D3 0x8A5C07C0 + #define ARCH_EXID_AT91SAM9M11 0x00000001 #define ARCH_EXID_AT91SAM9M10 0x00000002 #define ARCH_EXID_AT91SAM9G46 0x00000003 @@ -47,6 +49,11 @@ #define ARCH_EXID_AT91SAM9G25 0x00000003 #define ARCH_EXID_AT91SAM9X25 0x00000004 +#define ARCH_EXID_SAMA5D31 0x00444300 +#define ARCH_EXID_SAMA5D33 0x00414300 +#define ARCH_EXID_SAMA5D34 0x00414301 +#define ARCH_EXID_SAMA5D35 0x00584300 + #define ARCH_FAMILY_AT91X92 0x09200000 #define ARCH_FAMILY_AT91SAM9 0x01900000 #define ARCH_FAMILY_AT91SAM9XE 0x02900000 @@ -75,8 +82,11 @@ enum at91_soc_type { /* SAM9N12 */ AT91_SOC_SAM9N12, + /* SAMA5D3 */ + AT91_SOC_SAMA5D3, + /* Unknown type */ - AT91_SOC_NONE + AT91_SOC_UNKNOWN, }; enum at91_soc_subtype { @@ -93,8 +103,15 @@ enum at91_soc_subtype { AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, + /* SAMA5D3 */ + AT91_SOC_SAMA5D31, AT91_SOC_SAMA5D33, AT91_SOC_SAMA5D34, + AT91_SOC_SAMA5D35, + + /* No subtype for this SoC */ + AT91_SOC_SUBTYPE_NONE, + /* Unknown subtype */ - AT91_SOC_SUBTYPE_NONE + AT91_SOC_SUBTYPE_UNKNOWN, }; struct at91_socinfo { @@ -108,7 +125,7 @@ const char *at91_get_soc_subtype(struct at91_socinfo *c); static inline int at91_soc_is_detected(void) { - return at91_soc_initdata.type != AT91_SOC_NONE; + return at91_soc_initdata.type != AT91_SOC_UNKNOWN; } #ifdef CONFIG_SOC_AT91RM9200 @@ -187,6 +204,12 @@ static inline int at91_soc_is_detected(void) #define cpu_is_at91sam9n12() (0) #endif +#ifdef CONFIG_SOC_SAMA5D3 +#define cpu_is_sama5d3() (at91_soc_initdata.type == AT91_SOC_SAMA5D3) +#else +#define cpu_is_sama5d3() (0) +#endif + /* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers. diff --git a/trunk/arch/arm/mach-at91/include/mach/sama5d3.h b/trunk/arch/arm/mach-at91/include/mach/sama5d3.h new file mode 100644 index 000000000000..6dc81ee38048 --- /dev/null +++ b/trunk/arch/arm/mach-at91/include/mach/sama5d3.h @@ -0,0 +1,73 @@ +/* + * Chip-specific header file for the SAMA5D3 family + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Common definitions. + * Based on SAMA5D3 datasheet. + * + * Licensed under GPLv2 or later. + */ + +#ifndef SAMA5D3_H +#define SAMA5D3_H + +/* + * Peripheral identifiers/interrupts. + */ +#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91_ID_SYS 1 /* System Peripherals */ +#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ +#define AT91_ID_PIT 3 /* PIT */ +#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */ +#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */ +#define SAMA5D3_ID_PIOA 6 /* PIOA */ +#define SAMA5D3_ID_PIOB 7 /* PIOB */ +#define SAMA5D3_ID_PIOC 8 /* PIOC */ +#define SAMA5D3_ID_PIOD 9 /* PIOD */ +#define SAMA5D3_ID_PIOE 10 /* PIOE */ +#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ +#define SAMA5D3_ID_USART0 12 /* USART0 */ +#define SAMA5D3_ID_USART1 13 /* USART1 */ +#define SAMA5D3_ID_USART2 14 /* USART2 */ +#define SAMA5D3_ID_USART3 15 /* USART3 */ +#define SAMA5D3_ID_UART0 16 /* UART 0 */ +#define SAMA5D3_ID_UART1 17 /* UART 1 */ +#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ +#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ +#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ +#define SAMA5D3_ID_HSMCI0 21 /* MCI */ +#define SAMA5D3_ID_HSMCI1 22 /* MCI */ +#define SAMA5D3_ID_HSMCI2 23 /* MCI */ +#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ +#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ +#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */ +#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */ +#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ +#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ +#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ +#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ +#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ +#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ +#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ +#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ +#define SAMA5D3_ID_LCDC 36 /* LCD Controller */ +#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ +#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ +#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ +#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */ +#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */ +#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ +#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ +#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ +#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */ +#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ + +/* + * Internal Memory + */ +#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ +#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ + +#endif diff --git a/trunk/arch/arm/mach-at91/pm.c b/trunk/arch/arm/mach-at91/pm.c index 73f1f250403a..530db304ec5e 100644 --- a/trunk/arch/arm/mach-at91/pm.c +++ b/trunk/arch/arm/mach-at91/pm.c @@ -270,6 +270,8 @@ static int at91_pm_enter(suspend_state_t state) at91rm9200_standby(); else if (cpu_is_at91sam9g45()) at91sam9g45_standby(); + else if (cpu_is_at91sam9263()) + at91sam9263_standby(); else at91sam9_standby(); break; diff --git a/trunk/arch/arm/mach-at91/pm.h b/trunk/arch/arm/mach-at91/pm.h index 38f467c6b710..2f5908f0b8c5 100644 --- a/trunk/arch/arm/mach-at91/pm.h +++ b/trunk/arch/arm/mach-at91/pm.h @@ -70,13 +70,31 @@ static inline void at91sam9g45_standby(void) at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } -#ifdef CONFIG_SOC_AT91SAM9263 -/* - * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use; - * handle those cases both here and in the Suspend-To-RAM support. +/* We manage both DDRAM/SDRAM controllers, we need more than one value to + * remember. */ -#warning Assuming EB1 SDRAM controller is *NOT* used -#endif +static inline void at91sam9263_standby(void) +{ + u32 lpr0, lpr1; + u32 saved_lpr0, saved_lpr1; + + saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR); + lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB; + lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + + saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR); + lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB; + lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH; + + /* self-refresh mode now */ + at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0); + at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1); + + cpu_do_idle(); + + at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0); + at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1); +} static inline void at91sam9_standby(void) { diff --git a/trunk/arch/arm/mach-at91/sama5d3.c b/trunk/arch/arm/mach-at91/sama5d3.c new file mode 100644 index 000000000000..401279715ab1 --- /dev/null +++ b/trunk/arch/arm/mach-at91/sama5d3.c @@ -0,0 +1,377 @@ +/* + * Chip-specific setup code for the SAMA5D3 family + * + * Copyright (C) 2013 Atmel, + * 2013 Ludovic Desroches + * + * Licensed under GPLv2 or later. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "soc.h" +#include "generic.h" +#include "clock.h" +#include "sam9_smc.h" + +/* -------------------------------------------------------------------- + * Clocks + * -------------------------------------------------------------------- */ + +/* + * The peripheral clocks. + */ + +static struct clk pioA_clk = { + .name = "pioA_clk", + .pid = SAMA5D3_ID_PIOA, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioB_clk = { + .name = "pioB_clk", + .pid = SAMA5D3_ID_PIOB, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioC_clk = { + .name = "pioC_clk", + .pid = SAMA5D3_ID_PIOC, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioD_clk = { + .name = "pioD_clk", + .pid = SAMA5D3_ID_PIOD, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk pioE_clk = { + .name = "pioE_clk", + .pid = SAMA5D3_ID_PIOE, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk usart0_clk = { + .name = "usart0_clk", + .pid = SAMA5D3_ID_USART0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk usart1_clk = { + .name = "usart1_clk", + .pid = SAMA5D3_ID_USART1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk usart2_clk = { + .name = "usart2_clk", + .pid = SAMA5D3_ID_USART2, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk usart3_clk = { + .name = "usart3_clk", + .pid = SAMA5D3_ID_USART3, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk uart0_clk = { + .name = "uart0_clk", + .pid = SAMA5D3_ID_UART0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk uart1_clk = { + .name = "uart1_clk", + .pid = SAMA5D3_ID_UART1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk twi0_clk = { + .name = "twi0_clk", + .pid = SAMA5D3_ID_TWI0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk twi1_clk = { + .name = "twi1_clk", + .pid = SAMA5D3_ID_TWI1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk twi2_clk = { + .name = "twi2_clk", + .pid = SAMA5D3_ID_TWI2, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk mmc0_clk = { + .name = "mci0_clk", + .pid = SAMA5D3_ID_HSMCI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc1_clk = { + .name = "mci1_clk", + .pid = SAMA5D3_ID_HSMCI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk mmc2_clk = { + .name = "mci2_clk", + .pid = SAMA5D3_ID_HSMCI2, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi0_clk = { + .name = "spi0_clk", + .pid = SAMA5D3_ID_SPI0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk spi1_clk = { + .name = "spi1_clk", + .pid = SAMA5D3_ID_SPI1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tcb0_clk = { + .name = "tcb0_clk", + .pid = SAMA5D3_ID_TC0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk tcb1_clk = { + .name = "tcb1_clk", + .pid = SAMA5D3_ID_TC1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk adc_clk = { + .name = "adc_clk", + .pid = SAMA5D3_ID_ADC, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk adc_op_clk = { + .name = "adc_op_clk", + .type = CLK_TYPE_PERIPHERAL, + .rate_hz = 5000000, +}; +static struct clk dma0_clk = { + .name = "dma0_clk", + .pid = SAMA5D3_ID_DMA0, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk dma1_clk = { + .name = "dma1_clk", + .pid = SAMA5D3_ID_DMA1, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk uhphs_clk = { + .name = "uhphs", + .pid = SAMA5D3_ID_UHPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk udphs_clk = { + .name = "udphs_clk", + .pid = SAMA5D3_ID_UDPHS, + .type = CLK_TYPE_PERIPHERAL, +}; +/* gmac only for sama5d33, sama5d34, sama5d35 */ +static struct clk macb0_clk = { + .name = "macb0_clk", + .pid = SAMA5D3_ID_GMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +/* emac only for sama5d31, sama5d35 */ +static struct clk macb1_clk = { + .name = "macb1_clk", + .pid = SAMA5D3_ID_EMAC, + .type = CLK_TYPE_PERIPHERAL, +}; +/* lcd only for sama5d31, sama5d33, sama5d34 */ +static struct clk lcdc_clk = { + .name = "lcdc_clk", + .pid = SAMA5D3_ID_LCDC, + .type = CLK_TYPE_PERIPHERAL, +}; +/* isi only for sama5d33, sama5d35 */ +static struct clk isi_clk = { + .name = "isi_clk", + .pid = SAMA5D3_ID_ISI, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk can0_clk = { + .name = "can0_clk", + .pid = SAMA5D3_ID_CAN0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk can1_clk = { + .name = "can1_clk", + .pid = SAMA5D3_ID_CAN1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk ssc0_clk = { + .name = "ssc0_clk", + .pid = SAMA5D3_ID_SSC0, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk ssc1_clk = { + .name = "ssc1_clk", + .pid = SAMA5D3_ID_SSC1, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV2, +}; +static struct clk sha_clk = { + .name = "sha_clk", + .pid = SAMA5D3_ID_SHA, + .type = CLK_TYPE_PERIPHERAL, + .div = AT91_PMC_PCR_DIV8, +}; +static struct clk aes_clk = { + .name = "aes_clk", + .pid = SAMA5D3_ID_AES, + .type = CLK_TYPE_PERIPHERAL, +}; +static struct clk tdes_clk = { + .name = "tdes_clk", + .pid = SAMA5D3_ID_TDES, + .type = CLK_TYPE_PERIPHERAL, +}; + +static struct clk *periph_clocks[] __initdata = { + &pioA_clk, + &pioB_clk, + &pioC_clk, + &pioD_clk, + &pioE_clk, + &usart0_clk, + &usart1_clk, + &usart2_clk, + &usart3_clk, + &uart0_clk, + &uart1_clk, + &twi0_clk, + &twi1_clk, + &twi2_clk, + &mmc0_clk, + &mmc1_clk, + &mmc2_clk, + &spi0_clk, + &spi1_clk, + &tcb0_clk, + &tcb1_clk, + &adc_clk, + &adc_op_clk, + &dma0_clk, + &dma1_clk, + &uhphs_clk, + &udphs_clk, + &macb0_clk, + &macb1_clk, + &lcdc_clk, + &isi_clk, + &can0_clk, + &can1_clk, + &ssc0_clk, + &ssc1_clk, + &sha_clk, + &aes_clk, + &tdes_clk, +}; + +static struct clk pck0 = { + .name = "pck0", + .pmc_mask = AT91_PMC_PCK0, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 0, +}; + +static struct clk pck1 = { + .name = "pck1", + .pmc_mask = AT91_PMC_PCK1, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 1, +}; + +static struct clk pck2 = { + .name = "pck2", + .pmc_mask = AT91_PMC_PCK2, + .type = CLK_TYPE_PROGRAMMABLE, + .id = 2, +}; + +static struct clk_lookup periph_clocks_lookups[] = { + /* lookup table for DT entries */ + CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), + CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), + CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), + CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), + CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), + CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), + CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), + CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), + CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), + CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), + CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), + CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), + CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), + CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), + CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), + CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), + CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), + CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), + CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), + CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), + CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), + CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), + CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), + CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), + CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), + CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), + CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), + CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), + CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), + CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), + CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), + CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), + CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), + CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), + CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), + CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), + CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), +}; + +static void __init sama5d3_register_clocks(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) + clk_register(periph_clocks[i]); + + clkdev_add_table(periph_clocks_lookups, + ARRAY_SIZE(periph_clocks_lookups)); + + clk_register(&pck0); + clk_register(&pck1); + clk_register(&pck2); +} + +/* -------------------------------------------------------------------- + * AT91SAM9x5 processor initialization + * -------------------------------------------------------------------- */ + +static void __init sama5d3_map_io(void) +{ + at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); +} + +AT91_SOC_START(sama5d3) + .map_io = sama5d3_map_io, + .register_clocks = sama5d3_register_clocks, +AT91_SOC_END diff --git a/trunk/arch/arm/mach-at91/setup.c b/trunk/arch/arm/mach-at91/setup.c index 4b678478cf95..fd00a09da86b 100644 --- a/trunk/arch/arm/mach-at91/setup.c +++ b/trunk/arch/arm/mach-at91/setup.c @@ -105,28 +105,32 @@ static void __init soc_detect(u32 dbgu_base) switch (socid) { case ARCH_ID_AT91RM9200: at91_soc_initdata.type = AT91_SOC_RM9200; - if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE) + if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_UNKNOWN) at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; at91_boot_soc = at91rm9200_soc; break; case ARCH_ID_AT91SAM9260: at91_soc_initdata.type = AT91_SOC_SAM9260; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; at91_boot_soc = at91sam9260_soc; break; case ARCH_ID_AT91SAM9261: at91_soc_initdata.type = AT91_SOC_SAM9261; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; at91_boot_soc = at91sam9261_soc; break; case ARCH_ID_AT91SAM9263: at91_soc_initdata.type = AT91_SOC_SAM9263; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; at91_boot_soc = at91sam9263_soc; break; case ARCH_ID_AT91SAM9G20: at91_soc_initdata.type = AT91_SOC_SAM9G20; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; at91_boot_soc = at91sam9260_soc; break; @@ -139,6 +143,7 @@ static void __init soc_detect(u32 dbgu_base) case ARCH_ID_AT91SAM9RL64: at91_soc_initdata.type = AT91_SOC_SAM9RL; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; at91_boot_soc = at91sam9rl_soc; break; @@ -151,11 +156,17 @@ static void __init soc_detect(u32 dbgu_base) at91_soc_initdata.type = AT91_SOC_SAM9N12; at91_boot_soc = at91sam9n12_soc; break; + + case ARCH_ID_SAMA5D3: + at91_soc_initdata.type = AT91_SOC_SAMA5D3; + at91_boot_soc = sama5d3_soc; + break; } /* at91sam9g10 */ if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { at91_soc_initdata.type = AT91_SOC_SAM9G10; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; at91_boot_soc = at91sam9261_soc; } /* at91sam9xe */ @@ -206,6 +217,23 @@ static void __init soc_detect(u32 dbgu_base) break; } } + + if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) { + switch (at91_soc_initdata.exid) { + case ARCH_EXID_SAMA5D31: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D31; + break; + case ARCH_EXID_SAMA5D33: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D33; + break; + case ARCH_EXID_SAMA5D34: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D34; + break; + case ARCH_EXID_SAMA5D35: + at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; + break; + } + } } static const char *soc_name[] = { @@ -219,7 +247,8 @@ static const char *soc_name[] = { [AT91_SOC_SAM9RL] = "at91sam9rl", [AT91_SOC_SAM9X5] = "at91sam9x5", [AT91_SOC_SAM9N12] = "at91sam9n12", - [AT91_SOC_NONE] = "Unknown" + [AT91_SOC_SAMA5D3] = "sama5d3", + [AT91_SOC_UNKNOWN] = "Unknown", }; const char *at91_get_soc_type(struct at91_socinfo *c) @@ -241,7 +270,12 @@ static const char *soc_subtype_name[] = { [AT91_SOC_SAM9X35] = "at91sam9x35", [AT91_SOC_SAM9G25] = "at91sam9g25", [AT91_SOC_SAM9X25] = "at91sam9x25", - [AT91_SOC_SUBTYPE_NONE] = "Unknown" + [AT91_SOC_SAMA5D31] = "sama5d31", + [AT91_SOC_SAMA5D33] = "sama5d33", + [AT91_SOC_SAMA5D34] = "sama5d34", + [AT91_SOC_SAMA5D35] = "sama5d35", + [AT91_SOC_SUBTYPE_NONE] = "None", + [AT91_SOC_SUBTYPE_UNKNOWN] = "Unknown", }; const char *at91_get_soc_subtype(struct at91_socinfo *c) @@ -255,8 +289,8 @@ void __init at91_map_io(void) /* Map peripherals */ iotable_init(&at91_io_desc, 1); - at91_soc_initdata.type = AT91_SOC_NONE; - at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; + at91_soc_initdata.type = AT91_SOC_UNKNOWN; + at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_UNKNOWN; soc_detect(AT91_BASE_DBGU0); if (!at91_soc_is_detected()) @@ -267,8 +301,9 @@ void __init at91_map_io(void) pr_info("AT91: Detected soc type: %s\n", at91_get_soc_type(&at91_soc_initdata)); - pr_info("AT91: Detected soc subtype: %s\n", - at91_get_soc_subtype(&at91_soc_initdata)); + if (at91_soc_initdata.subtype != AT91_SOC_SUBTYPE_NONE) + pr_info("AT91: Detected soc subtype: %s\n", + at91_get_soc_subtype(&at91_soc_initdata)); if (!at91_soc_is_enabled()) panic("AT91: Soc not enabled"); diff --git a/trunk/arch/arm/mach-at91/soc.h b/trunk/arch/arm/mach-at91/soc.h index 9c6d3d4f9a23..43a225f9e713 100644 --- a/trunk/arch/arm/mach-at91/soc.h +++ b/trunk/arch/arm/mach-at91/soc.h @@ -22,9 +22,10 @@ extern struct at91_init_soc at91sam9g45_soc; extern struct at91_init_soc at91sam9rl_soc; extern struct at91_init_soc at91sam9x5_soc; extern struct at91_init_soc at91sam9n12_soc; +extern struct at91_init_soc sama5d3_soc; #define AT91_SOC_START(_name) \ -struct at91_init_soc __initdata at91##_name##_soc \ +struct at91_init_soc __initdata _name##_soc \ __used \ = { \ .builtin = 1, \ @@ -68,3 +69,7 @@ static inline int at91_soc_is_enabled(void) #if !defined(CONFIG_SOC_AT91SAM9N12) #define at91sam9n12_soc at91_boot_soc #endif + +#if !defined(CONFIG_SOC_SAMA5D3) +#define sama5d3_soc at91_boot_soc +#endif diff --git a/trunk/arch/arm/mach-cns3xxx/core.c b/trunk/arch/arm/mach-cns3xxx/core.c index e698f26cc0cb..52e4bb5cf12d 100644 --- a/trunk/arch/arm/mach-cns3xxx/core.c +++ b/trunk/arch/arm/mach-cns3xxx/core.c @@ -22,19 +22,9 @@ static struct map_desc cns3xxx_io_desc[] __initdata = { { - .virtual = CNS3XXX_TC11MP_TWD_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_TWD_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_CPU_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_GIC_DIST_BASE), - .length = SZ_4K, + .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, + .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE), + .length = SZ_8K, .type = MT_DEVICE, }, { .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, diff --git a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h index 191c8e57f289..b1021aafa481 100644 --- a/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h +++ b/trunk/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h @@ -94,10 +94,10 @@ #define RTC_INTR_STS_OFFSET 0x34 #define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ -#define CNS3XXX_MISC_BASE_VIRT 0xFFF07000 /* Misc Control */ +#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */ #define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ -#define CNS3XXX_PM_BASE_VIRT 0xFFF08000 +#define CNS3XXX_PM_BASE_VIRT 0xFB001000 #define PM_CLK_GATE_OFFSET 0x00 #define PM_SOFT_RST_OFFSET 0x04 @@ -109,7 +109,7 @@ #define PM_PLL_HM_PD_OFFSET 0x1C #define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ -#define CNS3XXX_UART0_BASE_VIRT 0xFFF09000 +#define CNS3XXX_UART0_BASE_VIRT 0xFB002000 #define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ #define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000 @@ -130,7 +130,7 @@ #define CNS3XXX_I2S_BASE_VIRT 0xFFF10000 #define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ -#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFFF10800 +#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 #define TIMER1_COUNTER_OFFSET 0x00 #define TIMER1_AUTO_RELOAD_OFFSET 0x04 @@ -227,16 +227,16 @@ * Testchip peripheral and fpga gic regions */ #define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ -#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFF000000 +#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000 #define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT 0xFF000100 +#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100) #define CNS3XXX_TC11MP_TWD_BASE 0x90000600 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT 0xFF000600 +#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600) #define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT 0xFF001000 +#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) #define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ #define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000 diff --git a/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h b/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h index d2afb4dd82ab..b5cc77d2380b 100644 --- a/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/uncompress.h @@ -47,9 +47,13 @@ static void __raw_writel(unsigned int value, unsigned int ptr) static inline void putc(int c) { - /* Transmit fifo not full? */ - while (__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF) - ; + int i; + + for (i = 0; i < 10000; i++) { + /* Transmit fifo not full? */ + if (!(__raw_readb(PHYS_UART_FLAG) & UART_FLAG_TXFF)) + break; + } __raw_writeb(c, PHYS_UART_DATA); } diff --git a/trunk/arch/arm/mach-exynos/Kconfig b/trunk/arch/arm/mach-exynos/Kconfig index 2f45906d6ee5..faca4326b46a 100644 --- a/trunk/arch/arm/mach-exynos/Kconfig +++ b/trunk/arch/arm/mach-exynos/Kconfig @@ -79,12 +79,6 @@ config SOC_EXYNOS5440 help Enable EXYNOS5440 SoC support -config EXYNOS4_MCT - bool - default y - help - Use MCT (Multi Core Timer) as kernel timers - config EXYNOS_DEV_DMA bool help @@ -406,6 +400,7 @@ config MACH_EXYNOS4_DT bool "Samsung Exynos4 Machine using device tree" depends on ARCH_EXYNOS4 select ARM_AMBA + select CLKSRC_OF select CPU_EXYNOS4210 select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD select PINCTRL @@ -422,6 +417,7 @@ config MACH_EXYNOS5_DT default y depends on ARCH_EXYNOS5 select ARM_AMBA + select CLKSRC_OF select USE_OF help Machine support for Samsung EXYNOS5 machine with device tree enabled. diff --git a/trunk/arch/arm/mach-exynos/Makefile b/trunk/arch/arm/mach-exynos/Makefile index 435757e57bb4..daf289b21486 100644 --- a/trunk/arch/arm/mach-exynos/Makefile +++ b/trunk/arch/arm/mach-exynos/Makefile @@ -26,8 +26,6 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o -obj-$(CONFIG_EXYNOS4_MCT) += mct.o - obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o # machine support diff --git a/trunk/arch/arm/mach-exynos/common.c b/trunk/arch/arm/mach-exynos/common.c index bdd957978d9b..db7dbd0eb6b4 100644 --- a/trunk/arch/arm/mach-exynos/common.c +++ b/trunk/arch/arm/mach-exynos/common.c @@ -256,11 +256,6 @@ static struct map_desc exynos5_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), .length = SZ_4K, .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_SYSTIMER, - .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER), - .length = SZ_4K, - .type = MT_DEVICE, }, { .virtual = (unsigned long)S5P_VA_SYSRAM, .pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM), diff --git a/trunk/arch/arm/mach-exynos/common.h b/trunk/arch/arm/mach-exynos/common.h index 9339bb8954be..3b186eaaaa7b 100644 --- a/trunk/arch/arm/mach-exynos/common.h +++ b/trunk/arch/arm/mach-exynos/common.h @@ -12,7 +12,7 @@ #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #define __ARCH_ARM_MACH_EXYNOS_COMMON_H -extern void exynos4_timer_init(void); +extern void mct_init(void); struct map_desc; void exynos_init_io(struct map_desc *mach_desc, int size); diff --git a/trunk/arch/arm/mach-exynos/include/mach/irqs.h b/trunk/arch/arm/mach-exynos/include/mach/irqs.h index 1f4dc35cd4b9..c0e75d8dd737 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/irqs.h +++ b/trunk/arch/arm/mach-exynos/include/mach/irqs.h @@ -30,8 +30,6 @@ /* For EXYNOS4 and EXYNOS5 */ -#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12) - #define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32) /* For EXYNOS4 SoCs */ @@ -323,8 +321,6 @@ #define EXYNOS5_IRQ_CEC IRQ_SPI(114) #define EXYNOS5_IRQ_SATA IRQ_SPI(115) -#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120) -#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121) #define EXYNOS5_IRQ_MMC44 IRQ_SPI(123) #define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124) #define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125) @@ -419,8 +415,6 @@ #define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4) #define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0) -#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3) -#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4) #define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0) #define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1) diff --git a/trunk/arch/arm/mach-exynos/include/mach/map.h b/trunk/arch/arm/mach-exynos/include/mach/map.h index 1df6abbf53b8..7f99b7b187d6 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/map.h +++ b/trunk/arch/arm/mach-exynos/include/mach/map.h @@ -65,7 +65,6 @@ #define EXYNOS5_PA_CMU 0x10010000 #define EXYNOS4_PA_SYSTIMER 0x10050000 -#define EXYNOS5_PA_SYSTIMER 0x101C0000 #define EXYNOS4_PA_WATCHDOG 0x10060000 #define EXYNOS5_PA_WATCHDOG 0x101D0000 diff --git a/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h deleted file mode 100644 index 80dd02ad6d61..000000000000 --- a/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h +++ /dev/null @@ -1,53 +0,0 @@ -/* arch/arm/mach-exynos4/include/mach/regs-mct.h - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 MCT configutation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_MCT_H -#define __ASM_ARCH_REGS_MCT_H __FILE__ - -#include - -#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x)) - -#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) -#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) -#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) - -#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) -#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) -#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) - -#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) - -#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) -#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) -#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) - -#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) -#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) -#define EXYNOS4_MCT_L_MASK (0xffffff00) - -#define MCT_L_TCNTB_OFFSET (0x00) -#define MCT_L_ICNTB_OFFSET (0x08) -#define MCT_L_TCON_OFFSET (0x20) -#define MCT_L_INT_CSTAT_OFFSET (0x30) -#define MCT_L_INT_ENB_OFFSET (0x34) -#define MCT_L_WSTAT_OFFSET (0x40) - -#define MCT_G_TCON_START (1 << 8) -#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) -#define MCT_G_TCON_COMP0_ENABLE (1 << 0) - -#define MCT_L_TCON_INTERVAL_MODE (1 << 2) -#define MCT_L_TCON_INT_START (1 << 1) -#define MCT_L_TCON_TIMER_START (1 << 0) - -#endif /* __ASM_ARCH_REGS_MCT_H */ diff --git a/trunk/arch/arm/mach-exynos/mach-armlex4210.c b/trunk/arch/arm/mach-exynos/mach-armlex4210.c index 685f29173afa..3b1a34742679 100644 --- a/trunk/arch/arm/mach-exynos/mach-armlex4210.c +++ b/trunk/arch/arm/mach-exynos/mach-armlex4210.c @@ -202,6 +202,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210") .map_io = armlex4210_map_io, .init_machine = armlex4210_machine_init, .init_late = exynos_init_late, - .init_time = exynos4_timer_init, + .init_time = mct_init, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c index 3358088c822a..c4ae108e192d 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c @@ -13,6 +13,7 @@ #include #include +#include #include #include @@ -142,7 +143,7 @@ DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)") .map_io = exynos4_dt_map_io, .init_machine = exynos4_dt_machine_init, .init_late = exynos_init_late, - .init_time = exynos4_timer_init, + .init_time = clocksource_of_init, .dt_compat = exynos4_dt_compat, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c index acaeb14db54b..be7eaac0df01 100644 --- a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -216,7 +217,6 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") .map_io = exynos5_dt_map_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, - .init_time = exynos4_timer_init, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve, diff --git a/trunk/arch/arm/mach-exynos/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c index 1ea79730187f..da3605d15110 100644 --- a/trunk/arch/arm/mach-exynos/mach-nuri.c +++ b/trunk/arch/arm/mach-exynos/mach-nuri.c @@ -1380,7 +1380,7 @@ MACHINE_START(NURI, "NURI") .map_io = nuri_map_io, .init_machine = nuri_machine_init, .init_late = exynos_init_late, - .init_time = exynos4_timer_init, + .init_time = mct_init, .reserve = &nuri_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c index 579d2d171daa..1772cd284f4c 100644 --- a/trunk/arch/arm/mach-exynos/mach-origen.c +++ b/trunk/arch/arm/mach-exynos/mach-origen.c @@ -815,7 +815,7 @@ MACHINE_START(ORIGEN, "ORIGEN") .map_io = origen_map_io, .init_machine = origen_machine_init, .init_late = exynos_init_late, - .init_time = exynos4_timer_init, + .init_time = mct_init, .reserve = &origen_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c index fe6149624b84..34a6356364eb 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c +++ b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c @@ -376,7 +376,7 @@ MACHINE_START(SMDK4212, "SMDK4212") .init_irq = exynos4_init_irq, .map_io = smdk4x12_map_io, .init_machine = smdk4x12_machine_init, - .init_time = exynos4_timer_init, + .init_time = mct_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END @@ -390,7 +390,7 @@ MACHINE_START(SMDK4412, "SMDK4412") .map_io = smdk4x12_map_io, .init_machine = smdk4x12_machine_init, .init_late = exynos_init_late, - .init_time = exynos4_timer_init, + .init_time = mct_init, .restart = exynos4_restart, .reserve = &smdk4x12_reserve, MACHINE_END diff --git a/trunk/arch/arm/mach-exynos/mach-smdkv310.c b/trunk/arch/arm/mach-exynos/mach-smdkv310.c index d71672922b19..893b14e8c62a 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdkv310.c +++ b/trunk/arch/arm/mach-exynos/mach-smdkv310.c @@ -423,7 +423,7 @@ MACHINE_START(SMDKV310, "SMDKV310") .init_irq = exynos4_init_irq, .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, - .init_time = exynos4_timer_init, + .init_time = mct_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END @@ -436,7 +436,7 @@ MACHINE_START(SMDKC210, "SMDKC210") .map_io = smdkv310_map_io, .init_machine = smdkv310_machine_init, .init_late = exynos_init_late, - .init_time = exynos4_timer_init, + .init_time = mct_init, .reserve = &smdkv310_reserve, .restart = exynos4_restart, MACHINE_END diff --git a/trunk/arch/arm/mach-highbank/highbank.c b/trunk/arch/arm/mach-highbank/highbank.c index 76c1170b3528..e7df2dd43a40 100644 --- a/trunk/arch/arm/mach-highbank/highbank.c +++ b/trunk/arch/arm/mach-highbank/highbank.c @@ -15,6 +15,7 @@ */ #include #include +#include #include #include #include @@ -28,12 +29,9 @@ #include #include -#include #include #include #include -#include -#include #include #include #include @@ -90,36 +88,16 @@ static void __init highbank_init_irq(void) #endif } -static struct clk_lookup lookup = { - .dev_id = "sp804", - .con_id = NULL, -}; - static void __init highbank_timer_init(void) { - int irq; struct device_node *np; - void __iomem *timer_base; /* Map system registers */ np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs"); sregs_base = of_iomap(np, 0); WARN_ON(!sregs_base); - np = of_find_compatible_node(NULL, NULL, "arm,sp804"); - timer_base = of_iomap(np, 0); - WARN_ON(!timer_base); - irq = irq_of_parse_and_map(np, 0); - of_clk_init(NULL); - lookup.clk = of_clk_get(np, 0); - clkdev_add(&lookup); - - sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); - sp804_clockevents_init(timer_base, irq, "timer0"); - - arch_timer_of_register(); - arch_timer_sched_clock_init(); clocksource_of_init(); } diff --git a/trunk/arch/arm/mach-imx/clk-busy.c b/trunk/arch/arm/mach-imx/clk-busy.c index 1ab91b5209e6..85b728cc27ab 100644 --- a/trunk/arch/arm/mach-imx/clk-busy.c +++ b/trunk/arch/arm/mach-imx/clk-busy.c @@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, busy->mux.reg = reg; busy->mux.shift = shift; - busy->mux.width = width; + busy->mux.mask = BIT(width) - 1; busy->mux.lock = &imx_ccm_lock; busy->mux_ops = &clk_mux_ops; diff --git a/trunk/arch/arm/mach-imx/common.h b/trunk/arch/arm/mach-imx/common.h index 5a800bfcec5b..5bf4a97ab241 100644 --- a/trunk/arch/arm/mach-imx/common.h +++ b/trunk/arch/arm/mach-imx/common.h @@ -110,6 +110,8 @@ void tzic_handle_irq(struct pt_regs *); extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); +extern u32 imx_get_cpu_arg(int cpu); +extern void imx_set_cpu_arg(int cpu, u32 arg); extern void v7_cpu_resume(void); extern u32 *pl310_get_save_ptr(void); #ifdef CONFIG_SMP diff --git a/trunk/arch/arm/mach-imx/hotplug.c b/trunk/arch/arm/mach-imx/hotplug.c index 7bc5fe15dda2..361a253e2b63 100644 --- a/trunk/arch/arm/mach-imx/hotplug.c +++ b/trunk/arch/arm/mach-imx/hotplug.c @@ -46,11 +46,23 @@ static inline void cpu_enter_lowpower(void) void imx_cpu_die(unsigned int cpu) { cpu_enter_lowpower(); + /* + * We use the cpu jumping argument register to sync with + * imx_cpu_kill() which is running on cpu0 and waiting for + * the register being cleared to kill the cpu. + */ + imx_set_cpu_arg(cpu, ~0); cpu_do_idle(); } int imx_cpu_kill(unsigned int cpu) { + unsigned long timeout = jiffies + msecs_to_jiffies(50); + + while (imx_get_cpu_arg(cpu) == 0) + if (time_after(jiffies, timeout)) + return 0; imx_enable_cpu(cpu, false); + imx_set_cpu_arg(cpu, 0); return 1; } diff --git a/trunk/arch/arm/mach-imx/src.c b/trunk/arch/arm/mach-imx/src.c index e15f1555c59b..09a742f8c7ab 100644 --- a/trunk/arch/arm/mach-imx/src.c +++ b/trunk/arch/arm/mach-imx/src.c @@ -43,6 +43,18 @@ void imx_set_cpu_jump(int cpu, void *jump_addr) src_base + SRC_GPR1 + cpu * 8); } +u32 imx_get_cpu_arg(int cpu) +{ + cpu = cpu_logical_map(cpu); + return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); +} + +void imx_set_cpu_arg(int cpu, u32 arg) +{ + cpu = cpu_logical_map(cpu); + writel_relaxed(arg, src_base + SRC_GPR1 + cpu * 8 + 4); +} + void imx_src_prepare_restart(void) { u32 val; diff --git a/trunk/arch/arm/mach-integrator/integrator_cp.c b/trunk/arch/arm/mach-integrator/integrator_cp.c index da1091be0887..8c60fcb08a98 100644 --- a/trunk/arch/arm/mach-integrator/integrator_cp.c +++ b/trunk/arch/arm/mach-integrator/integrator_cp.c @@ -250,39 +250,6 @@ static void __init intcp_init_early(void) } #ifdef CONFIG_OF - -static void __init cp_of_timer_init(void) -{ - struct device_node *node; - const char *path; - void __iomem *base; - int err; - int irq; - - err = of_property_read_string(of_aliases, - "arm,timer-primary", &path); - if (WARN_ON(err)) - return; - node = of_find_node_by_path(path); - base = of_iomap(node, 0); - if (WARN_ON(!base)) - return; - writel(0, base + TIMER_CTRL); - sp804_clocksource_init(base, node->name); - - err = of_property_read_string(of_aliases, - "arm,timer-secondary", &path); - if (WARN_ON(err)) - return; - node = of_find_node_by_path(path); - base = of_iomap(node, 0); - if (WARN_ON(!base)) - return; - irq = irq_of_parse_and_map(node, 0); - writel(0, base + TIMER_CTRL); - sp804_clockevents_init(base, irq, node->name); -} - static const struct of_device_id fpga_irq_of_match[] __initconst = { { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, { /* Sentinel */ } @@ -383,7 +350,6 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") .init_early = intcp_init_early, .init_irq = intcp_init_irq_of, .handle_irq = fpga_handle_irq, - .init_time = cp_of_timer_init, .init_machine = intcp_init_of, .restart = integrator_restart, .dt_compat = intcp_dt_board_compat, diff --git a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c b/trunk/arch/arm/mach-kirkwood/guruplug-setup.c index 1c6e736cbbf8..08dd739aa709 100644 --- a/trunk/arch/arm/mach-kirkwood/guruplug-setup.c +++ b/trunk/arch/arm/mach-kirkwood/guruplug-setup.c @@ -53,6 +53,8 @@ static struct mv_sata_platform_data guruplug_sata_data = { static struct mvsdio_platform_data guruplug_mvsdio_data = { /* unfortunately the CD signal has not been connected */ + .gpio_card_detect = -1, + .gpio_write_protect = -1, }; static struct gpio_led guruplug_led_pins[] = { diff --git a/trunk/arch/arm/mach-kirkwood/openrd-setup.c b/trunk/arch/arm/mach-kirkwood/openrd-setup.c index 8ddd69fdc937..6a6eb548307d 100644 --- a/trunk/arch/arm/mach-kirkwood/openrd-setup.c +++ b/trunk/arch/arm/mach-kirkwood/openrd-setup.c @@ -55,6 +55,7 @@ static struct mv_sata_platform_data openrd_sata_data = { static struct mvsdio_platform_data openrd_mvsdio_data = { .gpio_card_detect = 29, /* MPP29 used as SD card detect */ + .gpio_write_protect = -1, }; static unsigned int openrd_mpp_config[] __initdata = { diff --git a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c index c7d93b48926b..d24223166e06 100644 --- a/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/trunk/arch/arm/mach-kirkwood/rd88f6281-setup.c @@ -69,6 +69,7 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { static struct mvsdio_platform_data rd88f6281_mvsdio_data = { .gpio_card_detect = 28, + .gpio_write_protect = -1, }; static unsigned int rd88f6281_mpp_config[] __initdata = { diff --git a/trunk/arch/arm/mach-msm/timer.c b/trunk/arch/arm/mach-msm/timer.c index 2969027f02fa..f9fd77e8f1f5 100644 --- a/trunk/arch/arm/mach-msm/timer.c +++ b/trunk/arch/arm/mach-msm/timer.c @@ -62,7 +62,10 @@ static int msm_timer_set_next_event(unsigned long cycles, { u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); - writel_relaxed(0, event_base + TIMER_CLEAR); + ctrl &= ~TIMER_ENABLE_EN; + writel_relaxed(ctrl, event_base + TIMER_ENABLE); + + writel_relaxed(ctrl, event_base + TIMER_CLEAR); writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); return 0; diff --git a/trunk/arch/arm/mach-mvebu/Makefile b/trunk/arch/arm/mach-mvebu/Makefile index da93bcbc74c1..c3be068f1c96 100644 --- a/trunk/arch/arm/mach-mvebu/Makefile +++ b/trunk/arch/arm/mach-mvebu/Makefile @@ -5,6 +5,6 @@ AFLAGS_coherency_ll.o := -Wa,-march=armv7-a obj-y += system-controller.o obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o -obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o irq-armada-370-xp.o +obj-$(CONFIG_ARCH_MVEBU) += addr-map.o coherency.o coherency_ll.o pmsu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o diff --git a/trunk/arch/arm/mach-mvebu/armada-370-xp.c b/trunk/arch/arm/mach-mvebu/armada-370-xp.c index a5ea616d6d12..433e8c5343b2 100644 --- a/trunk/arch/arm/mach-mvebu/armada-370-xp.c +++ b/trunk/arch/arm/mach-mvebu/armada-370-xp.c @@ -19,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -54,6 +56,10 @@ void __init armada_370_xp_init_early(void) * to make sure such the allocations won't fail. */ init_dma_coherent_pool_size(SZ_1M); + +#ifdef CONFIG_CACHE_L2X0 + l2x0_of_init(0, ~0UL); +#endif } static void __init armada_370_xp_dt_init(void) @@ -72,8 +78,7 @@ DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, .init_early = armada_370_xp_init_early, - .init_irq = armada_370_xp_init_irq, - .handle_irq = armada_370_xp_handle_irq, + .init_irq = irqchip_init, .init_time = armada_370_xp_timer_and_clk_init, .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, diff --git a/trunk/arch/arm/mach-omap1/clock_data.c b/trunk/arch/arm/mach-omap1/clock_data.c index cb7c6ae2e3fc..6c4f766365a2 100644 --- a/trunk/arch/arm/mach-omap1/clock_data.c +++ b/trunk/arch/arm/mach-omap1/clock_data.c @@ -538,15 +538,6 @@ static struct clk usb_hhc_ck16xx = { }; static struct clk usb_dc_ck = { - .name = "usb_dc_ck", - .ops = &clkops_generic, - /* Direct from ULPD, no parent */ - .rate = 48000000, - .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), - .enable_bit = USB_REQ_EN_SHIFT, -}; - -static struct clk usb_dc_ck7xx = { .name = "usb_dc_ck", .ops = &clkops_generic, /* Direct from ULPD, no parent */ @@ -727,8 +718,7 @@ static struct omap_clk omap_clks[] = { CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), - CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), + CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX), CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), CLK(NULL, "mclk", &mclk_16xx, CK_16XX), CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), diff --git a/trunk/arch/arm/mach-omap1/include/mach/usb.h b/trunk/arch/arm/mach-omap1/include/mach/usb.h index 753cd5ce6949..45e5ac707cbb 100644 --- a/trunk/arch/arm/mach-omap1/include/mach/usb.h +++ b/trunk/arch/arm/mach-omap1/include/mach/usb.h @@ -2,7 +2,7 @@ * FIXME correct answer depends on hmc_mode, * as does (on omap1) any nonzero value for config->otg port number */ -#ifdef CONFIG_USB_GADGET_OMAP +#if IS_ENABLED(CONFIG_USB_OMAP) #define is_usb0_device(config) 1 #else #define is_usb0_device(config) 0 diff --git a/trunk/arch/arm/mach-omap1/usb.c b/trunk/arch/arm/mach-omap1/usb.c index 1a1db5971cd9..4118db50d5e8 100644 --- a/trunk/arch/arm/mach-omap1/usb.c +++ b/trunk/arch/arm/mach-omap1/usb.c @@ -123,7 +123,7 @@ omap_otg_init(struct omap_usb_config *config) syscon = omap_readl(OTG_SYSCON_1); syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; -#ifdef CONFIG_USB_GADGET_OMAP +#if IS_ENABLED(CONFIG_USB_OMAP) if (config->otg || config->register_dev) { struct platform_device *udc_device = config->udc_device; int status; @@ -169,7 +169,7 @@ omap_otg_init(struct omap_usb_config *config) void omap_otg_init(struct omap_usb_config *config) {} #endif -#ifdef CONFIG_USB_GADGET_OMAP +#if IS_ENABLED(CONFIG_USB_OMAP) static struct resource udc_resources[] = { /* order is significant! */ @@ -600,7 +600,7 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config) while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) cpu_relax(); -#ifdef CONFIG_USB_GADGET_OMAP +#if IS_ENABLED(CONFIG_USB_OMAP) if (config->register_dev) { int status; diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index b068b7fe99ef..62bb352c2d37 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -229,7 +229,6 @@ obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o -obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o obj-$(CONFIG_MACH_OVERO) += board-overo.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o @@ -255,8 +254,6 @@ obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o -obj-$(CONFIG_MACH_PCM049) += board-omap4pcm049.o - obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index cb0596b631cf..244d8a5aa54b 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -38,7 +38,7 @@ #include "gpmc-smc91x.h" #include