From 7dcc06a1b4c40b9d5fa7e1010ad002a6058ac59d Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Mon, 9 Aug 2010 14:50:53 +0100
Subject: [PATCH] --- yaml --- r: 217893 b: refs/heads/master c:
 19c55da11660fea1a0f1ddbb33ecf38d4f728799 h: refs/heads/master i:   217891:
 ddeb89f9685916df05e96894e11100b7c05a5ce4 v: v3

---
 [refs]                                 | 2 +-
 trunk/drivers/gpu/drm/i915/intel_crt.c | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index a23f6134e2f5..1031ff1c1c96 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 82d7c9e7da9fa11b8ed968c94a19c7732e11c1ad
+refs/heads/master: 19c55da11660fea1a0f1ddbb33ecf38d4f728799
diff --git a/trunk/drivers/gpu/drm/i915/intel_crt.c b/trunk/drivers/gpu/drm/i915/intel_crt.c
index c2982e48b61f..626279791b89 100644
--- a/trunk/drivers/gpu/drm/i915/intel_crt.c
+++ b/trunk/drivers/gpu/drm/i915/intel_crt.c
@@ -327,6 +327,7 @@ intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder
 	if (IS_I9XX(dev)) {
 		uint32_t pipeconf = I915_READ(pipeconf_reg);
 		I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
+		POSTING_READ(pipeconf_reg);
 		/* Wait for next Vblank to substitue
 		 * border color for Color info */
 		intel_wait_for_vblank(dev, pipe);