From 7df6af05707774ca2679b7f17fed54c0fa3bfdda Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 23 Oct 2009 19:03:48 +0300 Subject: [PATCH] --- yaml --- r: 179758 b: refs/heads/master c: 2bbe3af3f1e1c1d0992c984e05d061ef5469edb4 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap1/clock.c | 6 +- trunk/arch/arm/mach-omap2/clock34xx_data.c | 4 ++ trunk/arch/arm/mach-omap2/clock44xx_data.c | 62 +++++++++---------- trunk/arch/arm/mach-omap2/irq.c | 6 ++ trunk/arch/arm/mach-omap2/omap_hwmod.c | 3 +- trunk/arch/arm/mach-omap2/pm34xx.c | 2 + trunk/arch/arm/mach-omap2/prm.h | 2 - trunk/arch/arm/mach-omap2/prm44xx.h | 32 +++++----- trunk/arch/arm/plat-omap/include/plat/irqs.h | 1 + .../arm/plat-omap/include/plat/omap_hwmod.h | 1 - 11 files changed, 65 insertions(+), 56 deletions(-) diff --git a/[refs] b/[refs] index ae964cddfaae..61d30d2da575 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fa8d1d6c2a72659f773f919c4356b68884c875d0 +refs/heads/master: 2bbe3af3f1e1c1d0992c984e05d061ef5469edb4 diff --git a/trunk/arch/arm/mach-omap1/clock.c b/trunk/arch/arm/mach-omap1/clock.c index 04f1d29cba2c..2ba9ab953731 100644 --- a/trunk/arch/arm/mach-omap1/clock.c +++ b/trunk/arch/arm/mach-omap1/clock.c @@ -214,8 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate) struct mpu_rate * ptr; unsigned long dpll1_rate, ref_rate; - dpll1_rate = ck_dpll1_p->rate; - ref_rate = ck_ref_p->rate; + dpll1_rate = clk_get_rate(ck_dpll1_p); + ref_rate = clk_get_rate(ck_ref_p); for (ptr = omap1_rate_table; ptr->rate; ptr++) { if (ptr->xtal != ref_rate) @@ -306,7 +306,7 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) long highest_rate; unsigned long ref_rate; - ref_rate = ck_ref_p->rate; + ref_rate = clk_get_rate(ck_ref_p); highest_rate = -EINVAL; diff --git a/trunk/arch/arm/mach-omap2/clock34xx_data.c b/trunk/arch/arm/mach-omap2/clock34xx_data.c index 74930e3158e3..c6031d74d6f6 100644 --- a/trunk/arch/arm/mach-omap2/clock34xx_data.c +++ b/trunk/arch/arm/mach-omap2/clock34xx_data.c @@ -671,6 +671,7 @@ static struct clk dpll4_m3x2_ck = { .name = "dpll4_m3x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m3_ck, + .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_TV_SHIFT, .flags = INVERT_ENABLE, @@ -810,6 +811,7 @@ static struct clk dpll4_m6x2_ck = { .name = "dpll4_m6x2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll4_m6_ck, + .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, .flags = INVERT_ENABLE, @@ -1045,6 +1047,7 @@ static struct clk iva2_ck = { .name = "iva2_ck", .ops = &clkops_omap2_dflt_wait, .parent = &dpll2_m2_ck, + .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, .clkdm_name = "iva2_clkdm", @@ -1118,6 +1121,7 @@ static struct clk gfx_l3_ck = { .name = "gfx_l3_ck", .ops = &clkops_omap2_dflt_wait, .parent = &l3_ick, + .init = &omap2_init_clksel_parent, .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), .enable_bit = OMAP_EN_GFX_SHIFT, .recalc = &followparent_recalc, diff --git a/trunk/arch/arm/mach-omap2/clock44xx_data.c b/trunk/arch/arm/mach-omap2/clock44xx_data.c index 9d882bcb56e3..2210e227d78a 100644 --- a/trunk/arch/arm/mach-omap2/clock44xx_data.c +++ b/trunk/arch/arm/mach-omap2/clock44xx_data.c @@ -346,37 +346,37 @@ static struct clk aess_fclk = { }; static const struct clksel_rate div31_1to31_rates[] = { - { .div = 1, .val = 1, .flags = RATE_IN_4430 }, - { .div = 2, .val = 2, .flags = RATE_IN_4430 }, - { .div = 3, .val = 3, .flags = RATE_IN_4430 }, - { .div = 4, .val = 4, .flags = RATE_IN_4430 }, - { .div = 5, .val = 5, .flags = RATE_IN_4430 }, - { .div = 6, .val = 6, .flags = RATE_IN_4430 }, - { .div = 7, .val = 7, .flags = RATE_IN_4430 }, - { .div = 8, .val = 8, .flags = RATE_IN_4430 }, - { .div = 9, .val = 9, .flags = RATE_IN_4430 }, - { .div = 10, .val = 10, .flags = RATE_IN_4430 }, - { .div = 11, .val = 11, .flags = RATE_IN_4430 }, - { .div = 12, .val = 12, .flags = RATE_IN_4430 }, - { .div = 13, .val = 13, .flags = RATE_IN_4430 }, - { .div = 14, .val = 14, .flags = RATE_IN_4430 }, - { .div = 15, .val = 15, .flags = RATE_IN_4430 }, - { .div = 16, .val = 16, .flags = RATE_IN_4430 }, - { .div = 17, .val = 17, .flags = RATE_IN_4430 }, - { .div = 18, .val = 18, .flags = RATE_IN_4430 }, - { .div = 19, .val = 19, .flags = RATE_IN_4430 }, - { .div = 20, .val = 20, .flags = RATE_IN_4430 }, - { .div = 21, .val = 21, .flags = RATE_IN_4430 }, - { .div = 22, .val = 22, .flags = RATE_IN_4430 }, - { .div = 23, .val = 23, .flags = RATE_IN_4430 }, - { .div = 24, .val = 24, .flags = RATE_IN_4430 }, - { .div = 25, .val = 25, .flags = RATE_IN_4430 }, - { .div = 26, .val = 26, .flags = RATE_IN_4430 }, - { .div = 27, .val = 27, .flags = RATE_IN_4430 }, - { .div = 28, .val = 28, .flags = RATE_IN_4430 }, - { .div = 29, .val = 29, .flags = RATE_IN_4430 }, - { .div = 30, .val = 30, .flags = RATE_IN_4430 }, - { .div = 31, .val = 31, .flags = RATE_IN_4430 }, + { .div = 1, .val = 0, .flags = RATE_IN_4430 }, + { .div = 2, .val = 1, .flags = RATE_IN_4430 }, + { .div = 3, .val = 2, .flags = RATE_IN_4430 }, + { .div = 4, .val = 3, .flags = RATE_IN_4430 }, + { .div = 5, .val = 4, .flags = RATE_IN_4430 }, + { .div = 6, .val = 5, .flags = RATE_IN_4430 }, + { .div = 7, .val = 6, .flags = RATE_IN_4430 }, + { .div = 8, .val = 7, .flags = RATE_IN_4430 }, + { .div = 9, .val = 8, .flags = RATE_IN_4430 }, + { .div = 10, .val = 9, .flags = RATE_IN_4430 }, + { .div = 11, .val = 10, .flags = RATE_IN_4430 }, + { .div = 12, .val = 11, .flags = RATE_IN_4430 }, + { .div = 13, .val = 12, .flags = RATE_IN_4430 }, + { .div = 14, .val = 13, .flags = RATE_IN_4430 }, + { .div = 15, .val = 14, .flags = RATE_IN_4430 }, + { .div = 16, .val = 15, .flags = RATE_IN_4430 }, + { .div = 17, .val = 16, .flags = RATE_IN_4430 }, + { .div = 18, .val = 17, .flags = RATE_IN_4430 }, + { .div = 19, .val = 18, .flags = RATE_IN_4430 }, + { .div = 20, .val = 19, .flags = RATE_IN_4430 }, + { .div = 21, .val = 20, .flags = RATE_IN_4430 }, + { .div = 22, .val = 21, .flags = RATE_IN_4430 }, + { .div = 23, .val = 22, .flags = RATE_IN_4430 }, + { .div = 24, .val = 23, .flags = RATE_IN_4430 }, + { .div = 25, .val = 24, .flags = RATE_IN_4430 }, + { .div = 26, .val = 25, .flags = RATE_IN_4430 }, + { .div = 27, .val = 26, .flags = RATE_IN_4430 }, + { .div = 28, .val = 27, .flags = RATE_IN_4430 }, + { .div = 29, .val = 28, .flags = RATE_IN_4430 }, + { .div = 30, .val = 29, .flags = RATE_IN_4430 }, + { .div = 31, .val = 30, .flags = RATE_IN_4430 }, { .div = 0 }, }; diff --git a/trunk/arch/arm/mach-omap2/irq.c b/trunk/arch/arm/mach-omap2/irq.c index e9bc782fa414..54c5f0dcd663 100644 --- a/trunk/arch/arm/mach-omap2/irq.c +++ b/trunk/arch/arm/mach-omap2/irq.c @@ -274,4 +274,10 @@ void omap_intc_restore_context(void) } /* MIRs are saved and restore with other PRCM registers */ } + +void omap3_intc_suspend(void) +{ + /* A pending interrupt would prevent OMAP from entering suspend */ + omap_ack_irq(0); +} #endif /* CONFIG_ARCH_OMAP3 */ diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod.c b/trunk/arch/arm/mach-omap2/omap_hwmod.c index 478ae585ca39..d8c8545875b1 100644 --- a/trunk/arch/arm/mach-omap2/omap_hwmod.c +++ b/trunk/arch/arm/mach-omap2/omap_hwmod.c @@ -94,8 +94,7 @@ static int _update_sysc_cache(struct omap_hwmod *oh) oh->_sysc_cache = omap_hwmod_readl(oh, oh->sysconfig->sysc_offs); - if (!(oh->sysconfig->sysc_flags & SYSC_NO_CACHE)) - oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; + oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; return 0; } diff --git a/trunk/arch/arm/mach-omap2/pm34xx.c b/trunk/arch/arm/mach-omap2/pm34xx.c index c6cc809afb79..b26418d55076 100644 --- a/trunk/arch/arm/mach-omap2/pm34xx.c +++ b/trunk/arch/arm/mach-omap2/pm34xx.c @@ -578,6 +578,8 @@ static int omap3_pm_suspend(void) } omap_uart_prepare_suspend(); + omap3_intc_suspend(); + omap_sram_idle(); restore: diff --git a/trunk/arch/arm/mach-omap2/prm.h b/trunk/arch/arm/mach-omap2/prm.h index 40f006285163..ea050ce188a7 100644 --- a/trunk/arch/arm/mach-omap2/prm.h +++ b/trunk/arch/arm/mach-omap2/prm.h @@ -24,8 +24,6 @@ OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) #define OMAP44XX_PRM_REGADDR(module, reg) \ OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg)) -#define OMAP44XX_CHIRONSS_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP4430_CHIRONSS_BASE + (module) + (reg)) #include "prm44xx.h" diff --git a/trunk/arch/arm/mach-omap2/prm44xx.h b/trunk/arch/arm/mach-omap2/prm44xx.h index adb2558bb121..89be97f0589d 100644 --- a/trunk/arch/arm/mach-omap2/prm44xx.h +++ b/trunk/arch/arm/mach-omap2/prm44xx.h @@ -386,26 +386,26 @@ /* CHIRON_PRCM.CHIRONSS_OCP_SOCKET_PRCM register offsets */ -#define OMAP4430_REVISION_PRCM OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) +#define OMAP4430_REVISION_PRCM OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD, 0x0000) /* CHIRON_PRCM.CHIRONSS_DEVICE_PRM register offsets */ -#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) +#define OMAP4430_CHIRON_PRCM_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD, 0x0000) /* CHIRON_PRCM.CHIRONSS_CPU0 register offsets */ -#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) -#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) -#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) -#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) -#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) -#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) -#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) +#define OMAP4430_PM_PDA_CPU0_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0000) +#define OMAP4430_PM_PDA_CPU0_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0004) +#define OMAP4430_RM_PDA_CPU0_CPU0_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0008) +#define OMAP4430_RM_PDA_CPU0_CPU0_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x000c) +#define OMAP4430_RM_PDA_CPU0_CPU0_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0010) +#define OMAP4430_CM_PDA_CPU0_CPU0_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0014) +#define OMAP4430_CM_PDA_CPU0_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD, 0x0018) /* CHIRON_PRCM.CHIRONSS_CPU1 register offsets */ -#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) -#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) -#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) -#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) -#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) -#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) -#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_CHIRONSS_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) +#define OMAP4430_PM_PDA_CPU1_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0000) +#define OMAP4430_PM_PDA_CPU1_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0004) +#define OMAP4430_RM_PDA_CPU1_CPU1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0008) +#define OMAP4430_RM_PDA_CPU1_CPU1_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x000c) +#define OMAP4430_RM_PDA_CPU1_CPU1_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0010) +#define OMAP4430_CM_PDA_CPU1_CPU1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0014) +#define OMAP4430_CM_PDA_CPU1_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD, 0x0018) #endif diff --git a/trunk/arch/arm/plat-omap/include/plat/irqs.h b/trunk/arch/arm/plat-omap/include/plat/irqs.h index 97d6c50c3dcb..0082036f6a48 100644 --- a/trunk/arch/arm/plat-omap/include/plat/irqs.h +++ b/trunk/arch/arm/plat-omap/include/plat/irqs.h @@ -499,6 +499,7 @@ extern void omap_init_irq(void); extern int omap_irq_pending(void); void omap_intc_save_context(void); void omap_intc_restore_context(void); +void omap3_intc_suspend(void); #endif #include diff --git a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h index 33933256a226..007935a921ea 100644 --- a/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h +++ b/trunk/arch/arm/plat-omap/include/plat/omap_hwmod.h @@ -227,7 +227,6 @@ struct omap_hwmod_ocp_if { #define SYSC_HAS_SIDLEMODE (1 << 5) #define SYSC_HAS_MIDLEMODE (1 << 6) #define SYSS_MISSING (1 << 7) -#define SYSC_NO_CACHE (1 << 8) /* XXX SW flag, belongs elsewhere */ /* omap_hwmod_sysconfig.clockact flags */ #define CLOCKACT_TEST_BOTH 0x0