From 7e8751628aba6a844bf4d45bf6ed12fad22971c5 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 7 Feb 2012 19:42:07 +0100 Subject: [PATCH] --- yaml --- r: 287569 b: refs/heads/master c: b46c0f74657d1fe1c1b0c1452631cc38a9e6987f h: refs/heads/master i: 287567: 8832e8688c7b09b7fd28a8ce4ff5025c6abe0b65 v: v3 --- [refs] | 2 +- trunk/arch/arm/mm/cache-v7.S | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 91158f7af1fa..75741c52a2fd 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b8b9987ffdc2ab9c5e2c1edad556b23ccb38249b +refs/heads/master: b46c0f74657d1fe1c1b0c1452631cc38a9e6987f diff --git a/trunk/arch/arm/mm/cache-v7.S b/trunk/arch/arm/mm/cache-v7.S index 07c4bc8ea0a4..7a24d39661f0 100644 --- a/trunk/arch/arm/mm/cache-v7.S +++ b/trunk/arch/arm/mm/cache-v7.S @@ -54,9 +54,15 @@ loop1: and r1, r1, #7 @ mask of the bits for current cache only cmp r1, #2 @ see what cache we have at this level blt skip @ skip if no cache, or just i-cache +#ifdef CONFIG_PREEMPT + save_and_disable_irqs r9 @ make cssr&csidr read atomic +#endif mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr isb @ isb to sych the new cssr&csidr mrc p15, 1, r1, c0, c0, 0 @ read the new csidr +#ifdef CONFIG_PREEMPT + restore_irqs_notrace r9 +#endif and r2, r1, #7 @ extract the length of the cache lines add r2, r2, #4 @ add 4 (line length offset) ldr r4, =0x3ff