From 7ea93d53dbffdff7a7304650aa6bc3741e4c125d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 23 Sep 2011 15:37:38 +1000 Subject: [PATCH] --- yaml --- r: 275267 b: refs/heads/master c: ee9f7ef99f4422463634c075b22197c22c5cfa71 h: refs/heads/master i: 275265: 72f391f1fddf6e0fe1e9f404aedd1ccf959f724a 275263: 49eafea8e7a38bbb688da1881a2d32c0725d3f3e v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nouveau_bios.c | 22 ++++++++++++-------- 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/[refs] b/[refs] index c4ab13cf34cb..2e29f11a27f7 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 46b348865011bf0d706fe1ec8c9cef08cf86ad40 +refs/heads/master: ee9f7ef99f4422463634c075b22197c22c5cfa71 diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c b/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c index 032a82098136..5fc201b49d30 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -640,10 +640,9 @@ static int nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) { struct drm_nouveau_private *dev_priv = dev->dev_private; - uint32_t reg0 = nv_rd32(dev, reg + 0); - uint32_t reg1 = nv_rd32(dev, reg + 4); struct nouveau_pll_vals pll; struct pll_lims pll_limits; + u32 ctrl, mask, coef; int ret; ret = get_pll_limits(dev, reg, &pll_limits); @@ -654,15 +653,20 @@ nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk) if (!clk) return -ERANGE; - reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16); - reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1; - - if (dev_priv->vbios.execute) { - still_alive(); - nv_wr32(dev, reg + 4, reg1); - nv_wr32(dev, reg + 0, reg0); + coef = pll.N1 << 8 | pll.M1; + ctrl = pll.log2P << 16; + mask = 0x00070000; + if (reg == 0x004008) { + mask |= 0x01f80000; + ctrl |= (pll_limits.log2p_bias << 19); + ctrl |= (pll.log2P << 22); } + if (!dev_priv->vbios.execute) + return 0; + + nv_mask(dev, reg + 0, mask, ctrl); + nv_wr32(dev, reg + 4, coef); return 0; }