From 7edf411f65057d59ccd0efdcd5970e69b60dd8b0 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 21 Oct 2008 14:07:14 +0100 Subject: [PATCH] --- yaml --- r: 123861 b: refs/heads/master c: 8cdf47cb4bb10172732df0506d397aab4149e45e h: refs/heads/master i: 123859: fe44fbd939a9fc786ccdae3dfe71b24574f62342 v: v3 --- [refs] | 2 +- .../arch/arm/plat-s3c64xx/include/plat/irqs.h | 40 +++++++++++++++++-- 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index c684764ac906..fb31ce4f0064 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f945ee13cffbee48066e2ac24dbdd1b29a102b51 +refs/heads/master: 8cdf47cb4bb10172732df0506d397aab4149e45e diff --git a/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h b/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h index 5ab41ad143b7..bc25689c3f83 100644 --- a/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h +++ b/trunk/arch/arm/plat-s3c64xx/include/plat/irqs.h @@ -153,10 +153,44 @@ #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) #define IRQ_EINT(x) S3C_EINT(x) -/* Define NR_IRQs here, machine specific can always re-define. - * Currently the IRQ_EINT27 is the last one we can have. */ +/* Next the external interrupt groups. These are similar to the IRQ_EINT(x) + * that they are sourced from the GPIO pins but with a different scheme for + * priority and source indication. + * + * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO + * interrupts, but for historical reasons they are kept apart from these + * next interrupts. + * + * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the + * machine specific support files. + */ -#define NR_IRQS (S3C_EINT(27) + 1) +#define IRQ_EINT_GROUP1_NR (15) +#define IRQ_EINT_GROUP2_NR (8) +#define IRQ_EINT_GROUP3_NR (5) +#define IRQ_EINT_GROUP4_NR (14) +#define IRQ_EINT_GROUP5_NR (7) +#define IRQ_EINT_GROUP6_NR (10) +#define IRQ_EINT_GROUP7_NR (16) +#define IRQ_EINT_GROUP8_NR (15) +#define IRQ_EINT_GROUP9_NR (9) + +#define IRQ_EINT_GROUP_BASE S3C_EINT(28) +#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) +#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) +#define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) +#define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) +#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) +#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) +#define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) +#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) +#define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) + +#define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x)) + +/* Set the default NR_IRQS */ + +#define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) #endif /* __ASM_PLAT_S3C64XX_IRQS_H */