From 7f591b4ec9acaf5270ac71e6301d104990b05a1f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Wed, 30 Mar 2011 13:01:06 -0700
Subject: [PATCH] --- yaml --- r: 250592 b: refs/heads/master c:
 db244b60e7f7f11825c6f36bcc8e8d8f3ca7cd36 h: refs/heads/master v: v3

---
 [refs]                                     | 2 +-
 trunk/drivers/gpu/drm/i915/intel_display.c | 6 ------
 2 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/[refs] b/[refs]
index b8443cbb8da9..afdc46f4f937 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: c713bb087e714f01082e6b8a85e98552e7bc6c3a
+refs/heads/master: db244b60e7f7f11825c6f36bcc8e8d8f3ca7cd36
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
index 08ff2f0b9322..a0d5a1a039e0 100644
--- a/trunk/drivers/gpu/drm/i915/intel_display.c
+++ b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -4899,12 +4899,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
 
 	intel_wait_for_vblank(dev, pipe);
 
-	if (IS_GEN5(dev)) {
-		/* enable address swizzle for tiling buffer */
-		temp = I915_READ(DISP_ARB_CTL);
-		I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
-	}
-
 	I915_WRITE(DSPCNTR(plane), dspcntr);
 	POSTING_READ(DSPCNTR(plane));