diff --git a/[refs] b/[refs] index 62d2cea5aa98..5ee446f49a8d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1a58ddfc0fcf3d83a92573c71771962f9b218993 +refs/heads/master: a8035217324d52a316c4dd109736f9ebd5124951 diff --git a/trunk/Documentation/ABI/testing/sysfs-bus-pci b/trunk/Documentation/ABI/testing/sysfs-bus-pci index dff1f48d252d..34f51100f029 100644 --- a/trunk/Documentation/ABI/testing/sysfs-bus-pci +++ b/trunk/Documentation/ABI/testing/sysfs-bus-pci @@ -210,15 +210,3 @@ Users: firmware assigned instance number of the PCI device that can help in understanding the firmware intended order of the PCI device. - -What: /sys/bus/pci/devices/.../d3cold_allowed -Date: July 2012 -Contact: Huang Ying -Description: - d3cold_allowed is bit to control whether the corresponding PCI - device can be put into D3Cold state. If it is cleared, the - device will never be put into D3Cold state. If it is set, the - device may be put into D3Cold state if other requirements are - satisfied too. Reading this attribute will show the current - value of d3cold_allowed bit. Writing this attribute will set - the value of d3cold_allowed bit. diff --git a/trunk/Documentation/ABI/testing/sysfs-bus-usb b/trunk/Documentation/ABI/testing/sysfs-bus-usb index b6fbe514a869..5f75f8f7df34 100644 --- a/trunk/Documentation/ABI/testing/sysfs-bus-usb +++ b/trunk/Documentation/ABI/testing/sysfs-bus-usb @@ -220,10 +220,3 @@ Description: If the device doesn't support LTM, the file will read "no". The file will be present for all speeds of USB devices, and will always read "no" for USB 1.1 and USB 2.0 devices. - -What: /sys/bus/usb/devices/.../(hub interface)/portX -Date: August 2012 -Contact: Lan Tianyu -Description: - The /sys/bus/usb/devices/.../(hub interface)/portX - is usb port device's sysfs directory. diff --git a/trunk/Documentation/ABI/testing/sysfs-class-extcon b/trunk/Documentation/ABI/testing/sysfs-class-extcon index 57a726232912..20ab361bd8c6 100644 --- a/trunk/Documentation/ABI/testing/sysfs-class-extcon +++ b/trunk/Documentation/ABI/testing/sysfs-class-extcon @@ -13,7 +13,7 @@ Description: accessory cables have such capability. For example, the 30-pin port of Nuri board (/arch/arm/mach-exynos) may have both HDMI and Charger attached, or analog audio, - video, and USB cables attached simultaneously. + video, and USB cables attached simulteneously. If there are cables mutually exclusive with each other, such binary relations may be expressed with extcon_dev's @@ -35,7 +35,7 @@ Description: The /sys/class/extcon/.../state shows and stores the cable attach/detach information of the corresponding extcon object. If the extcon object has an optional callback "show_state" - defined, the showing function is overridden with the optional + defined, the showing function is overriden with the optional callback. If the default callback for showing function is used, the @@ -46,19 +46,19 @@ Description: TA=1 EAR_JACK=0 # - In this example, the extcon device has USB_OTG and TA + In this example, the extcon device have USB_OTG and TA cables attached and HDMI and EAR_JACK cables detached. In order to update the state of an extcon device, enter a hex - state number starting with 0x: - # echo 0xHEX > state + state number starting with 0x. + echo 0xHEX > state - This updates the whole state of the extcon device. + This updates the whole state of the extcon dev. Inputs of all the methods are required to meet the - mutually_exclusive conditions if they exist. + mutually_exclusive contidions if they exist. It is recommended to use this "global" state interface if - you need to set the value atomically. The later state + you need to enter the value atomically. The later state interface associated with each cable cannot update multiple cable states of an extcon device simultaneously. @@ -73,7 +73,7 @@ What: /sys/class/extcon/.../cable.x/state Date: February 2012 Contact: MyungJoo Ham Description: - The /sys/class/extcon/.../cable.x/state shows and stores the + The /sys/class/extcon/.../cable.x/name shows and stores the state of cable "x" (integer between 0 and 31) of an extcon device. The state value is either 0 (detached) or 1 (attached). @@ -83,8 +83,8 @@ Date: December 2011 Contact: MyungJoo Ham Description: Shows the relations of mutually exclusiveness. For example, - if the mutually_exclusive array of extcon device is - {0x3, 0x5, 0xC, 0x0}, then the output is: + if the mutually_exclusive array of extcon_dev is + {0x3, 0x5, 0xC, 0x0}, the, the output is: # ls mutually_exclusive/ 0x3 0x5 diff --git a/trunk/Documentation/ABI/testing/sysfs-class-regulator b/trunk/Documentation/ABI/testing/sysfs-class-regulator index bc578bc60628..e091fa873792 100644 --- a/trunk/Documentation/ABI/testing/sysfs-class-regulator +++ b/trunk/Documentation/ABI/testing/sysfs-class-regulator @@ -349,24 +349,3 @@ Description: This will be one of the same strings reported by the "state" attribute. - -What: /sys/class/regulator/.../bypass -Date: September 2012 -KernelVersion: 3.7 -Contact: Mark Brown -Description: - Some regulator directories will contain a field called - bypass. This indicates if the device is in bypass mode. - - This will be one of the following strings: - - 'enabled' - 'disabled' - 'unknown' - - 'enabled' means the regulator is in bypass mode. - - 'disabled' means that the regulator is regulating. - - 'unknown' means software cannot determine the state, or - the reported state is invalid. diff --git a/trunk/Documentation/ABI/testing/sysfs-driver-wacom b/trunk/Documentation/ABI/testing/sysfs-driver-wacom index 7fc781048b79..8d55a83d6921 100644 --- a/trunk/Documentation/ABI/testing/sysfs-driver-wacom +++ b/trunk/Documentation/ABI/testing/sysfs-driver-wacom @@ -1,16 +1,3 @@ -WWhat: /sys/class/hidraw/hidraw*/device/oled*_img -Date: June 2012 -Contact: linux-bluetooth@vger.kernel.org -Description: - The /sys/class/hidraw/hidraw*/device/oled*_img files control - OLED mocro displays on Intuos4 Wireless tablet. Accepted image - has to contain 256 bytes (64x32 px 1 bit colour). The format - is the same as PBM image 62x32px without header (64 bits per - horizontal line, 32 lines). An example of setting OLED No. 0: - dd bs=256 count=1 if=img_file of=[path to oled0_img]/oled0_img - The attribute is read only and no local copy of the image is - stored. - What: /sys/class/hidraw/hidraw*/device/speed Date: April 2010 Kernel Version: 2.6.35 diff --git a/trunk/Documentation/ABI/testing/sysfs-platform-ideapad-laptop b/trunk/Documentation/ABI/testing/sysfs-platform-ideapad-laptop index b31e782bd985..814b01354c41 100644 --- a/trunk/Documentation/ABI/testing/sysfs-platform-ideapad-laptop +++ b/trunk/Documentation/ABI/testing/sysfs-platform-ideapad-laptop @@ -5,15 +5,4 @@ Contact: "Ike Panhc " Description: Control the power of camera module. 1 means on, 0 means off. -What: /sys/devices/platform/ideapad/fan_mode -Date: June 2012 -KernelVersion: 3.6 -Contact: "Maxim Mikityanskiy " -Description: - Change fan mode - There are four available modes: - * 0 -> Super Silent Mode - * 1 -> Standard Mode - * 2 -> Dust Cleaning - * 4 -> Efficient Thermal Dissipation Mode diff --git a/trunk/Documentation/ABI/testing/sysfs-tty b/trunk/Documentation/ABI/testing/sysfs-tty index 0c430150d929..b138b663bf54 100644 --- a/trunk/Documentation/ABI/testing/sysfs-tty +++ b/trunk/Documentation/ABI/testing/sysfs-tty @@ -17,12 +17,3 @@ Description: device, like 'tty1'. The file supports poll() to detect virtual console switches. - -What: /sys/class/tty/ttyS0/uartclk -Date: Sep 2012 -Contact: Tomas Hlavacek -Description: - Shows the current uartclk value associated with the - UART port in serial_core, that is bound to TTY like ttyS0. - uartclk = 16 * baud_base - diff --git a/trunk/Documentation/DocBook/filesystems.tmpl b/trunk/Documentation/DocBook/filesystems.tmpl index 25b58efd955d..3fca32c41927 100644 --- a/trunk/Documentation/DocBook/filesystems.tmpl +++ b/trunk/Documentation/DocBook/filesystems.tmpl @@ -224,8 +224,8 @@ all your transactions. -Then at umount time , in your put_super() you can then call journal_destroy() -to clean up your in-core journal object. +Then at umount time , in your put_super() (2.4) or write_super() (2.5) +you can then call journal_destroy() to clean up your in-core journal object. diff --git a/trunk/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml b/trunk/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml index 701138f1209d..720395127904 100644 --- a/trunk/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml +++ b/trunk/Documentation/DocBook/media/v4l/vidioc-g-tuner.xml @@ -125,7 +125,7 @@ the structure refers to a radio tuner the V4L2_TUNER_CAP_NORM flags can't be used. If multiple frequency bands are supported, then capability is the union of all -capability fields of each &v4l2-frequency-band;. +capability> fields of each &v4l2-frequency-band;. diff --git a/trunk/Documentation/RCU/checklist.txt b/trunk/Documentation/RCU/checklist.txt index cdb20d41a44a..fc103d7a0474 100644 --- a/trunk/Documentation/RCU/checklist.txt +++ b/trunk/Documentation/RCU/checklist.txt @@ -310,12 +310,6 @@ over a rather long period of time, but improvements are always welcome! code under the influence of preempt_disable(), you instead need to use synchronize_irq() or synchronize_sched(). - This same limitation also applies to synchronize_rcu_bh() - and synchronize_srcu(), as well as to the asynchronous and - expedited forms of the three primitives, namely call_rcu(), - call_rcu_bh(), call_srcu(), synchronize_rcu_expedited(), - synchronize_rcu_bh_expedited(), and synchronize_srcu_expedited(). - 12. Any lock acquired by an RCU callback must be acquired elsewhere with softirq disabled, e.g., via spin_lock_irqsave(), spin_lock_bh(), etc. Failing to disable irq on a given diff --git a/trunk/Documentation/RCU/stallwarn.txt b/trunk/Documentation/RCU/stallwarn.txt index 1927151b386b..523364e4e1f1 100644 --- a/trunk/Documentation/RCU/stallwarn.txt +++ b/trunk/Documentation/RCU/stallwarn.txt @@ -99,7 +99,7 @@ In kernels with CONFIG_RCU_FAST_NO_HZ, even more information is printed: INFO: rcu_preempt detected stall on CPU - 0: (64628 ticks this GP) idle=dd5/3fffffffffffffff/0 drain=0 . timer not pending + 0: (64628 ticks this GP) idle=dd5/3fffffffffffffff/0 drain=0 . timer=-1 (t=65000 jiffies) The "(64628 ticks this GP)" indicates that this CPU has taken more @@ -116,13 +116,13 @@ number between the two "/"s is the value of the nesting, which will be a small positive number if in the idle loop and a very large positive number (as shown above) otherwise. -For CONFIG_RCU_FAST_NO_HZ kernels, the "drain=0" indicates that the CPU is -not in the process of trying to force itself into dyntick-idle state, the -"." indicates that the CPU has not given up forcing RCU into dyntick-idle -mode (it would be "H" otherwise), and the "timer not pending" indicates -that the CPU has not recently forced RCU into dyntick-idle mode (it -would otherwise indicate the number of microseconds remaining in this -forced state). +For CONFIG_RCU_FAST_NO_HZ kernels, the "drain=0" indicates that the +CPU is not in the process of trying to force itself into dyntick-idle +state, the "." indicates that the CPU has not given up forcing RCU +into dyntick-idle mode (it would be "H" otherwise), and the "timer=-1" +indicates that the CPU has not recented forced RCU into dyntick-idle +mode (it would otherwise indicate the number of microseconds remaining +in this forced state). Multiple Warnings From One Stall diff --git a/trunk/Documentation/RCU/trace.txt b/trunk/Documentation/RCU/trace.txt index 672d19083252..f6f15ce39903 100644 --- a/trunk/Documentation/RCU/trace.txt +++ b/trunk/Documentation/RCU/trace.txt @@ -333,23 +333,23 @@ o Each element of the form "1/1 0:127 ^0" represents one struct The output of "cat rcu/rcu_pending" looks as follows: rcu_sched: - 0 np=255892 qsp=53936 rpq=85 cbr=0 cng=14417 gpc=10033 gps=24320 nn=146741 - 1 np=261224 qsp=54638 rpq=33 cbr=0 cng=25723 gpc=16310 gps=2849 nn=155792 - 2 np=237496 qsp=49664 rpq=23 cbr=0 cng=2762 gpc=45478 gps=1762 nn=136629 - 3 np=236249 qsp=48766 rpq=98 cbr=0 cng=286 gpc=48049 gps=1218 nn=137723 - 4 np=221310 qsp=46850 rpq=7 cbr=0 cng=26 gpc=43161 gps=4634 nn=123110 - 5 np=237332 qsp=48449 rpq=9 cbr=0 cng=54 gpc=47920 gps=3252 nn=137456 - 6 np=219995 qsp=46718 rpq=12 cbr=0 cng=50 gpc=42098 gps=6093 nn=120834 - 7 np=249893 qsp=49390 rpq=42 cbr=0 cng=72 gpc=38400 gps=17102 nn=144888 + 0 np=255892 qsp=53936 rpq=85 cbr=0 cng=14417 gpc=10033 gps=24320 nf=6445 nn=146741 + 1 np=261224 qsp=54638 rpq=33 cbr=0 cng=25723 gpc=16310 gps=2849 nf=5912 nn=155792 + 2 np=237496 qsp=49664 rpq=23 cbr=0 cng=2762 gpc=45478 gps=1762 nf=1201 nn=136629 + 3 np=236249 qsp=48766 rpq=98 cbr=0 cng=286 gpc=48049 gps=1218 nf=207 nn=137723 + 4 np=221310 qsp=46850 rpq=7 cbr=0 cng=26 gpc=43161 gps=4634 nf=3529 nn=123110 + 5 np=237332 qsp=48449 rpq=9 cbr=0 cng=54 gpc=47920 gps=3252 nf=201 nn=137456 + 6 np=219995 qsp=46718 rpq=12 cbr=0 cng=50 gpc=42098 gps=6093 nf=4202 nn=120834 + 7 np=249893 qsp=49390 rpq=42 cbr=0 cng=72 gpc=38400 gps=17102 nf=41 nn=144888 rcu_bh: - 0 np=146741 qsp=1419 rpq=6 cbr=0 cng=6 gpc=0 gps=0 nn=145314 - 1 np=155792 qsp=12597 rpq=3 cbr=0 cng=0 gpc=4 gps=8 nn=143180 - 2 np=136629 qsp=18680 rpq=1 cbr=0 cng=0 gpc=7 gps=6 nn=117936 - 3 np=137723 qsp=2843 rpq=0 cbr=0 cng=0 gpc=10 gps=7 nn=134863 - 4 np=123110 qsp=12433 rpq=0 cbr=0 cng=0 gpc=4 gps=2 nn=110671 - 5 np=137456 qsp=4210 rpq=1 cbr=0 cng=0 gpc=6 gps=5 nn=133235 - 6 np=120834 qsp=9902 rpq=2 cbr=0 cng=0 gpc=6 gps=3 nn=110921 - 7 np=144888 qsp=26336 rpq=0 cbr=0 cng=0 gpc=8 gps=2 nn=118542 + 0 np=146741 qsp=1419 rpq=6 cbr=0 cng=6 gpc=0 gps=0 nf=2 nn=145314 + 1 np=155792 qsp=12597 rpq=3 cbr=0 cng=0 gpc=4 gps=8 nf=3 nn=143180 + 2 np=136629 qsp=18680 rpq=1 cbr=0 cng=0 gpc=7 gps=6 nf=0 nn=117936 + 3 np=137723 qsp=2843 rpq=0 cbr=0 cng=0 gpc=10 gps=7 nf=0 nn=134863 + 4 np=123110 qsp=12433 rpq=0 cbr=0 cng=0 gpc=4 gps=2 nf=0 nn=110671 + 5 np=137456 qsp=4210 rpq=1 cbr=0 cng=0 gpc=6 gps=5 nf=0 nn=133235 + 6 np=120834 qsp=9902 rpq=2 cbr=0 cng=0 gpc=6 gps=3 nf=2 nn=110921 + 7 np=144888 qsp=26336 rpq=0 cbr=0 cng=0 gpc=8 gps=2 nf=0 nn=118542 As always, this is once again split into "rcu_sched" and "rcu_bh" portions, with CONFIG_TREE_PREEMPT_RCU kernels having an additional @@ -377,6 +377,17 @@ o "gpc" is the number of times that an old grace period had o "gps" is the number of times that a new grace period had started, but this CPU was not yet aware of it. +o "nf" is the number of times that this CPU suspected that the + current grace period had run for too long, and thus needed to + be forced. + + Please note that "forcing" consists of sending resched IPIs + to holdout CPUs. If that CPU really still is in an old RCU + read-side critical section, then we really do have to wait for it. + The assumption behing "forcing" is that the CPU is not still in + an old RCU read-side critical section, but has not yet responded + for some other reason. + o "nn" is the number of times that this CPU needed nothing. Alert readers will note that the rcu "nn" number for a given CPU very closely matches the rcu_bh "np" number for that same CPU. This diff --git a/trunk/Documentation/RCU/whatisRCU.txt b/trunk/Documentation/RCU/whatisRCU.txt index bf0f6de2aa00..69ee188515e7 100644 --- a/trunk/Documentation/RCU/whatisRCU.txt +++ b/trunk/Documentation/RCU/whatisRCU.txt @@ -873,7 +873,7 @@ d. Do you need to treat NMI handlers, hardirq handlers, and code segments with preemption disabled (whether via preempt_disable(), local_irq_save(), local_bh_disable(), or some other mechanism) as if they were explicit RCU readers? - If so, RCU-sched is the only choice that will work for you. + If so, you need RCU-sched. e. Do you need RCU grace periods to complete even in the face of softirq monopolization of one or more of the CPUs? For @@ -884,12 +884,7 @@ f. Is your workload too update-intensive for normal use of RCU, but inappropriate for other synchronization mechanisms? If so, consider SLAB_DESTROY_BY_RCU. But please be careful! -g. Do you need read-side critical sections that are respected - even though they are in the middle of the idle loop, during - user-mode execution, or on an offlined CPU? If so, SRCU is the - only choice that will work for you. - -h. Otherwise, use RCU. +g. Otherwise, use RCU. Of course, this all assumes that you have determined that RCU is in fact the right tool for your job. diff --git a/trunk/Documentation/accounting/getdelays.c b/trunk/Documentation/accounting/getdelays.c index 6f706aca2049..f6318f6d7baf 100644 --- a/trunk/Documentation/accounting/getdelays.c +++ b/trunk/Documentation/accounting/getdelays.c @@ -98,9 +98,10 @@ static int create_nl_socket(int protocol) if (rcvbufsz) if (setsockopt(fd, SOL_SOCKET, SO_RCVBUF, &rcvbufsz, sizeof(rcvbufsz)) < 0) { - fprintf(stderr, "Unable to set socket rcv buf size to %d\n", + fprintf(stderr, "Unable to set socket rcv buf size " + "to %d\n", rcvbufsz); - goto error; + return -1; } memset(&local, 0, sizeof(local)); diff --git a/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt b/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt index 8b46c79679c4..816d6071669e 100644 --- a/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt +++ b/trunk/Documentation/arm/Samsung-S3C24XX/GPIO.txt @@ -1,4 +1,4 @@ - S3C24XX GPIO Control + S3C2410 GPIO Control ==================== Introduction @@ -12,7 +12,7 @@ Introduction of the s3c2410 GPIO system, please read the Samsung provided data-sheet/users manual to find out the complete list. - See Documentation/arm/Samsung/GPIO.txt for the core implementation. + See Documentation/arm/Samsung/GPIO.txt for the core implemetation. GPIOLIB @@ -41,8 +41,8 @@ GPIOLIB GPIOLIB conversion ------------------ -If you need to convert your board or driver to use gpiolib from the phased -out s3c2410 API, then here are some notes on the process. +If you need to convert your board or driver to use gpiolib from the exiting +s3c2410 api, then here are some notes on the process. 1) If your board is exclusively using an GPIO, say to control peripheral power, then it will require to claim the gpio with gpio_request() before @@ -55,7 +55,7 @@ out s3c2410 API, then here are some notes on the process. as they have the same arguments, and can either take the pin specific values, or the more generic special-function-number arguments. -3) s3c2410_gpio_pullup() changes have the problem that whilst the +3) s3c2410_gpio_pullup() changs have the problem that whilst the s3c2410_gpio_pullup(x, 1) can be easily translated to the s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0) are not so easy. @@ -74,7 +74,7 @@ out s3c2410 API, then here are some notes on the process. when using gpio_get_value() on an output pin (s3c2410_gpio_getpin would return the value the pin is supposed to be outputting). -6) s3c2410_gpio_getirq() should be directly replaceable with the +6) s3c2410_gpio_getirq() should be directly replacable with the gpio_to_irq() call. The s3c2410_gpio and gpio_ calls have always operated on the same gpio @@ -105,7 +105,7 @@ PIN Numbers ----------- Each pin has an unique number associated with it in regs-gpio.h, - e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell + eg S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell the GPIO functions which pin is to be used. With the conversion to gpiolib, there is no longer a direct conversion @@ -120,27 +120,31 @@ Configuring a pin The following function allows the configuration of a given pin to be changed. - void s3c_gpio_cfgpin(unsigned int pin, unsigned int function); + void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function); - e.g.: + Eg: - s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1)); - s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2)); + s3c2410_gpio_cfgpin(S3C2410_GPA(0), S3C2410_GPA0_ADDR0); + s3c2410_gpio_cfgpin(S3C2410_GPE(8), S3C2410_GPE8_SDDAT1); which would turn GPA(0) into the lowest Address line A0, and set GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line. + The s3c_gpio_cfgpin() call is a functional replacement for this call. + Reading the current configuration --------------------------------- - The current configuration of a pin can be read by using standard - gpiolib function: + The current configuration of a pin can be read by using: - s3c_gpio_getcfg(unsigned int pin); + s3c2410_gpio_getcfg(unsigned int pin); The return value will be from the same set of values which can be - passed to s3c_gpio_cfgpin(). + passed to s3c2410_gpio_cfgpin(). + + The s3c_gpio_getcfg() call should be a functional replacement for + this call. Configuring a pull-up resistor @@ -150,33 +154,61 @@ Configuring a pull-up resistor pull-up resistors enabled. This can be configured by the following function: - void s3c_gpio_setpull(unsigned int pin, unsigned int to); + void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); + + Where the to value is zero to set the pull-up off, and 1 to enable + the specified pull-up. Any other values are currently undefined. + + The s3c_gpio_setpull() offers similar functionality, but with the + ability to encode whether the pull is up or down. Currently there + is no 'just on' state, so up or down must be selected. + + +Getting the state of a PIN +-------------------------- + + The state of a pin can be read by using the function: + + unsigned int s3c2410_gpio_getpin(unsigned int pin); - Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off, - and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other - values are currently undefined. + This will return either zero or non-zero. Do not count on this + function returning 1 if the pin is set. + This call is now implemented by the relevant gpiolib calls, convert + your board or driver to use gpiolib. + + +Setting the state of a PIN +-------------------------- + + The value an pin is outputing can be modified by using the following: -Getting and setting the state of a PIN --------------------------------------- + void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); - These calls are now implemented by the relevant gpiolib calls, convert + Which sets the given pin to the value. Use 0 to write 0, and 1 to + set the output to 1. + + This call is now implemented by the relevant gpiolib calls, convert your board or driver to use gpiolib. Getting the IRQ number associated with a PIN -------------------------------------------- - A standard gpiolib function can map the given pin number to an IRQ + The following function can map the given pin number to an IRQ number to pass to the IRQ system. - int gpio_to_irq(unsigned int pin); + int s3c2410_gpio_getirq(unsigned int pin); Note, not all pins have an IRQ. + This call is now implemented by the relevant gpiolib calls, convert + your board or driver to use gpiolib. + -Author +Authour ------- + Ben Dooks, 03 October 2004 Copyright 2004 Ben Dooks, Simtec Electronics diff --git a/trunk/Documentation/arm/Samsung/GPIO.txt b/trunk/Documentation/arm/Samsung/GPIO.txt index 795adfd88081..513f2562c1a3 100644 --- a/trunk/Documentation/arm/Samsung/GPIO.txt +++ b/trunk/Documentation/arm/Samsung/GPIO.txt @@ -5,14 +5,14 @@ Introduction ------------ This outlines the Samsung GPIO implementation and the architecture -specific calls provided alongside the drivers/gpio core. +specific calls provided alongisde the drivers/gpio core. S3C24XX (Legacy) ---------------- See Documentation/arm/Samsung-S3C24XX/GPIO.txt for more information -about these devices. Their implementation has been brought into line +about these devices. Their implementation is being brought into line with the core samsung implementation described in this document. @@ -29,7 +29,7 @@ GPIO numbering is synchronised between the Samsung and gpiolib system. PIN configuration ----------------- -Pin configuration is specific to the Samsung architecture, with each SoC +Pin configuration is specific to the Samsung architecutre, with each SoC registering the necessary information for the core gpio configuration implementation to configure pins as necessary. @@ -38,3 +38,5 @@ driver or machine to change gpio configuration. See arch/arm/plat-samsung/include/plat/gpio-cfg.h for more information on these functions. + + diff --git a/trunk/Documentation/arm/memory.txt b/trunk/Documentation/arm/memory.txt index 4bfb9ffbdbc1..208a2d465b92 100644 --- a/trunk/Documentation/arm/memory.txt +++ b/trunk/Documentation/arm/memory.txt @@ -51,9 +51,6 @@ ffc00000 ffefffff DMA memory mapping region. Memory returned ff000000 ffbfffff Reserved for future expansion of DMA mapping region. -fee00000 feffffff Mapping of PCI I/O space. This is a static - mapping within the vmalloc space. - VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space. Memory returned by vmalloc/ioremap will be dynamically placed in this region. diff --git a/trunk/Documentation/arm64/booting.txt b/trunk/Documentation/arm64/booting.txt deleted file mode 100644 index 9c4d388daddc..000000000000 --- a/trunk/Documentation/arm64/booting.txt +++ /dev/null @@ -1,152 +0,0 @@ - Booting AArch64 Linux - ===================== - -Author: Will Deacon -Date : 07 September 2012 - -This document is based on the ARM booting document by Russell King and -is relevant to all public releases of the AArch64 Linux kernel. - -The AArch64 exception model is made up of a number of exception levels -(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure -counterpart. EL2 is the hypervisor level and exists only in non-secure -mode. EL3 is the highest priority level and exists only in secure mode. - -For the purposes of this document, we will use the term `boot loader' -simply to define all software that executes on the CPU(s) before control -is passed to the Linux kernel. This may include secure monitor and -hypervisor code, or it may just be a handful of instructions for -preparing a minimal boot environment. - -Essentially, the boot loader should provide (as a minimum) the -following: - -1. Setup and initialise the RAM -2. Setup the device tree -3. Decompress the kernel image -4. Call the kernel image - - -1. Setup and initialise RAM ---------------------------- - -Requirement: MANDATORY - -The boot loader is expected to find and initialise all RAM that the -kernel will use for volatile data storage in the system. It performs -this in a machine dependent manner. (It may use internal algorithms -to automatically locate and size all RAM, or it may use knowledge of -the RAM in the machine, or any other method the boot loader designer -sees fit.) - - -2. Setup the device tree -------------------------- - -Requirement: MANDATORY - -The device tree blob (dtb) must be no bigger than 2 megabytes in size -and placed at a 2-megabyte boundary within the first 512 megabytes from -the start of the kernel image. This is to allow the kernel to map the -blob using a single section mapping in the initial page tables. - - -3. Decompress the kernel image ------------------------------- - -Requirement: OPTIONAL - -The AArch64 kernel does not currently provide a decompressor and -therefore requires decompression (gzip etc.) to be performed by the boot -loader if a compressed Image target (e.g. Image.gz) is used. For -bootloaders that do not implement this requirement, the uncompressed -Image target is available instead. - - -4. Call the kernel image ------------------------- - -Requirement: MANDATORY - -The decompressed kernel image contains a 32-byte header as follows: - - u32 magic = 0x14000008; /* branch to stext, little-endian */ - u32 res0 = 0; /* reserved */ - u64 text_offset; /* Image load offset */ - u64 res1 = 0; /* reserved */ - u64 res2 = 0; /* reserved */ - -The image must be placed at the specified offset (currently 0x80000) -from the start of the system RAM and called there. The start of the -system RAM must be aligned to 2MB. - -Before jumping into the kernel, the following conditions must be met: - -- Quiesce all DMA capable devices so that memory does not get - corrupted by bogus network packets or disk data. This will save - you many hours of debug. - -- Primary CPU general-purpose register settings - x0 = physical address of device tree blob (dtb) in system RAM. - x1 = 0 (reserved for future use) - x2 = 0 (reserved for future use) - x3 = 0 (reserved for future use) - -- CPU mode - All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, - IRQ and FIQ). - The CPU must be in either EL2 (RECOMMENDED in order to have access to - the virtualisation extensions) or non-secure EL1. - -- Caches, MMUs - The MMU must be off. - Instruction cache may be on or off. - Data cache must be off and invalidated. - External caches (if present) must be configured and disabled. - -- Architected timers - CNTFRQ must be programmed with the timer frequency. - If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) - set where available. - -- Coherency - All CPUs to be booted by the kernel must be part of the same coherency - domain on entry to the kernel. This may require IMPLEMENTATION DEFINED - initialisation to enable the receiving of maintenance operations on - each CPU. - -- System registers - All writable architected system registers at the exception level where - the kernel image will be entered must be initialised by software at a - higher exception level to prevent execution in an UNKNOWN state. - -The boot loader is expected to enter the kernel on each CPU in the -following manner: - -- The primary CPU must jump directly to the first instruction of the - kernel image. The device tree blob passed by this CPU must contain - for each CPU node: - - 1. An 'enable-method' property. Currently, the only supported value - for this field is the string "spin-table". - - 2. A 'cpu-release-addr' property identifying a 64-bit, - zero-initialised memory location. - - It is expected that the bootloader will generate these device tree - properties and insert them into the blob prior to kernel entry. - -- Any secondary CPUs must spin outside of the kernel in a reserved area - of memory (communicated to the kernel by a /memreserve/ region in the - device tree) polling their cpu-release-addr location, which must be - contained in the reserved region. A wfe instruction may be inserted - to reduce the overhead of the busy-loop and a sev will be issued by - the primary CPU. When a read of the location pointed to by the - cpu-release-addr returns a non-zero value, the CPU must jump directly - to this value. - -- Secondary CPU general-purpose register settings - x0 = 0 (reserved for future use) - x1 = 0 (reserved for future use) - x2 = 0 (reserved for future use) - x3 = 0 (reserved for future use) diff --git a/trunk/Documentation/arm64/memory.txt b/trunk/Documentation/arm64/memory.txt deleted file mode 100644 index dbbdcbba75a3..000000000000 --- a/trunk/Documentation/arm64/memory.txt +++ /dev/null @@ -1,73 +0,0 @@ - Memory Layout on AArch64 Linux - ============================== - -Author: Catalin Marinas -Date : 20 February 2012 - -This document describes the virtual memory layout used by the AArch64 -Linux kernel. The architecture allows up to 4 levels of translation -tables with a 4KB page size and up to 3 levels with a 64KB page size. - -AArch64 Linux uses 3 levels of translation tables with the 4KB page -configuration, allowing 39-bit (512GB) virtual addresses for both user -and kernel. With 64KB pages, only 2 levels of translation tables are -used but the memory layout is the same. - -User addresses have bits 63:39 set to 0 while the kernel addresses have -the same bits set to 1. TTBRx selection is given by bit 63 of the -virtual address. The swapper_pg_dir contains only kernel (global) -mappings while the user pgd contains only user (non-global) mappings. -The swapper_pgd_dir address is written to TTBR1 and never written to -TTBR0. - - -AArch64 Linux memory layout: - -Start End Size Use ------------------------------------------------------------------------ -0000000000000000 0000007fffffffff 512GB user - -ffffff8000000000 ffffffbbfffcffff ~240GB vmalloc - -ffffffbbfffd0000 ffffffbcfffdffff 64KB [guard page] - -ffffffbbfffe0000 ffffffbcfffeffff 64KB PCI I/O space - -ffffffbbffff0000 ffffffbcffffffff 64KB [guard page] - -ffffffbc00000000 ffffffbdffffffff 8GB vmemmap - -ffffffbe00000000 ffffffbffbffffff ~8GB [guard, future vmmemap] - -ffffffbffc000000 ffffffbfffffffff 64MB modules - -ffffffc000000000 ffffffffffffffff 256GB memory - - -Translation table lookup with 4KB pages: - -+--------+--------+--------+--------+--------+--------+--------+--------+ -|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| -+--------+--------+--------+--------+--------+--------+--------+--------+ - | | | | | | - | | | | | v - | | | | | [11:0] in-page offset - | | | | +-> [20:12] L3 index - | | | +-----------> [29:21] L2 index - | | +---------------------> [38:30] L1 index - | +-------------------------------> [47:39] L0 index (not used) - +-------------------------------------------------> [63] TTBR0/1 - - -Translation table lookup with 64KB pages: - -+--------+--------+--------+--------+--------+--------+--------+--------+ -|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| -+--------+--------+--------+--------+--------+--------+--------+--------+ - | | | | | - | | | | v - | | | | [15:0] in-page offset - | | | +----------> [28:16] L3 index - | | +--------------------------> [41:29] L2 index (only 38:29 used) - | +-------------------------------> [47:42] L1 index (not used) - +-------------------------------------------------> [63] TTBR0/1 diff --git a/trunk/Documentation/block/00-INDEX b/trunk/Documentation/block/00-INDEX index d18ecd827c40..d111e3b23db0 100644 --- a/trunk/Documentation/block/00-INDEX +++ b/trunk/Documentation/block/00-INDEX @@ -3,21 +3,15 @@ biodoc.txt - Notes on the Generic Block Layer Rewrite in Linux 2.5 capability.txt - - Generic Block Device Capability (/sys/block//capability) -cfq-iosched.txt - - CFQ IO scheduler tunables -data-integrity.txt - - Block data integrity + - Generic Block Device Capability (/sys/block//capability) deadline-iosched.txt - Deadline IO scheduler tunables ioprio.txt - Block io priorities (in CFQ scheduler) -queue-sysfs.txt - - Queue's sysfs entries request.txt - The members of struct request (in include/linux/blkdev.h) stat.txt - - Block layer statistics in /sys/block//stat + - Block layer statistics in /sys/block//stat switching-sched.txt - Switching I/O schedulers at runtime writeback_cache_control.txt diff --git a/trunk/Documentation/block/cfq-iosched.txt b/trunk/Documentation/block/cfq-iosched.txt index d89b4fe724d7..6d670f570451 100644 --- a/trunk/Documentation/block/cfq-iosched.txt +++ b/trunk/Documentation/block/cfq-iosched.txt @@ -1,14 +1,3 @@ -CFQ (Complete Fairness Queueing) -=============================== - -The main aim of CFQ scheduler is to provide a fair allocation of the disk -I/O bandwidth for all the processes which requests an I/O operation. - -CFQ maintains the per process queue for the processes which request I/O -operation(syncronous requests). In case of asynchronous requests, all the -requests from all the processes are batched together according to their -process's I/O priority. - CFQ ioscheduler tunables ======================== @@ -36,72 +25,6 @@ there are multiple spindles behind single LUN (Host based hardware RAID controller or for storage arrays), setting slice_idle=0 might end up in better throughput and acceptable latencies. -back_seek_max -------------- -This specifies, given in Kbytes, the maximum "distance" for backward seeking. -The distance is the amount of space from the current head location to the -sectors that are backward in terms of distance. - -This parameter allows the scheduler to anticipate requests in the "backward" -direction and consider them as being the "next" if they are within this -distance from the current head location. - -back_seek_penalty ------------------ -This parameter is used to compute the cost of backward seeking. If the -backward distance of request is just 1/back_seek_penalty from a "front" -request, then the seeking cost of two requests is considered equivalent. - -So scheduler will not bias toward one or the other request (otherwise scheduler -will bias toward front request). Default value of back_seek_penalty is 2. - -fifo_expire_async ------------------ -This parameter is used to set the timeout of asynchronous requests. Default -value of this is 248ms. - -fifo_expire_sync ----------------- -This parameter is used to set the timeout of synchronous requests. Default -value of this is 124ms. In case to favor synchronous requests over asynchronous -one, this value should be decreased relative to fifo_expire_async. - -slice_async ------------ -This parameter is same as of slice_sync but for asynchronous queue. The -default value is 40ms. - -slice_async_rq --------------- -This parameter is used to limit the dispatching of asynchronous request to -device request queue in queue's slice time. The maximum number of request that -are allowed to be dispatched also depends upon the io priority. Default value -for this is 2. - -slice_sync ----------- -When a queue is selected for execution, the queues IO requests are only -executed for a certain amount of time(time_slice) before switching to another -queue. This parameter is used to calculate the time slice of synchronous -queue. - -time_slice is computed using the below equation:- -time_slice = slice_sync + (slice_sync/5 * (4 - prio)). To increase the -time_slice of synchronous queue, increase the value of slice_sync. Default -value is 100ms. - -quantum -------- -This specifies the number of request dispatched to the device queue. In a -queue's time slice, a request will not be dispatched if the number of request -in the device exceeds this parameter. This parameter is used for synchronous -request. - -In case of storage with several disk, this setting can limit the parallel -processing of request. Therefore, increasing the value can imporve the -performace although this can cause the latency of some I/O to increase due -to more number of requests. - CFQ IOPS Mode for group scheduling =================================== Basic CFQ design is to provide priority based time slices. Higher priority diff --git a/trunk/Documentation/block/queue-sysfs.txt b/trunk/Documentation/block/queue-sysfs.txt index e54ac1d53403..6518a55273e7 100644 --- a/trunk/Documentation/block/queue-sysfs.txt +++ b/trunk/Documentation/block/queue-sysfs.txt @@ -9,71 +9,20 @@ These files are the ones found in the /sys/block/xxx/queue/ directory. Files denoted with a RO postfix are readonly and the RW postfix means read-write. -add_random (RW) ----------------- -This file allows to trun off the disk entropy contribution. Default -value of this file is '1'(on). - -discard_granularity (RO) ------------------------ -This shows the size of internal allocation of the device in bytes, if -reported by the device. A value of '0' means device does not support -the discard functionality. - -discard_max_bytes (RO) ----------------------- -Devices that support discard functionality may have internal limits on -the number of bytes that can be trimmed or unmapped in a single operation. -The discard_max_bytes parameter is set by the device driver to the maximum -number of bytes that can be discarded in a single operation. Discard -requests issued to the device must not exceed this limit. A discard_max_bytes -value of 0 means that the device does not support discard functionality. - -discard_zeroes_data (RO) ------------------------- -When read, this file will show if the discarded block are zeroed by the -device or not. If its value is '1' the blocks are zeroed otherwise not. - hw_sector_size (RO) ------------------- This is the hardware sector size of the device, in bytes. -iostats (RW) -------------- -This file is used to control (on/off) the iostats accounting of the -disk. - -logical_block_size (RO) ------------------------ -This is the logcal block size of the device, in bytes. - max_hw_sectors_kb (RO) ---------------------- This is the maximum number of kilobytes supported in a single data transfer. -max_integrity_segments (RO) ---------------------------- -When read, this file shows the max limit of integrity segments as -set by block layer which a hardware controller can handle. - max_sectors_kb (RW) ------------------- This is the maximum number of kilobytes that the block layer will allow for a filesystem request. Must be smaller than or equal to the maximum size allowed by the hardware. -max_segments (RO) ------------------ -Maximum number of segments of the device. - -max_segment_size (RO) ---------------------- -Maximum segment size of the device. - -minimum_io_size (RO) --------------------- -This is the smallest preferred io size reported by the device. - nomerges (RW) ------------- This enables the user to disable the lookup logic involved with IO @@ -96,24 +45,11 @@ per-block-cgroup request pool. IOW, if there are N block cgroups, each request queue may have upto N request pools, each independently regulated by nr_requests. -optimal_io_size (RO) --------------------- -This is the optimal io size reported by the device. - -physical_block_size (RO) ------------------------- -This is the physical block size of device, in bytes. - read_ahead_kb (RW) ------------------ Maximum number of kilobytes to read-ahead for filesystems on this block device. -rotational (RW) ---------------- -This file is used to stat if the device is of rotational type or -non-rotational type. - rq_affinity (RW) ---------------- If this option is '1', the block layer will migrate request completions to the diff --git a/trunk/Documentation/devicetree/bindings/arm/pmu.txt b/trunk/Documentation/devicetree/bindings/arm/pmu.txt index 343781b9f246..1c044eb320cc 100644 --- a/trunk/Documentation/devicetree/bindings/arm/pmu.txt +++ b/trunk/Documentation/devicetree/bindings/arm/pmu.txt @@ -7,12 +7,8 @@ representation in the device tree should be done as under:- Required properties: - compatible : should be one of - "arm,cortex-a15-pmu" "arm,cortex-a9-pmu" "arm,cortex-a8-pmu" - "arm,cortex-a7-pmu" - "arm,cortex-a5-pmu" - "arm,arm11mpcore-pmu" "arm,arm1176-pmu" "arm,arm1136-pmu" - interrupts : 1 combined interrupt or 1 per core. diff --git a/trunk/Documentation/devicetree/bindings/misc/at25.txt b/trunk/Documentation/devicetree/bindings/misc/at25.txt index 1d3447165c37..ab3c327929dd 100644 --- a/trunk/Documentation/devicetree/bindings/misc/at25.txt +++ b/trunk/Documentation/devicetree/bindings/misc/at25.txt @@ -1,35 +1,21 @@ -EEPROMs (SPI) compatible with Atmel at25. +Atmel AT25 eeprom Required properties: - compatible : "atmel,at25". - reg : chip select number - spi-max-frequency : max spi frequency to use -- pagesize : size of the eeprom page -- size : total eeprom size in bytes -- address-width : number of address bits (one of 8, 16, or 24) -Optional properties: -- spi-cpha : SPI shifted clock phase, as per spi-bus bindings. -- spi-cpol : SPI inverse clock polarity, as per spi-bus bindings. -- read-only : this parameter-less property disables writes to the eeprom - -Obsolete legacy properties are can be used in place of "size", "pagesize", -"address-width", and "read-only": - at25,byte-len : total eeprom size in bytes - at25,addr-mode : addr-mode flags, as defined in include/linux/spi/eeprom.h - at25,page-size : size of the eeprom page -Additional compatible properties are also allowed. - -Example: - at25@0 { - compatible = "atmel,at25", "st,m95256"; - reg = <0> - spi-max-frequency = <5000000>; - spi-cpha; - spi-cpol; +Examples: +at25@0 { + compatible = "atmel,at25"; + reg = <0> + spi-max-frequency = <5000000>; - pagesize = <64>; - size = <32768>; - address-width = <16>; - }; + at25,byte-len = <0x8000>; + at25,addr-mode = <2>; + at25,page-size = <64>; +}; diff --git a/trunk/Documentation/devicetree/bindings/misc/lis302.txt b/trunk/Documentation/devicetree/bindings/misc/lis302.txt deleted file mode 100644 index 6def86f6b053..000000000000 --- a/trunk/Documentation/devicetree/bindings/misc/lis302.txt +++ /dev/null @@ -1,112 +0,0 @@ -LIS302 accelerometer devicetree bindings - -This device is matched via its bus drivers, and has a number of properties -that apply in on the generic device (independent from the bus). - - -Required properties for the SPI bindings: - - compatible: should be set to "st,lis3lv02d_spi" - - reg: the chipselect index - - spi-max-frequency: maximal bus speed, should be set to 1000000 unless - constrained by external circuitry - - interrupts: the interrupt generated by the device - -Required properties for the I2C bindings: - - compatible: should be set to "st,lis3lv02d" - - reg: i2c slave address - - Vdd-supply: The input supply for Vdd - - Vdd_IO-supply: The input supply for Vdd_IO - - -Optional properties for all bus drivers: - - - st,click-single-{x,y,z}: if present, tells the device to issue an - interrupt on single click events on the - x/y/z axis. - - st,click-double-{x,y,z}: if present, tells the device to issue an - interrupt on double click events on the - x/y/z axis. - - st,click-thresh-{x,y,z}: set the x/y/z axis threshold - - st,click-click-time-limit: click time limit, from 0 to 127.5msec - with step of 0.5 msec - - st,click-latency: click latency, from 0 to 255 msec with - step of 1 msec. - - st,click-window: click window, from 0 to 255 msec with - step of 1 msec. - - st,irq{1,2}-disable: disable IRQ 1/2 - - st,irq{1,2}-ff-wu-1: raise IRQ 1/2 on FF_WU_1 condition - - st,irq{1,2}-ff-wu-2: raise IRQ 1/2 on FF_WU_2 condition - - st,irq{1,2}-data-ready: raise IRQ 1/2 on data ready contition - - st,irq{1,2}-click: raise IRQ 1/2 on click condition - - st,irq-open-drain: consider IRQ lines open-drain - - st,irq-active-low: make IRQ lines active low - - st,wu-duration-1: duration register for Free-Fall/Wake-Up - interrupt 1 - - st,wu-duration-2: duration register for Free-Fall/Wake-Up - interrupt 2 - - st,wakeup-{x,y,z}-{lo,hi}: set wakeup condition on x/y/z axis for - upper/lower limit - - st,highpass-cutoff-hz=: 1, 2, 4 or 8 for 1Hz, 2Hz, 4Hz or 8Hz of - highpass cut-off frequency - - st,hipass{1,2}-disable: disable highpass 1/2. - - st,default-rate=: set the default rate - - st,axis-{x,y,z}=: set the axis to map to the three coordinates - - st,{min,max}-limit-{x,y,z} set the min/max limits for x/y/z axis - (used by self-test) - - -Example for a SPI device node: - - lis302@0 { - compatible = "st,lis302dl-spi"; - reg = <0>; - spi-max-frequency = <1000000>; - interrupt-parent = <&gpio>; - interrupts = <104 0>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - }; - -Example for a I2C device node: - - lis331dlh: lis331dlh@18 { - compatible = "st,lis331dlh", "st,lis3lv02d"; - reg = <0x18>; - Vdd-supply = <&lis3_reg>; - Vdd_IO-supply = <&lis3_reg>; - - st,click-single-x; - st,click-single-y; - st,click-single-z; - st,click-thresh-x = <10>; - st,click-thresh-y = <10>; - st,click-thresh-z = <10>; - st,irq1-click; - st,irq2-click; - st,wakeup-x-lo; - st,wakeup-x-hi; - st,wakeup-y-lo; - st,wakeup-y-hi; - st,wakeup-z-lo; - st,wakeup-z-hi; - st,min-limit-x = <120>; - st,min-limit-y = <120>; - st,min-limit-z = <140>; - st,max-limit-x = <550>; - st,max-limit-y = <550>; - st,max-limit-z = <750>; - }; - diff --git a/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index 1dd622546d06..70cd49b1caa8 100644 --- a/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/trunk/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -10,8 +10,8 @@ Required properties: - compatible : Should be "fsl,-esdhc" Optional properties: -- fsl,cd-controller : Indicate to use controller internal card detection -- fsl,wp-controller : Indicate to use controller internal write protection +- fsl,cd-internal : Indicate to use controller internal card detection +- fsl,wp-internal : Indicate to use controller internal write protection Examples: @@ -19,8 +19,8 @@ esdhc@70004000 { compatible = "fsl,imx51-esdhc"; reg = <0x70004000 0x4000>; interrupts = <1>; - fsl,cd-controller; - fsl,wp-controller; + fsl,cd-internal; + fsl,wp-internal; }; esdhc@70008000 { diff --git a/trunk/Documentation/devicetree/bindings/regulator/regulator.txt b/trunk/Documentation/devicetree/bindings/regulator/regulator.txt index ecfc6ccd67ef..66ece3f87bbc 100644 --- a/trunk/Documentation/devicetree/bindings/regulator/regulator.txt +++ b/trunk/Documentation/devicetree/bindings/regulator/regulator.txt @@ -11,13 +11,10 @@ Optional properties: - regulator-boot-on: bootloader/firmware enabled regulator - -supply: phandle to the parent supply/regulator node - regulator-ramp-delay: ramp delay for regulator(in uV/uS) - -Deprecated properties: - regulator-compatible: If a regulator chip contains multiple regulators, and if the chip's binding contains a child node that describes each regulator, then this property indicates which regulator - this child node is intended to configure. If this property is missing, - the node's name will be used instead. + this child node is intended to configure. Example: diff --git a/trunk/Documentation/devicetree/bindings/regulator/tps65217.txt b/trunk/Documentation/devicetree/bindings/regulator/tps65217.txt index d316fb895daf..0487e9675ba0 100644 --- a/trunk/Documentation/devicetree/bindings/regulator/tps65217.txt +++ b/trunk/Documentation/devicetree/bindings/regulator/tps65217.txt @@ -22,49 +22,66 @@ Example: compatible = "ti,tps65217"; regulators { - dcdc1_reg: dcdc1 { + #address-cells = <1>; + #size-cells = <0>; + + dcdc1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "dcdc1"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; - dcdc2_reg: dcdc2 { + dcdc2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "dcdc2"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - dcdc3_reg: dcc3 { + dcdc3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "dcdc3"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; - ldo1_reg: ldo1 { + ldo1_reg: regulator@3 { + reg = <3>; + regulator-compatible = "ldo1"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo2_reg: ldo2 { + ldo2_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo2"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo3_reg: ldo3 { + ldo3_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo4_reg: ldo4 { + ldo4_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo4"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; diff --git a/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt b/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt index 07b9ef6e49d5..d156e1b5db12 100644 --- a/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt +++ b/trunk/Documentation/devicetree/bindings/regulator/tps6586x.txt @@ -6,16 +6,12 @@ Required properties: - interrupts: the interrupt outputs of the controller - #gpio-cells: number of cells to describe a GPIO - gpio-controller: mark the device as a GPIO controller -- regulators: A node that houses a sub-node for each regulator within the - device. Each sub-node is identified using the node's name (or the deprecated - regulator-compatible property if present), with valid values listed below. - The content of each sub-node is defined by the standard binding for - regulators; see regulator.txt. - sys, sm[0-2], ldo[0-9] and ldo_rtc -- sys-supply: The input supply for SYS. -- vin-sm0-supply: The input supply for the SM0. -- vin-sm1-supply: The input supply for the SM1. -- vin-sm2-supply: The input supply for the SM2. +- regulators: list of regulators provided by this controller, must have + property "regulator-compatible" to match their hardware counterparts: + sm[0-2], ldo[0-9] and ldo_rtc +- sm0-supply: The input supply for the SM0. +- sm1-supply: The input supply for the SM1. +- sm2-supply: The input supply for the SM2. - vinldo01-supply: The input supply for the LDO1 and LDO2 - vinldo23-supply: The input supply for the LDO2 and LDO3 - vinldo4-supply: The input supply for the LDO4 @@ -24,9 +20,6 @@ Required properties: Each regulator is defined using the standard binding for regulators. -Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver - take care of making proper parent child relationship. - Example: pmu: tps6586x@34 { @@ -37,10 +30,9 @@ Example: #gpio-cells = <2>; gpio-controller; - sys-supply = <&some_reg>; - vin-sm0-supply = <&some_reg>; - vin-sm1-supply = <&some_reg>; - vin-sm2-supply = <&some_reg>; + sm0-supply = <&some_reg>; + sm1-supply = <&some_reg>; + sm2-supply = <&some_reg>; vinldo01-supply = <...>; vinldo23-supply = <...>; vinldo4-supply = <...>; @@ -48,80 +40,103 @@ Example: vinldo9-supply = <...>; regulators { - sys_reg: sys { - regulator-name = "vdd_sys"; - regulator-boot-on; - regulator-always-on; - }; + #address-cells = <1>; + #size-cells = <0>; - sm0_reg: sm0 { + sm0_reg: regulator@0 { + reg = <0>; + regulator-compatible = "sm0"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; - sm1_reg: sm1 { + sm1_reg: regulator@1 { + reg = <1>; + regulator-compatible = "sm1"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; - sm2_reg: sm2 { + sm2_reg: regulator@2 { + reg = <2>; + regulator-compatible = "sm2"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <4550000>; regulator-boot-on; regulator-always-on; }; - ldo0_reg: ldo0 { + ldo0_reg: regulator@3 { + reg = <3>; + regulator-compatible = "ldo0"; regulator-name = "PCIE CLK"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - ldo1_reg: ldo1 { + ldo1_reg: regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; - ldo2_reg: ldo2 { + ldo2_reg: regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; regulator-min-microvolt = < 725000>; regulator-max-microvolt = <1500000>; }; - ldo3_reg: ldo3 { + ldo3_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo3"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo4_reg: ldo4 { + ldo4_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; regulator-min-microvolt = <1700000>; regulator-max-microvolt = <2475000>; }; - ldo5_reg: ldo5 { + ldo5_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo6_reg: ldo6 { + ldo6_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo7_reg: ldo7 { + ldo7_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo8_reg: ldo8 { + ldo8_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; - ldo9_reg: ldo9 { + ldo9_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo9"; regulator-min-microvolt = <1250000>; regulator-max-microvolt = <3300000>; }; diff --git a/trunk/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt b/trunk/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt deleted file mode 100644 index 801d58cb6d4d..000000000000 --- a/trunk/Documentation/devicetree/bindings/staging/iio/adc/mxs-lradc.txt +++ /dev/null @@ -1,15 +0,0 @@ -* Freescale i.MX28 LRADC device driver - -Required properties: -- compatible: Should be "fsl,imx28-lradc" -- reg: Address and length of the register set for the device -- interrupts: Should contain the LRADC interrupts - -Examples: - - lradc@80050000 { - compatible = "fsl,imx28-lradc"; - reg = <0x80050000 0x2000>; - interrupts = <10 14 15 16 17 18 19 - 20 21 22 23 24 25>; - }; diff --git a/trunk/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/trunk/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt deleted file mode 100644 index 07654f0338b6..000000000000 --- a/trunk/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt +++ /dev/null @@ -1,41 +0,0 @@ -Freescale i.MX IPUv3 -==================== - -Required properties: -- compatible: Should be "fsl,-ipu" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain sync interrupt and error interrupt, - in this order. -- #crtc-cells: 1, See below - -example: - -ipu: ipu@18000000 { - #crtc-cells = <1>; - compatible = "fsl,imx53-ipu"; - reg = <0x18000000 0x080000000>; - interrupts = <11 10>; -}; - -Parallel display support -======================== - -Required properties: -- compatible: Should be "fsl,imx-parallel-display" -- crtc: the crtc this display is connected to, see below -Optional properties: -- interface_pix_fmt: How this display is connected to the - crtc. Currently supported types: "rgb24", "rgb565" -- edid: verbatim EDID data block describing attached display. -- ddc: phandle describing the i2c bus handling the display data - channel - -example: - -display@di0 { - compatible = "fsl,imx-parallel-display"; - edid = [edid-data]; - crtc = <&ipu 0>; - interface-pix-fmt = "rgb24"; -}; diff --git a/trunk/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt b/trunk/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt deleted file mode 100644 index 0d439dfc1aa5..000000000000 --- a/trunk/Documentation/devicetree/bindings/tty/serial/nxp-lpc32xx-hsuart.txt +++ /dev/null @@ -1,14 +0,0 @@ -* NXP LPC32xx SoC High Speed UART - -Required properties: -- compatible: Should be "nxp,lpc3220-hsuart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt - -Example: - - uart1: serial@40014000 { - compatible = "nxp,lpc3220-hsuart"; - reg = <0x40014000 0x1000>; - interrupts = <26 0>; - }; diff --git a/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt b/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt index ba385f2e0ddc..0847fdeee11a 100644 --- a/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt +++ b/trunk/Documentation/devicetree/bindings/tty/serial/of-serial.txt @@ -25,8 +25,6 @@ Optional properties: accesses to the UART (e.g. TI davinci). - used-by-rtas : set to indicate that the port is in use by the OpenFirmware RTAS and should not be registered. -- no-loopback-test: set to indicate that the port does not implements loopback - test mode Example: diff --git a/trunk/Documentation/devicetree/bindings/usb/am33xx-usb.txt b/trunk/Documentation/devicetree/bindings/usb/am33xx-usb.txt deleted file mode 100644 index ca8fa56e9f03..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/am33xx-usb.txt +++ /dev/null @@ -1,14 +0,0 @@ -AM33XX MUSB GLUE - - compatible : Should be "ti,musb-am33xx" - - ti,hwmods : must be "usb_otg_hs" - - multipoint : Should be "1" indicating the musb controller supports - multipoint. This is a MUSB configuration-specific setting. - - num_eps : Specifies the number of endpoints. This is also a - MUSB configuration-specific setting. Should be set to "16" - - ram_bits : Specifies the ram address size. Should be set to "12" - - port0_mode : Should be "3" to represent OTG. "1" signifies HOST and "2" - represents PERIPHERAL. - - port1_mode : Should be "1" to represent HOST. "3" signifies OTG and "2" - represents PERIPHERAL. - - power : Should be "250". This signifies the controller can supply upto - 500mA when operating in host mode. diff --git a/trunk/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/trunk/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt index 5778b9c83bd8..2c290418bb2d 100644 --- a/trunk/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt +++ b/trunk/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt @@ -7,10 +7,7 @@ Required properties: Optional properties: - fsl,usbphy: phandler of usb phy that connects to the only one port -- fsl,usbmisc: phandler of non-core register device, with one argument - that indicate usb controller index - vbus-supply: regulator for vbus -- disable-over-current: disable over current detect Examples: usb@02184000 { /* USB OTG */ @@ -18,6 +15,4 @@ usb@02184000 { /* USB OTG */ reg = <0x02184000 0x200>; interrupts = <0 43 0x04>; fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; - disable-over-current; }; diff --git a/trunk/Documentation/devicetree/bindings/usb/omap-usb.txt b/trunk/Documentation/devicetree/bindings/usb/omap-usb.txt deleted file mode 100644 index 29a043ecda52..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/omap-usb.txt +++ /dev/null @@ -1,33 +0,0 @@ -OMAP GLUE - -OMAP MUSB GLUE - - compatible : Should be "ti,omap4-musb" or "ti,omap3-musb" - - ti,hwmods : must be "usb_otg_hs" - - multipoint : Should be "1" indicating the musb controller supports - multipoint. This is a MUSB configuration-specific setting. - - num_eps : Specifies the number of endpoints. This is also a - MUSB configuration-specific setting. Should be set to "16" - - ram_bits : Specifies the ram address size. Should be set to "12" - - interface_type : This is a board specific setting to describe the type of - interface between the controller and the phy. It should be "0" or "1" - specifying ULPI and UTMI respectively. - - mode : Should be "3" to represent OTG. "1" signifies HOST and "2" - represents PERIPHERAL. - - power : Should be "50". This signifies the controller can supply upto - 100mA when operating in host mode. - -SOC specific device node entry -usb_otg_hs: usb_otg_hs@4a0ab000 { - compatible = "ti,omap4-musb"; - ti,hwmods = "usb_otg_hs"; - multipoint = <1>; - num_eps = <16>; - ram_bits = <12>; -}; - -Board specific device node entry -&usb_otg_hs { - interface_type = <1>; - mode = <3>; - power = <50>; -}; diff --git a/trunk/Documentation/devicetree/bindings/usb/platform-uhci.txt b/trunk/Documentation/devicetree/bindings/usb/platform-uhci.txt deleted file mode 100644 index 91477d6830ec..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/platform-uhci.txt +++ /dev/null @@ -1,12 +0,0 @@ -Generic Platform UHCI controllers. - -Required properties: - - compatible: Should be "platform-uhci". - - reg: Address range of the uhci registers - - interrupts: Should contain the uhci interrupt. - -usb: uhci@D8007301 { - compatible = "platform-uhci", "usb-uhci"; - reg = <0xD8007301 0x200>; - interrupts = <0>; -}; diff --git a/trunk/Documentation/devicetree/bindings/usb/pxa-usb.txt b/trunk/Documentation/devicetree/bindings/usb/pxa-usb.txt deleted file mode 100644 index 79729a948d5a..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/pxa-usb.txt +++ /dev/null @@ -1,31 +0,0 @@ -PXA USB controllers - -OHCI - -Required properties: - - compatible: Should be "marvell,pxa-ohci" for USB controllers - used in host mode. - -Optional properties: - - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3" - If present, enables the appropriate USB port of the controller. - - "marvell,port-mode" selects the mode of the ports: - 1 = PMM_NPS_MODE - 2 = PMM_GLOBAL_MODE - 3 = PMM_PERPORT_MODE - - "marvell,power-sense-low" - power sense pin is low-active. - - "marvell,power-control-low" - power control pin is low-active. - - "marvell,no-oc-protection" - disable over-current protection. - - "marvell,oc-mode-perport" - enable per-port over-current protection. - - "marvell,power_on_delay" Power On to Power Good time - in ms. - -Example: - - usb0: ohci@4c000000 { - compatible = "marvell,pxa-ohci", "usb-ohci"; - reg = <0x4c000000 0x100000>; - interrupts = <18>; - marvell,enable-port1; - marvell,port-mode = <2>; /* PMM_GLOBAL_MODE */ - }; - diff --git a/trunk/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt b/trunk/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt deleted file mode 100644 index 36b9aede3f40..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/twlxxxx-usb.txt +++ /dev/null @@ -1,40 +0,0 @@ -USB COMPARATOR OF TWL CHIPS - -TWL6030 USB COMPARATOR - - compatible : Should be "ti,twl6030-usb" - - interrupts : Two interrupt numbers to the cpu should be specified. First - interrupt number is the otg interrupt number that raises ID interrupts when - the controller has to act as host and the second interrupt number is the - usb interrupt number that raises VBUS interrupts when the controller has to - act as device - - usb-supply : phandle to the regulator device tree node. It should be vusb - if it is twl6030 or ldousb if it is twl6025 subclass. - -twl6030-usb { - compatible = "ti,twl6030-usb"; - interrupts = < 4 10 >; -}; - -Board specific device node entry -&twl6030-usb { - usb-supply = <&vusb>; -}; - -TWL4030 USB PHY AND COMPARATOR - - compatible : Should be "ti,twl4030-usb" - - interrupts : The interrupt numbers to the cpu should be specified. First - interrupt number is the otg interrupt number that raises ID interrupts - and VBUS interrupts. The second interrupt number is optional. - - -supply : phandle to the regulator device tree node. - should be vusb1v5, vusb1v8 and vusb3v1 - - usb_mode : The mode used by the phy to connect to the controller. "1" - specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode. - -twl4030-usb { - compatible = "ti,twl4030-usb"; - interrupts = < 10 4 >; - usb1v5-supply = <&vusb1v5>; - usb1v8-supply = <&vusb1v8>; - usb3v1-supply = <&vusb3v1>; - usb_mode = <1>; -}; diff --git a/trunk/Documentation/devicetree/bindings/usb/usb-phy.txt b/trunk/Documentation/devicetree/bindings/usb/usb-phy.txt deleted file mode 100644 index 80d4148cb661..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/usb-phy.txt +++ /dev/null @@ -1,17 +0,0 @@ -USB PHY - -OMAP USB2 PHY - -Required properties: - - compatible: Should be "ti,omap-usb2" - - reg : Address and length of the register set for the device. Also -add the address of control module dev conf register until a driver for -control module is added - -This is usually a subnode of ocp2scp to which it is connected. - -usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>, - <0x4a002300 0x4>; -}; diff --git a/trunk/Documentation/devicetree/bindings/usb/usbmisc-imx.txt b/trunk/Documentation/devicetree/bindings/usb/usbmisc-imx.txt deleted file mode 100644 index 97ce94e1a6cc..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/usbmisc-imx.txt +++ /dev/null @@ -1,14 +0,0 @@ -* Freescale i.MX non-core registers - -Required properties: -- #index-cells: Cells used to descibe usb controller index. Should be <1> -- compatible: Should be one of below: - "fsl,imx6q-usbmisc" for imx6q -- reg: Should contain registers location and length - -Examples: -usbmisc@02184800 { - #index-cells = <1>; - compatible = "fsl,imx6q-usbmisc"; - reg = <0x02184800 0x200>; -}; diff --git a/trunk/Documentation/devicetree/bindings/usb/vt8500-ehci.txt b/trunk/Documentation/devicetree/bindings/usb/vt8500-ehci.txt deleted file mode 100644 index 5fb8fd6e250c..000000000000 --- a/trunk/Documentation/devicetree/bindings/usb/vt8500-ehci.txt +++ /dev/null @@ -1,12 +0,0 @@ -VIA VT8500 and Wondermedia WM8xxx SoC USB controllers. - -Required properties: - - compatible: Should be "via,vt8500-ehci" or "wm,prizm-ehci". - - reg: Address range of the ehci registers. size should be 0x200 - - interrupts: Should contain the ehci interrupt. - -usb: ehci@D8007100 { - compatible = "wm,prizm-ehci", "usb-ehci"; - reg = <0xD8007100 0x200>; - interrupts = <1>; -}; diff --git a/trunk/Documentation/devicetree/bindings/w1/w1-gpio.txt b/trunk/Documentation/devicetree/bindings/w1/w1-gpio.txt deleted file mode 100644 index 6e09c35d9f1a..000000000000 --- a/trunk/Documentation/devicetree/bindings/w1/w1-gpio.txt +++ /dev/null @@ -1,22 +0,0 @@ -w1-gpio devicetree bindings - -Required properties: - - - compatible: "w1-gpio" - - gpios: one or two GPIO specs: - - the first one is used as data I/O pin - - the second one is optional. If specified, it is used as - enable pin for an external pin pullup. - -Optional properties: - - - linux,open-drain: if specified, the data pin is considered in - open-drain mode. - -Examples: - - onewire@0 { - compatible = "w1-gpio"; - gpios = <&gpio 126 0>, <&gpio 105 0>; - }; - diff --git a/trunk/Documentation/dontdiff b/trunk/Documentation/dontdiff index 74c25c8d8884..39462cf35cd4 100644 --- a/trunk/Documentation/dontdiff +++ b/trunk/Documentation/dontdiff @@ -162,6 +162,7 @@ mach-types.h machtypes.h map map_hugetlb +maui_boot.h media mconf miboot* diff --git a/trunk/Documentation/feature-removal-schedule.txt b/trunk/Documentation/feature-removal-schedule.txt new file mode 100644 index 000000000000..afaff312bf41 --- /dev/null +++ b/trunk/Documentation/feature-removal-schedule.txt @@ -0,0 +1,639 @@ +The following is a list of files and features that are going to be +removed in the kernel source tree. Every entry should contain what +exactly is going away, why it is happening, and who is going to be doing +the work. When the feature is removed from the kernel, it should also +be removed from this file. The suggested deprecation period is 3 releases. + +--------------------------- + +What: ddebug_query="query" boot cmdline param +When: v3.8 +Why: obsoleted by dyndbg="query" and module.dyndbg="query" +Who: Jim Cromie , Jason Baron + +--------------------------- + +What: /proc/sys/vm/nr_pdflush_threads +When: 2012 +Why: Since pdflush is deprecated, the interface exported in /proc/sys/vm/ + should be removed. +Who: Wanpeng Li + +--------------------------- + +What: CONFIG_APM_CPU_IDLE, and its ability to call APM BIOS in idle +When: 2012 +Why: This optional sub-feature of APM is of dubious reliability, + and ancient APM laptops are likely better served by calling HLT. + Deleting CONFIG_APM_CPU_IDLE allows x86 to stop exporting + the pm_idle function pointer to modules. +Who: Len Brown + +---------------------------- + +What: x86_32 "no-hlt" cmdline param +When: 2012 +Why: remove a branch from idle path, simplify code used by everybody. + This option disabled the use of HLT in idle and machine_halt() + for hardware that was flakey 15-years ago. Today we have + "idle=poll" that removed HLT from idle, and so if such a machine + is still running the upstream kernel, "idle=poll" is likely sufficient. +Who: Len Brown + +---------------------------- + +What: x86 "idle=mwait" cmdline param +When: 2012 +Why: simplify x86 idle code +Who: Len Brown + +---------------------------- + +What: PRISM54 +When: 2.6.34 + +Why: prism54 FullMAC PCI / Cardbus devices used to be supported only by the + prism54 wireless driver. After Intersil stopped selling these + devices in preference for the newer more flexible SoftMAC devices + a SoftMAC device driver was required and prism54 did not support + them. The p54pci driver now exists and has been present in the kernel for + a while. This driver supports both SoftMAC devices and FullMAC devices. + The main difference between these devices was the amount of memory which + could be used for the firmware. The SoftMAC devices support a smaller + amount of memory. Because of this the SoftMAC firmware fits into FullMAC + devices's memory. p54pci supports not only PCI / Cardbus but also USB + and SPI. Since p54pci supports all devices prism54 supports + you will have a conflict. I'm not quite sure how distributions are + handling this conflict right now. prism54 was kept around due to + claims users may experience issues when using the SoftMAC driver. + Time has passed users have not reported issues. If you use prism54 + and for whatever reason you cannot use p54pci please let us know! + E-mail us at: linux-wireless@vger.kernel.org + + For more information see the p54 wiki page: + + http://wireless.kernel.org/en/users/Drivers/p54 + +Who: Luis R. Rodriguez + +--------------------------- + +What: The ieee80211_regdom module parameter +When: March 2010 / desktop catchup + +Why: This was inherited by the CONFIG_WIRELESS_OLD_REGULATORY code, + and currently serves as an option for users to define an + ISO / IEC 3166 alpha2 code for the country they are currently + present in. Although there are userspace API replacements for this + through nl80211 distributions haven't yet caught up with implementing + decent alternatives through standard GUIs. Although available as an + option through iw or wpa_supplicant its just a matter of time before + distributions pick up good GUI options for this. The ideal solution + would actually consist of intelligent designs which would do this for + the user automatically even when travelling through different countries. + Until then we leave this module parameter as a compromise. + + When userspace improves with reasonable widely-available alternatives for + this we will no longer need this module parameter. This entry hopes that + by the super-futuristically looking date of "March 2010" we will have + such replacements widely available. + +Who: Luis R. Rodriguez + +--------------------------- + +What: dev->power.power_state +When: July 2007 +Why: Broken design for runtime control over driver power states, confusing + driver-internal runtime power management with: mechanisms to support + system-wide sleep state transitions; event codes that distinguish + different phases of swsusp "sleep" transitions; and userspace policy + inputs. This framework was never widely used, and most attempts to + use it were broken. Drivers should instead be exposing domain-specific + interfaces either to kernel or to userspace. +Who: Pavel Machek + +--------------------------- + +What: /proc//oom_adj +When: August 2012 +Why: /proc//oom_adj allows userspace to influence the oom killer's + badness heuristic used to determine which task to kill when the kernel + is out of memory. + + The badness heuristic has since been rewritten since the introduction of + this tunable such that its meaning is deprecated. The value was + implemented as a bitshift on a score generated by the badness() + function that did not have any precise units of measure. With the + rewrite, the score is given as a proportion of available memory to the + task allocating pages, so using a bitshift which grows the score + exponentially is, thus, impossible to tune with fine granularity. + + A much more powerful interface, /proc//oom_score_adj, was + introduced with the oom killer rewrite that allows users to increase or + decrease the badness score linearly. This interface will replace + /proc//oom_adj. + + A warning will be emitted to the kernel log if an application uses this + deprecated interface. After it is printed once, future warnings will be + suppressed until the kernel is rebooted. + +--------------------------- + +What: remove EXPORT_SYMBOL(kernel_thread) +When: August 2006 +Files: arch/*/kernel/*_ksyms.c +Check: kernel_thread +Why: kernel_thread is a low-level implementation detail. Drivers should + use the API instead which shields them from + implementation details and provides a higherlevel interface that + prevents bugs and code duplication +Who: Christoph Hellwig + +--------------------------- + +What: Unused EXPORT_SYMBOL/EXPORT_SYMBOL_GPL exports + (temporary transition config option provided until then) + The transition config option will also be removed at the same time. +When: before 2.6.19 +Why: Unused symbols are both increasing the size of the kernel binary + and are often a sign of "wrong API" +Who: Arjan van de Ven + +--------------------------- + +What: PHYSDEVPATH, PHYSDEVBUS, PHYSDEVDRIVER in the uevent environment +When: October 2008 +Why: The stacking of class devices makes these values misleading and + inconsistent. + Class devices should not carry any of these properties, and bus + devices have SUBSYTEM and DRIVER as a replacement. +Who: Kay Sievers + +--------------------------- + +What: ACPI procfs interface +When: July 2008 +Why: ACPI sysfs conversion should be finished by January 2008. + ACPI procfs interface will be removed in July 2008 so that + there is enough time for the user space to catch up. +Who: Zhang Rui + +--------------------------- + +What: CONFIG_ACPI_PROCFS_POWER +When: 2.6.39 +Why: sysfs I/F for ACPI power devices, including AC and Battery, + has been working in upstream kernel since 2.6.24, Sep 2007. + In 2.6.37, we make the sysfs I/F always built in and this option + disabled by default. + Remove this option and the ACPI power procfs interface in 2.6.39. +Who: Zhang Rui + +--------------------------- + +What: /proc/acpi/event +When: February 2008 +Why: /proc/acpi/event has been replaced by events via the input layer + and netlink since 2.6.23. +Who: Len Brown + +--------------------------- + +What: i386/x86_64 bzImage symlinks +When: April 2010 + +Why: The i386/x86_64 merge provides a symlink to the old bzImage + location so not yet updated user space tools, e.g. package + scripts, do not break. +Who: Thomas Gleixner + +--------------------------- + +What: GPIO autorequest on gpio_direction_{input,output}() in gpiolib +When: February 2010 +Why: All callers should use explicit gpio_request()/gpio_free(). + The autorequest mechanism in gpiolib was provided mostly as a + migration aid for legacy GPIO interfaces (for SOC based GPIOs). + Those users have now largely migrated. Platforms implementing + the GPIO interfaces without using gpiolib will see no changes. +Who: David Brownell +--------------------------- + +What: b43 support for firmware revision < 410 +When: The schedule was July 2008, but it was decided that we are going to keep the + code as long as there are no major maintanance headaches. + So it _could_ be removed _any_ time now, if it conflicts with something new. +Why: The support code for the old firmware hurts code readability/maintainability + and slightly hurts runtime performance. Bugfixes for the old firmware + are not provided by Broadcom anymore. +Who: Michael Buesch + +--------------------------- + +What: Ability for non root users to shm_get hugetlb pages based on mlock + resource limits +When: 2.6.31 +Why: Non root users need to be part of /proc/sys/vm/hugetlb_shm_group or + have CAP_IPC_LOCK to be able to allocate shm segments backed by + huge pages. The mlock based rlimit check to allow shm hugetlb is + inconsistent with mmap based allocations. Hence it is being + deprecated. +Who: Ravikiran Thirumalai + +--------------------------- + +What: sysfs ui for changing p4-clockmod parameters +When: September 2009 +Why: See commits 129f8ae9b1b5be94517da76009ea956e89104ce8 and + e088e4c9cdb618675874becb91b2fd581ee707e6. + Removal is subject to fixing any remaining bugs in ACPI which may + cause the thermal throttling not to happen at the right time. +Who: Dave Jones , Matthew Garrett + +----------------------------- + +What: fakephp and associated sysfs files in /sys/bus/pci/slots/ +When: 2011 +Why: In 2.6.27, the semantics of /sys/bus/pci/slots was redefined to + represent a machine's physical PCI slots. The change in semantics + had userspace implications, as the hotplug core no longer allowed + drivers to create multiple sysfs files per physical slot (required + for multi-function devices, e.g.). fakephp was seen as a developer's + tool only, and its interface changed. Too late, we learned that + there were some users of the fakephp interface. + + In 2.6.30, the original fakephp interface was restored. At the same + time, the PCI core gained the ability that fakephp provided, namely + function-level hot-remove and hot-add. + + Since the PCI core now provides the same functionality, exposed in: + + /sys/bus/pci/rescan + /sys/bus/pci/devices/.../remove + /sys/bus/pci/devices/.../rescan + + there is no functional reason to maintain fakephp as well. + + We will keep the existing module so that 'modprobe fakephp' will + present the old /sys/bus/pci/slots/... interface for compatibility, + but users are urged to migrate their applications to the API above. + + After a reasonable transition period, we will remove the legacy + fakephp interface. +Who: Alex Chiang + +--------------------------- + +What: CONFIG_RFKILL_INPUT +When: 2.6.33 +Why: Should be implemented in userspace, policy daemon. +Who: Johannes Berg + +---------------------------- + +What: sound-slot/service-* module aliases and related clutters in + sound/sound_core.c +When: August 2010 +Why: OSS sound_core grabs all legacy minors (0-255) of SOUND_MAJOR + (14) and requests modules using custom sound-slot/service-* + module aliases. The only benefit of doing this is allowing + use of custom module aliases which might as well be considered + a bug at this point. This preemptive claiming prevents + alternative OSS implementations. + + Till the feature is removed, the kernel will be requesting + both sound-slot/service-* and the standard char-major-* module + aliases and allow turning off the pre-claiming selectively via + CONFIG_SOUND_OSS_CORE_PRECLAIM and soundcore.preclaim_oss + kernel parameter. + + After the transition phase is complete, both the custom module + aliases and switches to disable it will go away. This removal + will also allow making ALSA OSS emulation independent of + sound_core. The dependency will be broken then too. +Who: Tejun Heo + +---------------------------- + +What: sysfs-class-rfkill state file +When: Feb 2014 +Files: net/rfkill/core.c +Why: Documented as obsolete since Feb 2010. This file is limited to 3 + states while the rfkill drivers can have 4 states. +Who: anybody or Florian Mickler + +---------------------------- + +What: sysfs-class-rfkill claim file +When: Feb 2012 +Files: net/rfkill/core.c +Why: It is not possible to claim an rfkill driver since 2007. This is + Documented as obsolete since Feb 2010. +Who: anybody or Florian Mickler + +---------------------------- + +What: iwlwifi 50XX module parameters +When: 3.0 +Why: The "..50" modules parameters were used to configure 5000 series and + up devices; different set of module parameters also available for 4965 + with same functionalities. Consolidate both set into single place + in drivers/net/wireless/iwlwifi/iwl-agn.c + +Who: Wey-Yi Guy + +---------------------------- + +What: iwl4965 alias support +When: 3.0 +Why: Internal alias support has been present in module-init-tools for some + time, the MODULE_ALIAS("iwl4965") boilerplate aliases can be removed + with no impact. + +Who: Wey-Yi Guy + +--------------------------- + +What: xt_NOTRACK +Files: net/netfilter/xt_NOTRACK.c +When: April 2011 +Why: Superseded by xt_CT +Who: Netfilter developer team + +---------------------------- + +What: IRQF_DISABLED +When: 2.6.36 +Why: The flag is a NOOP as we run interrupt handlers with interrupts disabled +Who: Thomas Gleixner + +---------------------------- + +What: PCI DMA unmap state API +When: August 2012 +Why: PCI DMA unmap state API (include/linux/pci-dma.h) was replaced + with DMA unmap state API (DMA unmap state API can be used for + any bus). +Who: FUJITA Tomonori + +---------------------------- + +What: iwlwifi disable_hw_scan module parameters +When: 3.0 +Why: Hareware scan is the prefer method for iwlwifi devices for + scanning operation. Remove software scan support for all the + iwlwifi devices. + +Who: Wey-Yi Guy + +---------------------------- + +What: Legacy, non-standard chassis intrusion detection interface. +When: June 2011 +Why: The adm9240, w83792d and w83793 hardware monitoring drivers have + legacy interfaces for chassis intrusion detection. A standard + interface has been added to each driver, so the legacy interface + can be removed. +Who: Jean Delvare + +---------------------------- + +What: i2c_driver.attach_adapter + i2c_driver.detach_adapter +When: September 2011 +Why: These legacy callbacks should no longer be used as i2c-core offers + a variety of preferable alternative ways to instantiate I2C devices. +Who: Jean Delvare + +---------------------------- + +What: Opening a radio device node will no longer automatically switch the + tuner mode from tv to radio. +When: 3.3 +Why: Just opening a V4L device should not change the state of the hardware + like that. It's very unexpected and against the V4L spec. Instead, you + switch to radio mode by calling VIDIOC_S_FREQUENCY. This is the second + and last step of the move to consistent handling of tv and radio tuners. +Who: Hans Verkuil + +---------------------------- + +What: CONFIG_CFG80211_WEXT +When: as soon as distributions ship new wireless tools, ie. wpa_supplicant 1.0 + and NetworkManager/connman/etc. that are able to use nl80211 +Why: Wireless extensions are deprecated, and userland tools are moving to + using nl80211. New drivers are no longer using wireless extensions, + and while there might still be old drivers, both new drivers and new + userland no longer needs them and they can't be used for an feature + developed in the past couple of years. As such, compatibility with + wireless extensions in new drivers will be removed. +Who: Johannes Berg + +---------------------------- + +What: g_file_storage driver +When: 3.8 +Why: This driver has been superseded by g_mass_storage. +Who: Alan Stern + +---------------------------- + +What: threeg and interface sysfs files in /sys/devices/platform/acer-wmi +When: 2012 +Why: In 3.0, we can now autodetect internal 3G device and already have + the threeg rfkill device. So, we plan to remove threeg sysfs support + for it's no longer necessary. + + We also plan to remove interface sysfs file that exposed which ACPI-WMI + interface that was used by acer-wmi driver. It will replaced by + information log when acer-wmi initial. +Who: Lee, Chun-Yi + +--------------------------- + +What: /sys/devices/platform/_UDC_/udc/_UDC_/is_dualspeed file and + is_dualspeed line in /sys/devices/platform/ci13xxx_*/udc/device file. +When: 3.8 +Why: The is_dualspeed file is superseded by maximum_speed in the same + directory and is_dualspeed line in device file is superseded by + max_speed line in the same file. + + The maximum_speed/max_speed specifies maximum speed supported by UDC. + To check if dualspeeed is supported, check if the value is >= 3. + Various possible speeds are defined in . +Who: Michal Nazarewicz + +---------------------------- + +What: The XFS nodelaylog mount option +When: 3.3 +Why: The delaylog mode that has been the default since 2.6.39 has proven + stable, and the old code is in the way of additional improvements in + the log code. +Who: Christoph Hellwig + +---------------------------- + +What: iwlagn alias support +When: 3.5 +Why: The iwlagn module has been renamed iwlwifi. The alias will be around + for backward compatibility for several cycles and then dropped. +Who: Don Fry + +---------------------------- + +What: pci_scan_bus_parented() +When: 3.5 +Why: The pci_scan_bus_parented() interface creates a new root bus. The + bus is created with default resources (ioport_resource and + iomem_resource) that are always wrong, so we rely on arch code to + correct them later. Callers of pci_scan_bus_parented() should + convert to using pci_scan_root_bus() so they can supply a list of + bus resources when the bus is created. +Who: Bjorn Helgaas + +---------------------------- + +What: Low Performance USB Block driver ("CONFIG_BLK_DEV_UB") +When: 3.6 +Why: This driver provides support for USB storage devices like "USB + sticks". As of now, it is deactivated in Debian, Fedora and + Ubuntu. All current users can switch over to usb-storage + (CONFIG_USB_STORAGE) which only drawback is the additional SCSI + stack. +Who: Sebastian Andrzej Siewior + +---------------------------- + +What: get_robust_list syscall +When: 2013 +Why: There appear to be no production users of the get_robust_list syscall, + and it runs the risk of leaking address locations, allowing the bypass + of ASLR. It was only ever intended for debugging, so it should be + removed. +Who: Kees Cook + +---------------------------- + +What: Removing the pn544 raw driver. +When: 3.6 +Why: With the introduction of the NFC HCI and SHDL kernel layers, pn544.c + is being replaced by pn544_hci.c which is accessible through the netlink + and socket NFC APIs. Moreover, pn544.c is outdated and does not seem to + work properly with the latest Android stacks. + Having 2 drivers for the same hardware is confusing and as such we + should only keep the one following the kernel NFC APIs. +Who: Samuel Ortiz + +---------------------------- + +What: setitimer accepts user NULL pointer (value) +When: 3.6 +Why: setitimer is not returning -EFAULT if user pointer is NULL. This + violates the spec. +Who: Sasikantha Babu + +---------------------------- + +What: remove bogus DV presets V4L2_DV_1080I29_97, V4L2_DV_1080I30 and + V4L2_DV_1080I25 +When: 3.6 +Why: These HDTV formats do not exist and were added by a confused mind + (that was me, to be precise...) +Who: Hans Verkuil + +---------------------------- + +What: V4L2_CID_HCENTER, V4L2_CID_VCENTER V4L2 controls +When: 3.7 +Why: The V4L2_CID_VCENTER, V4L2_CID_HCENTER controls have been deprecated + for about 4 years and they are not used by any mainline driver. + There are newer controls (V4L2_CID_PAN*, V4L2_CID_TILT*) that provide + similar functionality. +Who: Sylwester Nawrocki + +---------------------------- + +What: cgroup option updates via remount +When: March 2013 +Why: Remount currently allows changing bound subsystems and + release_agent. Rebinding is hardly useful as it only works + when the hierarchy is empty and release_agent itself should be + replaced with conventional fsnotify. + +---------------------------- + +What: xt_recent rev 0 +When: 2013 +Who: Pablo Neira Ayuso +Files: net/netfilter/xt_recent.c + +---------------------------- + +What: KVM debugfs statistics +When: 2013 +Why: KVM tracepoints provide mostly equivalent information in a much more + flexible fashion. + +---------------------------- + +What: at91-mci driver ("CONFIG_MMC_AT91") +When: 3.7 +Why: There are two mci drivers: at91-mci and atmel-mci. The PDC support + was added to atmel-mci as a first step to support more chips. + Then at91-mci was kept only for old IP versions (on at91rm9200 and + at91sam9261). The support of these IP versions has just been added + to atmel-mci, so atmel-mci can be used for all chips. +Who: Ludovic Desroches + +---------------------------- + +What: net/wanrouter/ +When: June 2013 +Why: Unsupported/unmaintained/unused since 2.6 + +---------------------------- + +What: V4L2 selections API target rectangle and flags unification, the + following definitions will be removed: V4L2_SEL_TGT_CROP_ACTIVE, + V4L2_SEL_TGT_COMPOSE_ACTIVE, V4L2_SUBDEV_SEL_*, V4L2_SUBDEV_SEL_FLAG_* + in favor of common V4L2_SEL_TGT_* and V4L2_SEL_FLAG_* definitions. + For more details see include/linux/v4l2-common.h. +When: 3.8 +Why: The regular V4L2 selections and the subdev selection API originally + defined distinct names for the target rectangles and flags - V4L2_SEL_* + and V4L2_SUBDEV_SEL_*. Although, it turned out that the meaning of these + target rectangles is virtually identical and the APIs were consolidated + to use single set of names - V4L2_SEL_*. This didn't involve any ABI + changes. Alias definitions were created for the original ones to avoid + any instabilities in the user space interface. After few cycles these + backward compatibility definitions will be removed. +Who: Sylwester Nawrocki + +---------------------------- + +What: Using V4L2_CAP_VIDEO_CAPTURE and V4L2_CAP_VIDEO_OUTPUT flags + to indicate a V4L2 memory-to-memory device capability +When: 3.8 +Why: New drivers should use new V4L2_CAP_VIDEO_M2M capability flag + to indicate a V4L2 video memory-to-memory (M2M) device and + applications can now identify a M2M video device by checking + for V4L2_CAP_VIDEO_M2M, with VIDIOC_QUERYCAP ioctl. Using ORed + V4L2_CAP_VIDEO_CAPTURE and V4L2_CAP_VIDEO_OUTPUT flags for M2M + devices is ambiguous and may lead, for example, to identifying + a M2M device as a video capture or output device. +Who: Sylwester Nawrocki + +---------------------------- + +What: OMAP private DMA implementation +When: 2013 +Why: We have a DMA engine implementation; all users should be updated + to use this rather than persisting with the old APIs. The old APIs + block merging the old DMA engine implementation into the DMA + engine driver. +Who: Russell King , + Santosh Shilimkar + +---------------------------- diff --git a/trunk/Documentation/filesystems/Locking b/trunk/Documentation/filesystems/Locking index e540a24e5d06..0f103e39b4f6 100644 --- a/trunk/Documentation/filesystems/Locking +++ b/trunk/Documentation/filesystems/Locking @@ -114,6 +114,7 @@ prototypes: int (*drop_inode) (struct inode *); void (*evict_inode) (struct inode *); void (*put_super) (struct super_block *); + void (*write_super) (struct super_block *); int (*sync_fs)(struct super_block *sb, int wait); int (*freeze_fs) (struct super_block *); int (*unfreeze_fs) (struct super_block *); @@ -135,6 +136,7 @@ write_inode: drop_inode: !!!inode->i_lock!!! evict_inode: put_super: write +write_super: read sync_fs: read freeze_fs: write unfreeze_fs: write diff --git a/trunk/Documentation/filesystems/debugfs.txt b/trunk/Documentation/filesystems/debugfs.txt index 3a863f692728..7a34f827989c 100644 --- a/trunk/Documentation/filesystems/debugfs.txt +++ b/trunk/Documentation/filesystems/debugfs.txt @@ -15,8 +15,8 @@ Debugfs is typically mounted with a command like: mount -t debugfs none /sys/kernel/debug (Or an equivalent /etc/fstab line). -The debugfs root directory is accessible only to the root user by -default. To change access to the tree the "uid", "gid" and "mode" mount +The debugfs root directory is accessible by anyone by default. To +restrict access to the tree the "uid", "gid" and "mode" mount options can be used. Note that the debugfs API is exported GPL-only to modules. diff --git a/trunk/Documentation/filesystems/porting b/trunk/Documentation/filesystems/porting index 0742feebc6e2..2bef2b3843d1 100644 --- a/trunk/Documentation/filesystems/porting +++ b/trunk/Documentation/filesystems/porting @@ -94,8 +94,9 @@ protected. --- [mandatory] -BKL is also moved from around sb operations. BKL should have been shifted into -individual fs sb_op functions. If you don't need it, remove it. +BKL is also moved from around sb operations. ->write_super() Is now called +without BKL held. BKL should have been shifted into individual fs sb_op +functions. If you don't need it, remove it. --- [informational] diff --git a/trunk/Documentation/filesystems/vfat.txt b/trunk/Documentation/filesystems/vfat.txt index de1e6c4dccff..ead764b2728f 100644 --- a/trunk/Documentation/filesystems/vfat.txt +++ b/trunk/Documentation/filesystems/vfat.txt @@ -137,17 +137,6 @@ errors=panic|continue|remount-ro without doing anything or remount the partition in read-only mode (default behavior). -discard -- If set, issues discard/TRIM commands to the block - device when blocks are freed. This is useful for SSD devices - and sparse/thinly-provisoned LUNs. - -nfs -- This option maintains an index (cache) of directory - inodes by i_logstart which is used by the nfs-related code to - improve look-ups. - - Enable this only if you want to export the FAT filesystem - over NFS - : 0,1,yes,no,true,false TODO diff --git a/trunk/Documentation/filesystems/vfs.txt b/trunk/Documentation/filesystems/vfs.txt index 2ee133e030c3..065aa2dc0835 100644 --- a/trunk/Documentation/filesystems/vfs.txt +++ b/trunk/Documentation/filesystems/vfs.txt @@ -216,6 +216,7 @@ struct super_operations { void (*drop_inode) (struct inode *); void (*delete_inode) (struct inode *); void (*put_super) (struct super_block *); + void (*write_super) (struct super_block *); int (*sync_fs)(struct super_block *sb, int wait); int (*freeze_fs) (struct super_block *); int (*unfreeze_fs) (struct super_block *); @@ -272,6 +273,9 @@ or bottom half). put_super: called when the VFS wishes to free the superblock (i.e. unmount). This is called with the superblock lock held + write_super: called when the VFS superblock needs to be written to + disc. This method is optional + sync_fs: called when VFS is writing out all dirty data associated with a superblock. The second parameter indicates whether the method should wait until the write out has been completed. Optional. diff --git a/trunk/Documentation/hid/hid-sensor.txt b/trunk/Documentation/hid/hid-sensor.txt deleted file mode 100755 index 948b0989c433..000000000000 --- a/trunk/Documentation/hid/hid-sensor.txt +++ /dev/null @@ -1,140 +0,0 @@ - -HID Sensors Framework -====================== -HID sensor framework provides necessary interfaces to implement sensor drivers, -which are connected to a sensor hub. The sensor hub is a HID device and it provides -a report descriptor conforming to HID 1.12 sensor usage tables. - -Description from the HID 1.12 "HID Sensor Usages" specification: -"Standardization of HID usages for sensors would allow (but not require) sensor -hardware vendors to provide a consistent Plug And Play interface at the USB boundary, -thereby enabling some operating systems to incorporate common device drivers that -could be reused between vendors, alleviating any need for the vendors to provide -the drivers themselves." - -This specification describes many usage IDs, which describe the type of sensor -and also the individual data fields. Each sensor can have variable number of -data fields. The length and order is specified in the report descriptor. For -example a part of report descriptor can look like: - - INPUT(1)[INPUT] - .. - Field(2) - Physical(0020.0073) - Usage(1) - 0020.045f - Logical Minimum(-32767) - Logical Maximum(32767) - Report Size(8) - Report Count(1) - Report Offset(16) - Flags(Variable Absolute) -.. -.. - -The report is indicating "sensor page (0x20)" contains an accelerometer-3D (0x73). -This accelerometer-3D has some fields. Here for example field 2 is motion intensity -(0x045f) with a logical minimum value of -32767 and logical maximum of 32767. The -order of fields and length of each field is important as the input event raw -data will use this format. - - -Implementation -================= - -This specification defines many different types of sensors with different sets of -data fields. It is difficult to have a common input event to user space applications, -for different sensors. For example an accelerometer can send X,Y and Z data, whereas -an ambient light sensor can send illumination data. -So the implementation has two parts: -- Core hid driver -- Individual sensor processing part (sensor drivers) - -Core driver ------------ -The core driver registers (hid-sensor-hub) registers as a HID driver. It parses -report descriptors and identifies all the sensors present. It adds an MFD device -with name HID-SENSOR-xxxx (where xxxx is usage id from the specification). -For example -HID-SENSOR-200073 is registered for an Accelerometer 3D driver. -So if any driver with this name is inserted, then the probe routine for that -function will be called. So an accelerometer processing driver can register -with this name and will be probed if there is an accelerometer-3D detected. - -The core driver provides a set of APIs which can be used by the processing -drivers to register and get events for that usage id. Also it provides parsing -functions, which get and set each input/feature/output report. - -Individual sensor processing part (sensor drivers) ------------ -The processing driver will use an interface provided by the core driver to parse -the report and get the indexes of the fields and also can get events. This driver -can use IIO interface to use the standard ABI defined for a type of sensor. - - -Core driver Interface -===================== - -Callback structure: -Each processing driver can use this structure to set some callbacks. - int (*suspend)(..): Callback when HID suspend is received - int (*resume)(..): Callback when HID resume is received - int (*capture_sample)(..): Capture a sample for one of its data fields - int (*send_event)(..): One complete event is received which can have - multiple data fields. - -Registration functions: -int sensor_hub_register_callback(struct hid_sensor_hub_device *hsdev, - u32 usage_id, - struct hid_sensor_hub_callbacks *usage_callback): - -Registers callbacks for an usage id. The callback functions are not allowed -to sleep. - - -int sensor_hub_remove_callback(struct hid_sensor_hub_device *hsdev, - u32 usage_id): - -Removes callbacks for an usage id. - - -Parsing function: -int sensor_hub_input_get_attribute_info(struct hid_sensor_hub_device *hsdev, - u8 type, - u32 usage_id, u32 attr_usage_id, - struct hid_sensor_hub_attribute_info *info); - -A processing driver can look for some field of interest and check if it exists -in a report descriptor. If it exists it will store necessary information -so that fields can be set or get individually. -These indexes avoid searching every time and getting field index to get or set. - - -Set Feature report -int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id, - u32 field_index, s32 value); - -This interface is used to set a value for a field in feature report. For example -if there is a field report_interval, which is parsed by a call to -sensor_hub_input_get_attribute_info before, then it can directly set that individual -field. - - -int sensor_hub_get_feature(struct hid_sensor_hub_device *hsdev, u32 report_id, - u32 field_index, s32 *value); - -This interface is used to get a value for a field in input report. For example -if there is a field report_interval, which is parsed by a call to -sensor_hub_input_get_attribute_info before, then it can directly get that individual -field value. - - -int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev, - u32 usage_id, - u32 attr_usage_id, u32 report_id); - -This is used to get a particular field value through input reports. For example -accelerometer wants to poll X axis value, then it can call this function with -the usage id of X axis. HID sensors can provide events, so this is not necessary -to poll for any field. If there is some new sample, the core driver will call -registered callback function to process the sample. diff --git a/trunk/Documentation/hwmon/adt7410 b/trunk/Documentation/hwmon/adt7410 deleted file mode 100644 index 96004000dc2a..000000000000 --- a/trunk/Documentation/hwmon/adt7410 +++ /dev/null @@ -1,51 +0,0 @@ -Kernel driver adt7410 -===================== - -Supported chips: - * Analog Devices ADT7410 - Prefix: 'adt7410' - Addresses scanned: I2C 0x48 - 0x4B - Datasheet: Publicly available at the Analog Devices website - http://www.analog.com/static/imported-files/data_sheets/ADT7410.pdf - -Author: Hartmut Knaack - -Description ------------ - -The ADT7410 is a temperature sensor with rated temperature range of -55°C to -+150°C. It has a high accuracy of +/-0.5°C and can be operated at a resolution -of 13 bits (0.0625°C) or 16 bits (0.0078°C). The sensor provides an INT pin to -indicate that a minimum or maximum temperature set point has been exceeded, as -well as a critical temperature (CT) pin to indicate that the critical -temperature set point has been exceeded. Both pins can be set up with a common -hysteresis of 0°C - 15°C and a fault queue, ranging from 1 to 4 events. Both -pins can individually set to be active-low or active-high, while the whole -device can either run in comparator mode or interrupt mode. The ADT7410 -supports continous temperature sampling, as well as sampling one temperature -value per second or even justget one sample on demand for power saving. -Besides, it can completely power down its ADC, if power management is -required. - -Configuration Notes -------------------- - -Since the device uses one hysteresis value, which is an offset to minimum, -maximum and critical temperature, it can only be set for temp#_max_hyst. -However, temp#_min_hyst and temp#_crit_hyst show their corresponding -hysteresis. -The device is set to 16 bit resolution and comparator mode. - -sysfs-Interface ---------------- - -temp#_input - temperature input -temp#_min - temperature minimum setpoint -temp#_max - temperature maximum setpoint -temp#_crit - critical temperature setpoint -temp#_min_hyst - hysteresis for temperature minimum (read-only) -temp#_max_hyst - hysteresis for temperature maximum (read/write) -temp#_crit_hyst - hysteresis for critical temperature (read-only) -temp#_min_alarm - temperature minimum alarm flag -temp#_max_alarm - temperature maximum alarm flag -temp#_crit_alarm - critical temperature alarm flag diff --git a/trunk/Documentation/hwmon/ina2xx b/trunk/Documentation/hwmon/ina2xx index 03444f9d833f..f50a6cc27616 100644 --- a/trunk/Documentation/hwmon/ina2xx +++ b/trunk/Documentation/hwmon/ina2xx @@ -8,24 +8,12 @@ Supported chips: Datasheet: Publicly available at the Texas Instruments website http://www.ti.com/ - * Texas Instruments INA220 - Prefix: 'ina220' - Addresses: I2C 0x40 - 0x4f - Datasheet: Publicly available at the Texas Instruments website - http://www.ti.com/ - * Texas Instruments INA226 Prefix: 'ina226' Addresses: I2C 0x40 - 0x4f Datasheet: Publicly available at the Texas Instruments website http://www.ti.com/ - * Texas Instruments INA230 - Prefix: 'ina230' - Addresses: I2C 0x40 - 0x4f - Datasheet: Publicly available at the Texas Instruments website - http://www.ti.com/ - Author: Lothar Felten Description @@ -35,13 +23,7 @@ The INA219 is a high-side current shunt and power monitor with an I2C interface. The INA219 monitors both shunt drop and supply voltage, with programmable conversion times and filtering. -The INA220 is a high or low side current shunt and power monitor with an I2C -interface. The INA220 monitors both shunt drop and supply voltage. - The INA226 is a current shunt and power monitor with an I2C interface. The INA226 monitors both a shunt voltage drop and bus supply voltage. -The INA230 is a high or low side current shunt and power monitor with an I2C -interface. The INA230 monitors both a shunt voltage drop and bus supply voltage. - The shunt value in micro-ohms can be set via platform data. diff --git a/trunk/Documentation/hwmon/lm70 b/trunk/Documentation/hwmon/lm70 index 86d182942c51..0d240291e3cc 100644 --- a/trunk/Documentation/hwmon/lm70 +++ b/trunk/Documentation/hwmon/lm70 @@ -6,10 +6,6 @@ Supported chips: Datasheet: http://www.national.com/pf/LM/LM70.html * Texas Instruments TMP121/TMP123 Information: http://focus.ti.com/docs/prod/folders/print/tmp121.html - * National Semiconductor LM71 - Datasheet: http://www.ti.com/product/LM71 - * National Semiconductor LM74 - Datasheet: http://www.ti.com/product/LM74 Author: Kaiwan N Billimoria @@ -35,11 +31,9 @@ As a real (in-tree) example of this "SPI protocol driver" interfacing with a "SPI master controller driver", see drivers/spi/spi_lm70llp.c and its associated documentation. -The LM74 and TMP121/TMP123 are very similar; main difference is 13-bit -temperature data (0.0625 degrees celsius resolution). - -The LM71 is also very similar; main difference is 14-bit temperature -data (0.03125 degrees celsius resolution). +The TMP121/TMP123 are very similar; main differences are 4 wire SPI inter- +face (read only) and 13-bit temperature data (0.0625 degrees celsius reso- +lution). Thanks to --------- diff --git a/trunk/Documentation/hwmon/max197 b/trunk/Documentation/hwmon/max197 deleted file mode 100644 index 8d89b9009df8..000000000000 --- a/trunk/Documentation/hwmon/max197 +++ /dev/null @@ -1,60 +0,0 @@ -Maxim MAX197 driver -=================== - -Author: - * Vivien Didelot - -Supported chips: - * Maxim MAX197 - Prefix: 'max197' - Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX197.pdf - - * Maxim MAX199 - Prefix: 'max199' - Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX199.pdf - -Description ------------ - -The A/D converters MAX197, and MAX199 are both 8-Channel, Multi-Range, 5V, -12-Bit DAS with 8+4 Bus Interface and Fault Protection. - -The available ranges for the MAX197 are {0,-5V} to 5V, and {0,-10V} to 10V, -while they are {0,-2V} to 2V, and {0,-4V} to 4V on the MAX199. - -Platform data -------------- - -The MAX197 platform data (defined in linux/platform_data/max197.h) should be -filled with a pointer to a conversion function, defined like: - - int convert(u8 ctrl); - -ctrl is the control byte to write to start a new conversion. -On success, the function must return the 12-bit raw value read from the chip, -or a negative error code otherwise. - -Control byte format: - -Bit Name Description -7,6 PD1,PD0 Clock and Power-Down modes -5 ACQMOD Internal or External Controlled Acquisition -4 RNG Full-scale voltage magnitude at the input -3 BIP Unipolar or Bipolar conversion mode -2,1,0 A2,A1,A0 Channel - -Sysfs interface ---------------- - -* in[0-7]_input: The conversion value for the corresponding channel. - RO - -* in[0-7]_min: The lower limit (in mV) for the corresponding channel. - For the MAX197, it will be adjusted to -10000, -5000, or 0. - For the MAX199, it will be adjusted to -4000, -2000, or 0. - RW - -* in[0-7]_max: The higher limit (in mV) for the corresponding channel. - For the MAX197, it will be adjusted to 0, 5000, or 10000. - For the MAX199, it will be adjusted to 0, 2000, or 4000. - RW diff --git a/trunk/Documentation/hwmon/mcp3021 b/trunk/Documentation/hwmon/mcp3021 index 74a6b72adf5f..325fd87e81b2 100644 --- a/trunk/Documentation/hwmon/mcp3021 +++ b/trunk/Documentation/hwmon/mcp3021 @@ -5,25 +5,18 @@ Supported chips: * Microchip Technology MCP3021 Prefix: 'mcp3021' Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/21805a.pdf - * Microchip Technology MCP3221 - Prefix: 'mcp3221' - Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/21732c.pdf -Authors: - Mingkai Hu - Sven Schuchmann +Author: Mingkai Hu Description ----------- -This driver implements support for the Microchip Technology MCP3021 and -MCP3221 chip. +This driver implements support for the Microchip Technology MCP3021 chip. The Microchip Technology Inc. MCP3021 is a successive approximation A/D -converter (ADC) with 10-bit resolution. The MCP3221 has 12-bit resolution. - -These devices provide one single-ended input with very low power consumption. -Communication to the MCP3021/MCP3221 is performed using a 2-wire I2C -compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are -available. The default I2C device address is 0x4d (contact the Microchip -factory for additional address options). +converter (ADC) with 10-bit resolution. +This device provides one single-ended input with very low power consumption. +Communication to the MCP3021 is performed using a 2-wire I2C compatible +interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are available. +The default I2C device address is 0x4d (contact the Microchip factory for +additional address options). diff --git a/trunk/Documentation/i2c/busses/i2c-i801 b/trunk/Documentation/i2c/busses/i2c-i801 index 157416e78cc4..615142da4ef6 100644 --- a/trunk/Documentation/i2c/busses/i2c-i801 +++ b/trunk/Documentation/i2c/busses/i2c-i801 @@ -21,7 +21,6 @@ Supported adapters: * Intel DH89xxCC (PCH) * Intel Panther Point (PCH) * Intel Lynx Point (PCH) - * Intel Lynx Point-LP (PCH) Datasheets: Publicly available at the Intel website On Intel Patsburg and later chipsets, both the normal host SMBus controller diff --git a/trunk/Documentation/ia64/aliasing-test.c b/trunk/Documentation/ia64/aliasing-test.c index 62a190d45f38..5caa2af33207 100644 --- a/trunk/Documentation/ia64/aliasing-test.c +++ b/trunk/Documentation/ia64/aliasing-test.c @@ -132,7 +132,6 @@ static int read_rom(char *path) rc = write(fd, "1", 2); if (rc <= 0) { - close(fd); perror("write"); return -1; } diff --git a/trunk/Documentation/kernel-parameters.txt b/trunk/Documentation/kernel-parameters.txt index df43807bb5da..ad7e2e5088c1 100644 --- a/trunk/Documentation/kernel-parameters.txt +++ b/trunk/Documentation/kernel-parameters.txt @@ -1812,12 +1812,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. noexec=on: enable non-executable mappings (default) noexec=off: disable non-executable mappings - nosmap [X86] - Disable SMAP (Supervisor Mode Access Prevention) - even if it is supported by processor. - nosmep [X86] - Disable SMEP (Supervisor Mode Execution Prevention) + Disable SMEP (Supervisor Mode Execution Protection) even if it is supported by processor. noexec32 [X86-64] @@ -1837,12 +1833,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted. and restore using xsave. The kernel will fallback to enabling legacy floating-point and sse state. - eagerfpu= [X86] - on enable eager fpu restore - off disable eager fpu restore - auto selects the default scheme, which automatically - enables eagerfpu restore for xsaveopt. - nohlt [BUGS=ARM,SH] Tells the kernel that the sleep(SH) or wfi(ARM) instruction doesn't work correctly and not to use it. This is also useful when using JTAG debugger. @@ -2395,17 +2385,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted. rcutree.rcu_cpu_stall_timeout= [KNL,BOOT] Set timeout for RCU CPU stall warning messages. - rcutree.jiffies_till_first_fqs= [KNL,BOOT] - Set delay from grace-period initialization to - first attempt to force quiescent states. - Units are jiffies, minimum value is zero, - and maximum value is HZ. - - rcutree.jiffies_till_next_fqs= [KNL,BOOT] - Set delay between subsequent attempts to force - quiescent states. Units are jiffies, minimum - value is one, and maximum value is HZ. - rcutorture.fqs_duration= [KNL,BOOT] Set duration of force_quiescent_state bursts. @@ -2659,6 +2638,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted. smart2= [HW] Format: [,[,...,]] + smp-alt-once [X86-32,SMP] On a hotplug CPU system, only + attempt to substitute SMP alternatives once at boot. + smsc-ircc2.nopnp [HW] Don't use PNP to discover SMC devices smsc-ircc2.ircc_cfg= [HW] Device configuration I/O port smsc-ircc2.ircc_sir= [HW] SIR base I/O port diff --git a/trunk/Documentation/kobject.txt b/trunk/Documentation/kobject.txt index c5182bb2c16c..49578cf1aea5 100644 --- a/trunk/Documentation/kobject.txt +++ b/trunk/Documentation/kobject.txt @@ -284,11 +284,9 @@ instead, it is associated with the ktype. So let us introduce struct kobj_type: struct kobj_type { - void (*release)(struct kobject *kobj); + void (*release)(struct kobject *); const struct sysfs_ops *sysfs_ops; - struct attribute **default_attrs; - const struct kobj_ns_type_operations *(*child_ns_type)(struct kobject *kobj); - const void *(*namespace)(struct kobject *kobj); + struct attribute **default_attrs; }; This structure is used to describe a particular type of kobject (or, more diff --git a/trunk/Documentation/laptops/laptop-mode.txt b/trunk/Documentation/laptops/laptop-mode.txt index 4ebbfc3f1c6e..0bf25eebce94 100644 --- a/trunk/Documentation/laptops/laptop-mode.txt +++ b/trunk/Documentation/laptops/laptop-mode.txt @@ -262,9 +262,9 @@ MINIMUM_BATTERY_MINUTES=10 # # Allowed dirty background ratio, in percent. Once DIRTY_RATIO has been -# exceeded, the kernel will wake flusher threads which will then reduce the -# amount of dirty memory to dirty_background_ratio. Set this nice and low, -# so once some writeout has commenced, we do a lot of it. +# exceeded, the kernel will wake pdflush which will then reduce the amount +# of dirty memory to dirty_background_ratio. Set this nice and low, so once +# some writeout has commenced, we do a lot of it. # #DIRTY_BACKGROUND_RATIO=5 @@ -384,9 +384,9 @@ CPU_MAXFREQ=${CPU_MAXFREQ:-'slowest'} # # Allowed dirty background ratio, in percent. Once DIRTY_RATIO has been -# exceeded, the kernel will wake flusher threads which will then reduce the -# amount of dirty memory to dirty_background_ratio. Set this nice and low, -# so once some writeout has commenced, we do a lot of it. +# exceeded, the kernel will wake pdflush which will then reduce the amount +# of dirty memory to dirty_background_ratio. Set this nice and low, so once +# some writeout has commenced, we do a lot of it. # DIRTY_BACKGROUND_RATIO=${DIRTY_BACKGROUND_RATIO:-'5'} diff --git a/trunk/Documentation/misc-devices/lis3lv02d b/trunk/Documentation/misc-devices/lis3lv02d index af815b9ba413..f1a4ec840f86 100644 --- a/trunk/Documentation/misc-devices/lis3lv02d +++ b/trunk/Documentation/misc-devices/lis3lv02d @@ -4,8 +4,7 @@ Kernel driver lis3lv02d Supported chips: * STMicroelectronics LIS3LV02DL, LIS3LV02DQ (12 bits precision) - * STMicroelectronics LIS302DL, LIS3L02DQ, LIS331DL (8 bits) and - LIS331DLH (16 bits) + * STMicroelectronics LIS302DL, LIS3L02DQ, LIS331DL (8 bits) Authors: Yan Burman diff --git a/trunk/Documentation/networking/netconsole.txt b/trunk/Documentation/networking/netconsole.txt index 2e9e0ae2cd45..8d022073e3ef 100644 --- a/trunk/Documentation/networking/netconsole.txt +++ b/trunk/Documentation/networking/netconsole.txt @@ -51,23 +51,8 @@ Built-in netconsole starts immediately after the TCP stack is initialized and attempts to bring up the supplied dev at the supplied address. -The remote host has several options to receive the kernel messages, -for example: - -1) syslogd - -2) netcat - - On distributions using a BSD-based netcat version (e.g. Fedora, - openSUSE and Ubuntu) the listening port must be specified without - the -p switch: - - 'nc -u -l -p ' / 'nc -u -l ' or - 'netcat -u -l -p ' / 'netcat -u -l ' - -3) socat - - 'socat udp-recv: -' +The remote host can run either 'netcat -u -l -p ', +'nc -l -u ' or syslogd. Dynamic reconfiguration: ======================== diff --git a/trunk/Documentation/pinctrl.txt b/trunk/Documentation/pinctrl.txt index 1479aca23744..e40f4b4e1977 100644 --- a/trunk/Documentation/pinctrl.txt +++ b/trunk/Documentation/pinctrl.txt @@ -840,9 +840,9 @@ static unsigned long i2c_pin_configs[] = { static struct pinctrl_map __initdata mapping[] = { PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"), - PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs), - PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs), - PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs), + PIN_MAP_MUX_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs), + PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs), + PIN_MAP_MUX_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs), }; Finally, some devices expect the mapping table to contain certain specific diff --git a/trunk/Documentation/power/swsusp.txt b/trunk/Documentation/power/swsusp.txt index 0b4b63e7e9b6..92341b84250d 100644 --- a/trunk/Documentation/power/swsusp.txt +++ b/trunk/Documentation/power/swsusp.txt @@ -53,7 +53,7 @@ before suspend (it is limited to 500 MB by default). Article about goals and implementation of Software Suspend for Linux ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Author: Gábor Kuti +Author: G‚ábor Kuti Last revised: 2003-10-20 by Pavel Machek Idea and goals to achieve diff --git a/trunk/Documentation/scheduler/sched-arch.txt b/trunk/Documentation/scheduler/sched-arch.txt index b1b8587b86f0..28aa1075e291 100644 --- a/trunk/Documentation/scheduler/sched-arch.txt +++ b/trunk/Documentation/scheduler/sched-arch.txt @@ -17,6 +17,16 @@ you must `#define __ARCH_WANT_UNLOCKED_CTXSW` in a header file Unlocked context switches introduce only a very minor performance penalty to the core scheduler implementation in the CONFIG_SMP case. +2. Interrupt status +By default, the switch_to arch function is called with interrupts +disabled. Interrupts may be enabled over the call if it is likely to +introduce a significant interrupt latency by adding the line +`#define __ARCH_WANT_INTERRUPTS_ON_CTXSW` in the same place as for +unlocked context switches. This define also implies +`__ARCH_WANT_UNLOCKED_CTXSW`. See arch/arm/include/asm/system.h for an +example. + + CPU idle ======== Your cpu_idle routines need to obey the following rules: diff --git a/trunk/Documentation/security/Yama.txt b/trunk/Documentation/security/Yama.txt index dd908cf64ecf..e369de2d48cd 100644 --- a/trunk/Documentation/security/Yama.txt +++ b/trunk/Documentation/security/Yama.txt @@ -46,13 +46,14 @@ restrictions, it can call prctl(PR_SET_PTRACER, PR_SET_PTRACER_ANY, ...) so that any otherwise allowed process (even those in external pid namespaces) may attach. -The sysctl settings (writable only with CAP_SYS_PTRACE) are: +These restrictions do not change how ptrace via PTRACE_TRACEME operates. + +The sysctl settings are: 0 - classic ptrace permissions: a process can PTRACE_ATTACH to any other process running under the same uid, as long as it is dumpable (i.e. did not transition uids, start privileged, or have called - prctl(PR_SET_DUMPABLE...) already). Similarly, PTRACE_TRACEME is - unchanged. + prctl(PR_SET_DUMPABLE...) already). 1 - restricted ptrace: a process must have a predefined relationship with the inferior it wants to call PTRACE_ATTACH on. By default, @@ -60,13 +61,12 @@ The sysctl settings (writable only with CAP_SYS_PTRACE) are: classic criteria is also met. To change the relationship, an inferior can call prctl(PR_SET_PTRACER, debugger, ...) to declare an allowed debugger PID to call PTRACE_ATTACH on the inferior. - Using PTRACE_TRACEME is unchanged. 2 - admin-only attach: only processes with CAP_SYS_PTRACE may use ptrace - with PTRACE_ATTACH, or through children calling PTRACE_TRACEME. + with PTRACE_ATTACH. -3 - no attach: no processes may use ptrace with PTRACE_ATTACH nor via - PTRACE_TRACEME. Once set, this sysctl value cannot be changed. +3 - no attach: no processes may use ptrace with PTRACE_ATTACH. Once set, + this sysctl cannot be changed to a lower value. The original children-only logic was based on the restrictions in grsecurity. diff --git a/trunk/Documentation/serial/00-INDEX b/trunk/Documentation/serial/00-INDEX index f7b0c7dc25ef..e09468ad3cb1 100644 --- a/trunk/Documentation/serial/00-INDEX +++ b/trunk/Documentation/serial/00-INDEX @@ -2,6 +2,8 @@ - this file. README.cycladesZ - info on Cyclades-Z firmware loading. +computone.txt + - info on Computone Intelliport II/Plus Multiport Serial Driver. digiepca.txt - info on Digi Intl. {PC,PCI,EISA}Xx and Xem series cards. hayes-esp.txt diff --git a/trunk/Documentation/serial/computone.txt b/trunk/Documentation/serial/computone.txt new file mode 100644 index 000000000000..a6a1158ea2ba --- /dev/null +++ b/trunk/Documentation/serial/computone.txt @@ -0,0 +1,520 @@ +NOTE: This is an unmaintained driver. It is not guaranteed to work due to +changes made in the tty layer in 2.6. If you wish to take over maintenance of +this driver, contact Michael Warfield . + +Changelog: +---------- +11-01-2001: Original Document + +10-29-2004: Minor misspelling & format fix, update status of driver. + James Nelson + +Computone Intelliport II/Plus Multiport Serial Driver +----------------------------------------------------- + +Release Notes For Linux Kernel 2.2 and higher. +These notes are for the drivers which have already been integrated into the +kernel and have been tested on Linux kernels 2.0, 2.2, 2.3, and 2.4. + +Version: 1.2.14 +Date: 11/01/2001 +Historical Author: Andrew Manison +Primary Author: Doug McNash + +This file assumes that you are using the Computone drivers which are +integrated into the kernel sources. For updating the drivers or installing +drivers into kernels which do not already have Computone drivers, please +refer to the instructions in the README.computone file in the driver patch. + + +1. INTRODUCTION + +This driver supports the entire family of Intelliport II/Plus controllers +with the exception of the MicroChannel controllers. It does not support +products previous to the Intelliport II. + +This driver was developed on the v2.0.x Linux tree and has been tested up +to v2.4.14; it will probably not work with earlier v1.X kernels,. + + +2. QUICK INSTALLATION + +Hardware - If you have an ISA card, find a free interrupt and io port. + List those in use with `cat /proc/interrupts` and + `cat /proc/ioports`. Set the card dip switches to a free + address. You may need to configure your BIOS to reserve an + irq for an ISA card. PCI and EISA parameters are set + automagically. Insert card into computer with the power off + before or after drivers installation. + + Note the hardware address from the Computone ISA cards installed into + the system. These are required for editing ip2.c or editing + /etc/modprobe.d/*.conf, or for specification on the modprobe + command line. + + Note that the /etc/modules.conf should be used for older (pre-2.6) + kernels. + +Software - + +Module installation: + +a) Determine free irq/address to use if any (configure BIOS if need be) +b) Run "make config" or "make menuconfig" or "make xconfig" + Select (m) module for CONFIG_COMPUTONE under character + devices. CONFIG_PCI and CONFIG_MODULES also may need to be set. +c) Set address on ISA cards then: + edit /usr/src/linux/drivers/char/ip2.c if needed + or + edit config file in /etc/modprobe.d/ if needed (module). + or both to match this setting. +d) Run "make modules" +e) Run "make modules_install" +f) Run "/sbin/depmod -a" +g) install driver using `modprobe ip2 ` (options listed below) +h) run ip2mkdev (either the script below or the binary version) + + +Kernel installation: + +a) Determine free irq/address to use if any (configure BIOS if need be) +b) Run "make config" or "make menuconfig" or "make xconfig" + Select (y) kernel for CONFIG_COMPUTONE under character + devices. CONFIG_PCI may need to be set if you have PCI bus. +c) Set address on ISA cards then: + edit /usr/src/linux/drivers/char/ip2.c + (Optional - may be specified on kernel command line now) +d) Run "make zImage" or whatever target you prefer. +e) mv /usr/src/linux/arch/x86/boot/zImage to /boot. +f) Add new config for this kernel into /etc/lilo.conf, run "lilo" + or copy to a floppy disk and boot from that floppy disk. +g) Reboot using this kernel +h) run ip2mkdev (either the script below or the binary version) + +Kernel command line options: + +When compiling the driver into the kernel, io and irq may be +compiled into the driver by editing ip2.c and setting the values for +io and irq in the appropriate array. An alternative is to specify +a command line parameter to the kernel at boot up. + + ip2=io0,irq0,io1,irq1,io2,irq2,io3,irq3 + +Note that this order is very different from the specifications for the +modload parameters which have separate IRQ and IO specifiers. + +The io port also selects PCI (1) and EISA (2) boards. + + io=0 No board + io=1 PCI board + io=2 EISA board + else ISA board io address + +You only need to specify the boards which are present. + + Examples: + + 2 PCI boards: + + ip2=1,0,1,0 + + 1 ISA board at 0x310 irq 5: + + ip2=0x310,5 + +This can be added to and "append" option in lilo.conf similar to this: + + append="ip2=1,0,1,0" + + +3. INSTALLATION + +Previously, the driver sources were packaged with a set of patch files +to update the character drivers' makefile and configuration file, and other +kernel source files. A build script (ip2build) was included which applies +the patches if needed, and build any utilities needed. +What you receive may be a single patch file in conventional kernel +patch format build script. That form can also be applied by +running patch -p1 < ThePatchFile. Otherwise run ip2build. + +The driver can be installed as a module (recommended) or built into the +kernel. This is selected as for other drivers through the `make config` +command from the root of the Linux source tree. If the driver is built +into the kernel you will need to edit the file ip2.c to match the boards +you are installing. See that file for instructions. If the driver is +installed as a module the configuration can also be specified on the +modprobe command line as follows: + + modprobe ip2 irq=irq1,irq2,irq3,irq4 io=addr1,addr2,addr3,addr4 + +where irqnum is one of the valid Intelliport II interrupts (3,4,5,7,10,11, +12,15) and addr1-4 are the base addresses for up to four controllers. If +the irqs are not specified the driver uses the default in ip2.c (which +selects polled mode). If no base addresses are specified the defaults in +ip2.c are used. If you are autoloading the driver module with kerneld or +kmod the base addresses and interrupt number must also be set in ip2.c +and recompile or just insert and options line in /etc/modprobe.d/*.conf or both. +The options line is equivalent to the command line and takes precedence over +what is in ip2.c. + +config sample to put /etc/modprobe.d/*.conf: + options ip2 io=1,0x328 irq=1,10 + alias char-major-71 ip2 + alias char-major-72 ip2 + alias char-major-73 ip2 + +The equivalent in ip2.c: + +static int io[IP2_MAX_BOARDS]= { 1, 0x328, 0, 0 }; +static int irq[IP2_MAX_BOARDS] = { 1, 10, -1, -1 }; + +The equivalent for the kernel command line (in lilo.conf): + + append="ip2=1,1,0x328,10" + + +Note: Both io and irq should be updated to reflect YOUR system. An "io" + address of 1 or 2 indicates a PCI or EISA card in the board table. + The PCI or EISA irq will be assigned automatically. + +Specifying an invalid or in-use irq will default the driver into +running in polled mode for that card. If all irq entries are 0 then +all cards will operate in polled mode. + +If you select the driver as part of the kernel run : + + make zlilo (or whatever you do to create a bootable kernel) + +If you selected a module run : + + make modules && make modules_install + +The utility ip2mkdev (see 5 and 7 below) creates all the device nodes +required by the driver. For a device to be created it must be configured +in the driver and the board must be installed. Only devices corresponding +to real IntelliPort II ports are created. With multiple boards and expansion +boxes this will leave gaps in the sequence of device names. ip2mkdev uses +Linux tty naming conventions: ttyF0 - ttyF255 for normal devices, and +cuf0 - cuf255 for callout devices. + + +4. USING THE DRIVERS + +As noted above, the driver implements the ports in accordance with Linux +conventions, and the devices should be interchangeable with the standard +serial devices. (This is a key point for problem reporting: please make +sure that what you are trying do works on the ttySx/cuax ports first; then +tell us what went wrong with the ip2 ports!) + +Higher speeds can be obtained using the setserial utility which remaps +38,400 bps (extb) to 57,600 bps, 115,200 bps, or a custom speed. +Intelliport II installations using the PowerPort expansion module can +use the custom speed setting to select the highest speeds: 153,600 bps, +230,400 bps, 307,200 bps, 460,800bps and 921,600 bps. The base for +custom baud rate configuration is fixed at 921,600 for cards/expansion +modules with ST654's and 115200 for those with Cirrus CD1400's. This +corresponds to the maximum bit rates those chips are capable. +For example if the baud base is 921600 and the baud divisor is 18 then +the custom rate is 921600/18 = 51200 bps. See the setserial man page for +complete details. Of course if stty accepts the higher rates now you can +use that as well as the standard ioctls(). + + +5. ip2mkdev and assorted utilities... + +Several utilities, including the source for a binary ip2mkdev utility are +available under .../drivers/char/ip2. These can be build by changing to +that directory and typing "make" after the kernel has be built. If you do +not wish to compile the binary utilities, the shell script below can be +cut out and run as "ip2mkdev" to create the necessary device files. To +use the ip2mkdev script, you must have procfs enabled and the proc file +system mounted on /proc. + + +6. NOTES + +This is a release version of the driver, but it is impossible to test it +in all configurations of Linux. If there is any anomalous behaviour that +does not match the standard serial port's behaviour please let us know. + + +7. ip2mkdev shell script + +Previously, this script was simply attached here. It is now attached as a +shar archive to make it easier to extract the script from the documentation. +To create the ip2mkdev shell script change to a convenient directory (/tmp +works just fine) and run the following command: + + unshar Documentation/serial/computone.txt + (This file) + +You should now have a file ip2mkdev in your current working directory with +permissions set to execute. Running that script with then create the +necessary devices for the Computone boards, interfaces, and ports which +are present on you system at the time it is run. + + +#!/bin/sh +# This is a shell archive (produced by GNU sharutils 4.2.1). +# To extract the files from this archive, save it to some FILE, remove +# everything before the `!/bin/sh' line above, then type `sh FILE'. +# +# Made on 2001-10-29 10:32 EST by . +# Source directory was `/home2/src/tmp'. +# +# Existing files will *not* be overwritten unless `-c' is specified. +# +# This shar contains: +# length mode name +# ------ ---------- ------------------------------------------ +# 4251 -rwxr-xr-x ip2mkdev +# +save_IFS="${IFS}" +IFS="${IFS}:" +gettext_dir=FAILED +locale_dir=FAILED +first_param="$1" +for dir in $PATH +do + if test "$gettext_dir" = FAILED && test -f $dir/gettext \ + && ($dir/gettext --version >/dev/null 2>&1) + then + set `$dir/gettext --version 2>&1` + if test "$3" = GNU + then + gettext_dir=$dir + fi + fi + if test "$locale_dir" = FAILED && test -f $dir/shar \ + && ($dir/shar --print-text-domain-dir >/dev/null 2>&1) + then + locale_dir=`$dir/shar --print-text-domain-dir` + fi +done +IFS="$save_IFS" +if test "$locale_dir" = FAILED || test "$gettext_dir" = FAILED +then + echo=echo +else + TEXTDOMAINDIR=$locale_dir + export TEXTDOMAINDIR + TEXTDOMAIN=sharutils + export TEXTDOMAIN + echo="$gettext_dir/gettext -s" +fi +if touch -am -t 200112312359.59 $$.touch >/dev/null 2>&1 && test ! -f 200112312359.59 -a -f $$.touch; then + shar_touch='touch -am -t $1$2$3$4$5$6.$7 "$8"' +elif touch -am 123123592001.59 $$.touch >/dev/null 2>&1 && test ! -f 123123592001.59 -a ! -f 123123592001.5 -a -f $$.touch; then + shar_touch='touch -am $3$4$5$6$1$2.$7 "$8"' +elif touch -am 1231235901 $$.touch >/dev/null 2>&1 && test ! -f 1231235901 -a -f $$.touch; then + shar_touch='touch -am $3$4$5$6$2 "$8"' +else + shar_touch=: + echo + $echo 'WARNING: not restoring timestamps. Consider getting and' + $echo "installing GNU \`touch', distributed in GNU File Utilities..." + echo +fi +rm -f 200112312359.59 123123592001.59 123123592001.5 1231235901 $$.touch +# +if mkdir _sh17581; then + $echo 'x -' 'creating lock directory' +else + $echo 'failed to create lock directory' + exit 1 +fi +# ============= ip2mkdev ============== +if test -f 'ip2mkdev' && test "$first_param" != -c; then + $echo 'x -' SKIPPING 'ip2mkdev' '(file already exists)' +else + $echo 'x -' extracting 'ip2mkdev' '(text)' + sed 's/^X//' << 'SHAR_EOF' > 'ip2mkdev' && +#!/bin/sh - +# +# ip2mkdev +# +# Make or remove devices as needed for Computone Intelliport drivers +# +# First rule! If the dev file exists and you need it, don't mess +# with it. That prevents us from screwing up open ttys, ownership +# and permissions on a running system! +# +# This script will NOT remove devices that no longer exist if their +# board or interface box has been removed. If you want to get rid +# of them, you can manually do an "rm -f /dev/ttyF* /dev/cuaf*" +# before running this script. Running this script will then recreate +# all the valid devices. +# +# Michael H. Warfield +# /\/\|=mhw=|\/\/ +# mhw@wittsend.com +# +# Updated 10/29/2000 for version 1.2.13 naming convention +# under devfs. /\/\|=mhw=|\/\/ +# +# Updated 03/09/2000 for devfs support in ip2 drivers. /\/\|=mhw=|\/\/ +# +X +if test -d /dev/ip2 ; then +# This is devfs mode... We don't do anything except create symlinks +# from the real devices to the old names! +X cd /dev +X echo "Creating symbolic links to devfs devices" +X for i in `ls ip2` ; do +X if test ! -L ip2$i ; then +X # Remove it incase it wasn't a symlink (old device) +X rm -f ip2$i +X ln -s ip2/$i ip2$i +X fi +X done +X for i in `( cd tts ; ls F* )` ; do +X if test ! -L tty$i ; then +X # Remove it incase it wasn't a symlink (old device) +X rm -f tty$i +X ln -s tts/$i tty$i +X fi +X done +X for i in `( cd cua ; ls F* )` ; do +X DEVNUMBER=`expr $i : 'F\(.*\)'` +X if test ! -L cuf$DEVNUMBER ; then +X # Remove it incase it wasn't a symlink (old device) +X rm -f cuf$DEVNUMBER +X ln -s cua/$i cuf$DEVNUMBER +X fi +X done +X exit 0 +fi +X +if test ! -f /proc/tty/drivers +then +X echo "\ +Unable to check driver status. +Make sure proc file system is mounted." +X +X exit 255 +fi +X +if test ! -f /proc/tty/driver/ip2 +then +X echo "\ +Unable to locate ip2 proc file. +Attempting to load driver" +X +X if /sbin/insmod ip2 +X then +X if test ! -f /proc/tty/driver/ip2 +X then +X echo "\ +Unable to locate ip2 proc file after loading driver. +Driver initialization failure or driver version error. +" +X exit 255 +X fi +X else +X echo "Unable to load ip2 driver." +X exit 255 +X fi +fi +X +# Ok... So we got the driver loaded and we can locate the procfs files. +# Next we need our major numbers. +X +TTYMAJOR=`sed -e '/^ip2/!d' -e '/\/dev\/tt/!d' -e 's/.*tt[^ ]*[ ]*\([0-9]*\)[ ]*.*/\1/' < /proc/tty/drivers` +CUAMAJOR=`sed -e '/^ip2/!d' -e '/\/dev\/cu/!d' -e 's/.*cu[^ ]*[ ]*\([0-9]*\)[ ]*.*/\1/' < /proc/tty/drivers` +BRDMAJOR=`sed -e '/^Driver: /!d' -e 's/.*IMajor=\([0-9]*\)[ ]*.*/\1/' < /proc/tty/driver/ip2` +X +echo "\ +TTYMAJOR = $TTYMAJOR +CUAMAJOR = $CUAMAJOR +BRDMAJOR = $BRDMAJOR +" +X +# Ok... Now we should know our major numbers, if appropriate... +# Now we need our boards and start the device loops. +X +grep '^Board [0-9]:' /proc/tty/driver/ip2 | while read token number type alltherest +do +X # The test for blank "type" will catch the stats lead-in lines +X # if they exist in the file +X if test "$type" = "vacant" -o "$type" = "Vacant" -o "$type" = "" +X then +X continue +X fi +X +X BOARDNO=`expr "$number" : '\([0-9]\):'` +X PORTS=`expr "$alltherest" : '.*ports=\([0-9]*\)' | tr ',' ' '` +X MINORS=`expr "$alltherest" : '.*minors=\([0-9,]*\)' | tr ',' ' '` +X +X if test "$BOARDNO" = "" -o "$PORTS" = "" +X then +# This may be a bug. We should at least get this much information +X echo "Unable to process board line" +X continue +X fi +X +X if test "$MINORS" = "" +X then +# Silently skip this one. This board seems to have no boxes +X continue +X fi +X +X echo "board $BOARDNO: $type ports = $PORTS; port numbers = $MINORS" +X +X if test "$BRDMAJOR" != "" +X then +X BRDMINOR=`expr $BOARDNO \* 4` +X STSMINOR=`expr $BRDMINOR + 1` +X if test ! -c /dev/ip2ipl$BOARDNO ; then +X mknod /dev/ip2ipl$BOARDNO c $BRDMAJOR $BRDMINOR +X fi +X if test ! -c /dev/ip2stat$BOARDNO ; then +X mknod /dev/ip2stat$BOARDNO c $BRDMAJOR $STSMINOR +X fi +X fi +X +X if test "$TTYMAJOR" != "" +X then +X PORTNO=$BOARDBASE +X +X for PORTNO in $MINORS +X do +X if test ! -c /dev/ttyF$PORTNO ; then +X # We got the hardware but no device - make it +X mknod /dev/ttyF$PORTNO c $TTYMAJOR $PORTNO +X fi +X done +X fi +X +X if test "$CUAMAJOR" != "" +X then +X PORTNO=$BOARDBASE +X +X for PORTNO in $MINORS +X do +X if test ! -c /dev/cuf$PORTNO ; then +X # We got the hardware but no device - make it +X mknod /dev/cuf$PORTNO c $CUAMAJOR $PORTNO +X fi +X done +X fi +done +X +Xexit 0 +SHAR_EOF + (set 20 01 10 29 10 32 01 'ip2mkdev'; eval "$shar_touch") && + chmod 0755 'ip2mkdev' || + $echo 'restore of' 'ip2mkdev' 'failed' + if ( md5sum --help 2>&1 | grep 'sage: md5sum \[' ) >/dev/null 2>&1 \ + && ( md5sum --version 2>&1 | grep -v 'textutils 1.12' ) >/dev/null; then + md5sum -c << SHAR_EOF >/dev/null 2>&1 \ + || $echo 'ip2mkdev:' 'MD5 check failed' +cb5717134509f38bad9fde6b1f79b4a4 ip2mkdev +SHAR_EOF + else + shar_count="`LC_ALL= LC_CTYPE= LANG= wc -c < 'ip2mkdev'`" + test 4251 -eq "$shar_count" || + $echo 'ip2mkdev:' 'original size' '4251,' 'current size' "$shar_count!" + fi +fi +rm -fr _sh17581 +exit 0 diff --git a/trunk/Documentation/sysctl/vm.txt b/trunk/Documentation/sysctl/vm.txt index 078701fdbd4d..dcc2a94ae34e 100644 --- a/trunk/Documentation/sysctl/vm.txt +++ b/trunk/Documentation/sysctl/vm.txt @@ -76,8 +76,8 @@ huge pages although processes will also directly compact memory as required. dirty_background_bytes -Contains the amount of dirty memory at which the background kernel -flusher threads will start writeback. +Contains the amount of dirty memory at which the pdflush background writeback +daemon will start writeback. Note: dirty_background_bytes is the counterpart of dirty_background_ratio. Only one of them may be specified at a time. When one sysctl is written it is @@ -89,7 +89,7 @@ other appears as 0 when read. dirty_background_ratio Contains, as a percentage of total system memory, the number of pages at which -the background kernel flusher threads will start writing out dirty data. +the pdflush background writeback daemon will start writing out dirty data. ============================================================== @@ -112,9 +112,9 @@ retained. dirty_expire_centisecs This tunable is used to define when dirty data is old enough to be eligible -for writeout by the kernel flusher threads. It is expressed in 100'ths -of a second. Data which has been dirty in-memory for longer than this -interval will be written out next time a flusher thread wakes up. +for writeout by the pdflush daemons. It is expressed in 100'ths of a second. +Data which has been dirty in-memory for longer than this interval will be +written out next time a pdflush daemon wakes up. ============================================================== @@ -128,7 +128,7 @@ data. dirty_writeback_centisecs -The kernel flusher threads will periodically wake up and write `old' data +The pdflush writeback daemons will periodically wake up and write `old' data out to disk. This tunable expresses the interval between those wakeups, in 100'ths of a second. diff --git a/trunk/Documentation/trace/kprobetrace.txt b/trunk/Documentation/trace/kprobetrace.txt index d68ea5fc812b..d0d0bb9e3e25 100644 --- a/trunk/Documentation/trace/kprobetrace.txt +++ b/trunk/Documentation/trace/kprobetrace.txt @@ -12,7 +12,7 @@ kprobes can probe (this means, all functions body except for __kprobes functions). Unlike the Tracepoint based event, this can be added and removed dynamically, on the fly. -To enable this feature, build your kernel with CONFIG_KPROBE_EVENT=y. +To enable this feature, build your kernel with CONFIG_KPROBE_TRACING=y. Similar to the events tracer, this doesn't need to be activated via current_tracer. Instead of that, add probe points via diff --git a/trunk/Documentation/usb/persist.txt b/trunk/Documentation/usb/persist.txt index 35d70eda9ad6..074b159b77c2 100644 --- a/trunk/Documentation/usb/persist.txt +++ b/trunk/Documentation/usb/persist.txt @@ -155,9 +155,6 @@ If the kernel gets fooled in this way, it's almost certain to cause data corruption and to crash your system. You'll have no one to blame but yourself. -For those devices with avoid_reset_quirk attribute being set, persist -maybe fail because they may morph after reset. - YOU HAVE BEEN WARNED! USE AT YOUR OWN RISK! That having been said, most of the time there shouldn't be any trouble diff --git a/trunk/Documentation/vfio.txt b/trunk/Documentation/vfio.txt index 8eda3635a17d..0cb6685c8029 100644 --- a/trunk/Documentation/vfio.txt +++ b/trunk/Documentation/vfio.txt @@ -133,7 +133,7 @@ character devices for this group: $ lspci -n -s 0000:06:0d.0 06:0d.0 0401: 1102:0002 (rev 08) # echo 0000:06:0d.0 > /sys/bus/pci/devices/0000:06:0d.0/driver/unbind -# echo 1102 0002 > /sys/bus/pci/drivers/vfio-pci/new_id +# echo 1102 0002 > /sys/bus/pci/drivers/vfio/new_id Now we need to look at what other devices are in the group to free it for use by VFIO: diff --git a/trunk/Documentation/vm/hugetlbpage.txt b/trunk/Documentation/vm/hugetlbpage.txt index 4ac359b7aa17..f8551b3879f8 100644 --- a/trunk/Documentation/vm/hugetlbpage.txt +++ b/trunk/Documentation/vm/hugetlbpage.txt @@ -299,17 +299,11 @@ map_hugetlb.c. ******************************************************************* /* - * map_hugetlb: see tools/testing/selftests/vm/map_hugetlb.c + * hugepage-shm: see Documentation/vm/hugepage-shm.c */ ******************************************************************* /* - * hugepage-shm: see tools/testing/selftests/vm/hugepage-shm.c - */ - -******************************************************************* - -/* - * hugepage-mmap: see tools/testing/selftests/vm/hugepage-mmap.c + * hugepage-mmap: see Documentation/vm/hugepage-mmap.c */ diff --git a/trunk/Documentation/w1/slaves/w1_therm b/trunk/Documentation/w1/slaves/w1_therm index 874a8ca93feb..0403aaaba878 100644 --- a/trunk/Documentation/w1/slaves/w1_therm +++ b/trunk/Documentation/w1/slaves/w1_therm @@ -3,7 +3,6 @@ Kernel driver w1_therm Supported chips: * Maxim ds18*20 based temperature sensors. - * Maxim ds1825 based temperature sensors. Author: Evgeniy Polyakov @@ -16,7 +15,6 @@ supported family codes: W1_THERM_DS18S20 0x10 W1_THERM_DS1822 0x22 W1_THERM_DS18B20 0x28 -W1_THERM_DS1825 0x3B Support is provided through the sysfs w1_slave file. Each open and read sequence will initiate a temperature conversion then provide two diff --git a/trunk/Documentation/watchdog/src/watchdog-test.c b/trunk/Documentation/watchdog/src/watchdog-test.c index 3da822967ee0..73ff5cc93e05 100644 --- a/trunk/Documentation/watchdog/src/watchdog-test.c +++ b/trunk/Documentation/watchdog/src/watchdog-test.c @@ -31,7 +31,7 @@ static void keep_alive(void) * or "-e" to enable the card. */ -static void term(int sig) +void term(int sig) { close(fd); fprintf(stderr, "Stopping watchdog ticks...\n"); diff --git a/trunk/Documentation/x86/x86_64/boot-options.txt b/trunk/Documentation/x86/x86_64/boot-options.txt index de38429beb71..c54b4f503e2a 100644 --- a/trunk/Documentation/x86/x86_64/boot-options.txt +++ b/trunk/Documentation/x86/x86_64/boot-options.txt @@ -50,13 +50,6 @@ Machine check monarchtimeout: Sets the time in us to wait for other CPUs on machine checks. 0 to disable. - mce=bios_cmci_threshold - Don't overwrite the bios-set CMCI threshold. This boot option - prevents Linux from overwriting the CMCI threshold set by the - bios. Without this option, Linux always sets the CMCI - threshold to 1. Enabling this may make memory predictive failure - analysis less effective if the bios sets thresholds for memory - errors since we will not see details for all errors. nomce (for compatibility with i386): same as mce=off diff --git a/trunk/Documentation/zh_CN/arm/Booting b/trunk/Documentation/zh_CN/arm/Booting deleted file mode 100644 index 6158a64df80c..000000000000 --- a/trunk/Documentation/zh_CN/arm/Booting +++ /dev/null @@ -1,175 +0,0 @@ -Chinese translated version of Documentation/arm/Booting - -If you have any comment or update to the content, please contact the -original document maintainer directly. However, if you have a problem -communicating in English you can also ask the Chinese maintainer for -help. Contact the Chinese maintainer if this translation is outdated -or if there is a problem with the translation. - -Maintainer: Russell King -Chinese maintainer: Fu Wei ---------------------------------------------------------------------- -Documentation/arm/Booting 的中文翻译 - -如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 -交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 -译存在问题，请联系中文版维护者。 - -英文版维护者： Russell King -中文版维护者： 傅炜 Fu Wei -中文版翻译者： 傅炜 Fu Wei -中文版校译者： 傅炜 Fu Wei - -以下为正文 ---------------------------------------------------------------------- - - 启动 ARM Linux - ============== - -作者：Russell King -日期：2002年5月18日 - -以下文档适用于 2.4.18-rmk6 及以上版本。 - -为了启动 ARM Linux，你需要一个引导装载程序（boot loader）， -它是一个在主内核启动前运行的一个小程序。引导装载程序需要初始化各种 -设备，并最终调用 Linux 内核，将信息传递给内核。 - -从本质上讲，引导装载程序应提供（至少）以下功能： - -1、设置和初始化 RAM。 -2、初始化一个串口。 -3、检测机器的类型（machine type）。 -4、设置内核标签列表（tagged list）。 -5、调用内核映像。 - - -1、设置和初始化 RAM -------------------- - -现有的引导加载程序: 强制 -新开发的引导加载程序: 强制 - -引导装载程序应该找到并初始化系统中所有内核用于保持系统变量数据的 RAM。 -这个操作的执行是设备依赖的。（它可能使用内部算法来自动定位和计算所有 -RAM，或可能使用对这个设备已知的 RAM 信息，还可能使用任何引导装载程序 -设计者想到的匹配方法。） - - -2、初始化一个串口 ------------------------------ - -现有的引导加载程序: 可选、建议 -新开发的引导加载程序: 可选、建议 - -引导加载程序应该初始化并使能一个目标板上的串口。这允许内核串口驱动 -自动检测哪个串口用于内核控制台。(一般用于调试或与目标板通信。) - -作为替代方案，引导加载程序也可以通过标签列表传递相关的'console=' -选项给内核以指定某个串口，而串口数据格式的选项在以下文档中描述： - - Documentation/kernel-parameters.txt。 - - -3、检测机器类型 --------------------------- - -现有的引导加载程序: 可选 -新开发的引导加载程序: 强制 - -引导加载程序应该通过某些方式检测自身所处的机器类型。这是一个硬件 -代码或通过查看所连接的硬件用某些算法得到，这些超出了本文档的范围。 -引导加载程序最终必须能提供一个 MACH_TYPE_xxx 值给内核。 -(详见 linux/arch/arm/tools/mach-types )。 - -4、设置启动数据 ------------------- - -现有的引导加载程序: 可选、强烈建议 -新开发的引导加载程序: 强制 - -引导加载程序必须提供标签列表或者 dtb 映像以传递配置数据给内核。启动 -数据的物理地址通过寄存器 r2 传递给内核。 - -4a、设置内核标签列表 --------------------------------- - -bootloader 必须创建和初始化内核标签列表。一个有效的标签列表以 -ATAG_CORE 标签开始，并以 ATAG_NONE 标签结束。ATAG_CORE 标签可以是 -空的，也可以是非空。一个空 ATAG_CORE 标签其 size 域设置为 -‘2’(0x00000002)。ATAG_NONE 标签的 size 域必须设置为零。 - -在列表中可以保存任意数量的标签。对于一个重复的标签是追加到之前标签 -所携带的信息之后，还是会覆盖原来的信息，是未定义的。某些标签的行为 -是前者，其他是后者。 - -bootloader 必须传递一个系统内存的位置和最小值，以及根文件系统位置。 -因此，最小的标签列表如下所示： - - +-----------+ -基地址 -> | ATAG_CORE | | - +-----------+ | - | ATAG_MEM | | 地址增长方向 - +-----------+ | - | ATAG_NONE | | - +-----------+ v - -标签列表应该保存在系统的 RAM 中。 - -标签列表必须置于内核自解压和 initrd'bootp' 程序都不会覆盖的内存区。 -建议放在 RAM 的头 16KiB 中。 - -4b、设置设备树 -------------------------- - -bootloader 必须以 64bit 地址对齐的形式加载一个设备树映像(dtb)到系统 -RAM 中，并用启动数据初始化它。dtb 格式在文档 -Documentation/devicetree/booting-without-of.txt 中。内核将会在 -dtb 物理地址处查找 dtb 魔数值（0xd00dfeed），以确定 dtb 是否已经代替 -标签列表被传递进来。 - -bootloader 必须传递一个系统内存的位置和最小值，以及根文件系统位置。 -dtb 必须置于内核自解压不会覆盖的内存区。建议将其放置于 RAM 的头 16KiB -中。但是不可将其放置于“0”物理地址处，因为内核认为：r2 中为 0，意味着 -没有标签列表和 dtb 传递过来。 - -5、调用内核映像 ---------------------------- - -现有的引导加载程序: 强制 -新开发的引导加载程序: 强制 - -调用内核映像 zImage 有两个选择。如果 zImge 保存在 flash 中，且是为了 -在 flash 中直接运行而被正确链接的。这样引导加载程序就可以在 flash 中 -直接调用 zImage。 - -zImage 也可以被放在系统 RAM（任意位置）中被调用。注意：内核使用映像 -基地址的前 16KB RAM 空间来保存页表。建议将映像置于 RAM 的 32KB 处。 - -对于以上任意一种情况，都必须符合以下启动状态： - -- 停止所有 DMA 设备，这样内存数据就不会因为虚假网络包或磁盘数据而被破坏。 - 这可能可以节省你许多的调试时间。 - -- CPU 寄存器配置 - r0 = 0， - r1 = （在上面 3 中获取的）机器类型码。 - r2 = 标签列表在系统 RAM 中的物理地址，或 - 设备树块(dtb)在系统 RAM 中的物理地址 - -- CPU 模式 - 所有形式的中断必须被禁止 (IRQs 和 FIQs) - CPU 必须处于 SVC 模式。(对于 Angel 调试有特例存在) - -- 缓存，MMUs - MMU 必须关闭。 - 指令缓存开启或关闭都可以。 - 数据缓存必须关闭。 - -- 引导加载程序应该通过直接跳转到内核映像的第一条指令来调用内核映像。 - - 对于支持 ARM 指令集的 CPU，跳入内核入口时必须处在 ARM 状态，即使 - 对于 Thumb-2 内核也是如此。 - - 对于仅支持 Thumb 指令集的 CPU，比如 Cortex-M 系列的 CPU，跳入 - 内核入口时必须处于 Thumb 状态。 diff --git a/trunk/Documentation/zh_CN/basic_profiling.txt b/trunk/Documentation/zh_CN/basic_profiling.txt deleted file mode 100644 index 1e6bf0bdf8f5..000000000000 --- a/trunk/Documentation/zh_CN/basic_profiling.txt +++ /dev/null @@ -1,71 +0,0 @@ -Chinese translated version of Documentation/basic_profiling - -If you have any comment or update to the content, please post to LKML directly. -However, if you have problem communicating in English you can also ask the -Chinese maintainer for help. Contact the Chinese maintainer, if this -translation is outdated or there is problem with translation. - -Chinese maintainer: Liang Xie ---------------------------------------------------------------------- -Documentation/basic_profiling的中文翻译 - -如果想评论或更新本文的内容，请直接发信到LKML。如果你使用英文交流有困难的话，也可 -以向中文版维护者求助。如果本翻译更新不及时或者翻译存在问题，请联系中文版维护者。 - -中文版维护者： 谢良 Liang Xie -中文版翻译者： 谢良 Liang Xie -中文版校译者： -以下为正文 ---------------------------------------------------------------------- - -下面这些说明指令都是非常基础的，如果你想进一步了解请阅读相关专业文档：） -请不要再在本文档增加新的内容，但可以修复文档中的错误：）(mbligh@aracnet.com) -感谢John Levon，Dave Hansen等在撰写时的帮助 - - 用于表示要测量的目标 -请先确保您已经有正确的System.map / vmlinux配置！ - -对于linux系统来说，配置vmlinuz最容易的方法可能就是使用“make install”，然后修改 -/sbin/installkernel将vmlinux拷贝到/boot目录，而System.map通常是默认安装好的 - -Readprofile ------------ -2.6系列内核需要版本相对较新的readprofile，比如util-linux 2.12a中包含的，可以从: - -http://www.kernel.org/pub/linux/utils/util-linux/ 下载 - -大部分linux发行版已经包含了. - -启用readprofile需要在kernel启动命令行增加”profile=2“ - -clear readprofile -r - -dump output readprofile -m /boot/System.map > captured_profile - -Oprofile --------- - -从http://oprofile.sourceforge.net/获取源代码（请参考Changes以获取匹配的版本） -在kernel启动命令行增加“idle=poll” - -配置CONFIG_PROFILING=y和CONFIG_OPROFILE=y然后重启进入新kernel - -./configure --with-kernel-support -make install - -想得到好的测量结果，请确保启用了本地APIC特性。如果opreport显示有0Hz CPU， -说明APIC特性没有开启。另外注意idle=poll选项可能有损性能。 - -One time setup: - opcontrol --setup --vmlinux=/boot/vmlinux - -clear opcontrol --reset -start opcontrol --start - -stop opcontrol --stop -dump output opreport > output_file - -如果只看kernel相关的报告结果，请运行命令 opreport -l /boot/vmlinux > output_file - -通过reset选项可以清理过期统计数据，相当于重启的效果。 - diff --git a/trunk/Documentation/zh_CN/filesystems/sysfs.txt b/trunk/Documentation/zh_CN/filesystems/sysfs.txt deleted file mode 100644 index e230eaa33122..000000000000 --- a/trunk/Documentation/zh_CN/filesystems/sysfs.txt +++ /dev/null @@ -1,372 +0,0 @@ -Chinese translated version of Documentation/filesystems/sysfs.txt - -If you have any comment or update to the content, please contact the -original document maintainer directly. However, if you have a problem -communicating in English you can also ask the Chinese maintainer for -help. Contact the Chinese maintainer if this translation is outdated -or if there is a problem with the translation. - -Maintainer: Patrick Mochel - Mike Murphy -Chinese maintainer: Fu Wei ---------------------------------------------------------------------- -Documentation/filesystems/sysfs.txt 的中文翻译 - -如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 -交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 -译存在问题，请联系中文版维护者。 -英文版维护者： Patrick Mochel - Mike Murphy -中文版维护者： 傅炜 Fu Wei -中文版翻译者： 傅炜 Fu Wei -中文版校译者： 傅炜 Fu Wei - - -以下为正文 ---------------------------------------------------------------------- -sysfs - 用于导出内核对象(kobject)的文件系统 - -Patrick Mochel -Mike Murphy - -修订: 16 August 2011 -原始版本: 10 January 2003 - - -sysfs 简介: -~~~~~~~~~~ - -sysfs 是一个最初基于 ramfs 且位于内存的文件系统。它提供导出内核 -数据结构及其属性，以及它们之间的关联到用户空间的方法。 - -sysfs 始终与 kobject 的底层结构紧密相关。请阅读 -Documentation/kobject.txt 文档以获得更多关于 kobject 接口的 -信息。 - - -使用 sysfs -~~~~~~~~~~~ - -只要内核配置中定义了 CONFIG_SYSFS ，sysfs 总是被编译进内核。你可 -通过以下命令挂载它: - - mount -t sysfs sysfs /sys - - -创建目录 -~~~~~~~~ - -任何 kobject 在系统中注册，就会有一个目录在 sysfs 中被创建。这个 -目录是作为该 kobject 的父对象所在目录的子目录创建的，以准确地传递 -内核的对象层次到用户空间。sysfs 中的顶层目录代表着内核对象层次的 -共同祖先；例如：某些对象属于某个子系统。 - -Sysfs 在与其目录关联的 sysfs_dirent 对象中内部保存一个指向实现 -目录的 kobject 的指针。以前，这个 kobject 指针被 sysfs 直接用于 -kobject 文件打开和关闭的引用计数。而现在的 sysfs 实现中，kobject -引用计数只能通过 sysfs_schedule_callback() 函数直接修改。 - - -属性 -~~~~ - -kobject 的属性可在文件系统中以普通文件的形式导出。Sysfs 为属性定义 -了面向文件 I/O 操作的方法，以提供对内核属性的读写。 - - -属性应为 ASCII 码文本文件。以一个文件只存储一个属性值为宜。但一个 -文件只包含一个属性值可能影响效率，所以一个包含相同数据类型的属性值 -数组也被广泛地接受。 - -混合类型、表达多行数据以及一些怪异的数据格式会遭到强烈反对。这样做是 -很丢脸的,而且其代码会在未通知作者的情况下被重写。 - - -一个简单的属性结构定义如下: - -struct attribute { - char * name; - struct module *owner; - umode_t mode; -}; - - -int sysfs_create_file(struct kobject * kobj, const struct attribute * attr); -void sysfs_remove_file(struct kobject * kobj, const struct attribute * attr); - - -一个单独的属性结构并不包含读写其属性值的方法。子系统最好为增删特定 -对象类型的属性定义自己的属性结构体和封装函数。 - -例如:驱动程序模型定义的 device_attribute 结构体如下: - -struct device_attribute { - struct attribute attr; - ssize_t (*show)(struct device *dev, struct device_attribute *attr, - char *buf); - ssize_t (*store)(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count); -}; - -int device_create_file(struct device *, const struct device_attribute *); -void device_remove_file(struct device *, const struct device_attribute *); - -为了定义设备属性，同时定义了一下辅助宏: - -#define DEVICE_ATTR(_name, _mode, _show, _store) \ -struct device_attribute dev_attr_##_name = __ATTR(_name, _mode, _show, _store) - -例如:声明 - -static DEVICE_ATTR(foo, S_IWUSR | S_IRUGO, show_foo, store_foo); - -等同于如下代码： - -static struct device_attribute dev_attr_foo = { - .attr = { - .name = "foo", - .mode = S_IWUSR | S_IRUGO, - .show = show_foo, - .store = store_foo, - }, -}; - - -子系统特有的回调函数 -~~~~~~~~~~~~~~~~~~~ - -当一个子系统定义一个新的属性类型时，必须实现一系列的 sysfs 操作， -以帮助读写调用实现属性所有者的显示和储存方法。 - -struct sysfs_ops { - ssize_t (*show)(struct kobject *, struct attribute *, char *); - ssize_t (*store)(struct kobject *, struct attribute *, const char *, size_t); -}; - -[子系统应已经定义了一个 struct kobj_type 结构体作为这个类型的 -描述符，并在此保存 sysfs_ops 的指针。更多的信息参见 kobject 的 -文档] - -sysfs 会为这个类型调用适当的方法。当一个文件被读写时，这个方法会 -将一般的kobject 和 attribute 结构体指针转换为适当的指针类型后 -调用相关联的函数。 - - -示例: - -#define to_dev(obj) container_of(obj, struct device, kobj) -#define to_dev_attr(_attr) container_of(_attr, struct device_attribute, attr) - -static ssize_t dev_attr_show(struct kobject *kobj, struct attribute *attr, - char *buf) -{ - struct device_attribute *dev_attr = to_dev_attr(attr); - struct device *dev = to_dev(kobj); - ssize_t ret = -EIO; - - if (dev_attr->show) - ret = dev_attr->show(dev, dev_attr, buf); - if (ret >= (ssize_t)PAGE_SIZE) { - print_symbol("dev_attr_show: %s returned bad count\n", - (unsigned long)dev_attr->show); - } - return ret; -} - - - -读写属性数据 -~~~~~~~~~~~~ - -在声明属性时，必须指定 show() 或 store() 方法，以实现属性的 -读或写。这些方法的类型应该和以下的设备属性定义一样简单。 - -ssize_t (*show)(struct device *dev, struct device_attribute *attr, char *buf); -ssize_t (*store)(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count); - -也就是说,他们应只以一个处理对象、一个属性和一个缓冲指针作为参数。 - -sysfs 会分配一个大小为 (PAGE_SIZE) 的缓冲区并传递给这个方法。 -Sysfs 将会为每次读写操作调用一次这个方法。这使得这些方法在执行时 -会出现以下的行为: - -- 在读方面（read(2)），show() 方法应该填充整个缓冲区。回想属性 - 应只导出了一个属性值或是一个同类型属性值的数组，所以这个代价将 - 不会不太高。 - - 这使得用户空间可以局部地读和任意的向前搜索整个文件。如果用户空间 - 向后搜索到零或使用‘0’偏移执行一个pread(2)操作，show()方法将 - 再次被调用，以重新填充缓存。 - -- 在写方面（write(2)），sysfs 希望在第一次写操作时得到整个缓冲区。 - 之后 Sysfs 传递整个缓冲区给 store() 方法。 - - 当要写 sysfs 文件时，用户空间进程应首先读取整个文件，修该想要 - 改变的值，然后回写整个缓冲区。 - - 在读写属性值时，属性方法的执行应操作相同的缓冲区。 - -注记: - -- 写操作导致的 show() 方法重载，会忽略当前文件位置。 - -- 缓冲区应总是 PAGE_SIZE 大小。对于i386，这个值为4096。 - -- show() 方法应该返回写入缓冲区的字节数，也就是 snprintf()的 - 返回值。 - -- show() 应始终使用 snprintf()。 - -- store() 应返回缓冲区的已用字节数。如果整个缓存都已填满，只需返回 - count 参数。 - -- show() 或 store() 可以返回错误值。当得到一个非法值，必须返回一个 - 错误值。 - -- 一个传递给方法的对象将会通过 sysfs 调用对象内嵌的引用计数固定在 - 内存中。尽管如此，对象代表的物理实体(如设备)可能已不存在。如有必要， - 应该实现一个检测机制。 - -一个简单的(未经实验证实的)设备属性实现如下： - -static ssize_t show_name(struct device *dev, struct device_attribute *attr, - char *buf) -{ - return scnprintf(buf, PAGE_SIZE, "%s\n", dev->name); -} - -static ssize_t store_name(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count) -{ - snprintf(dev->name, sizeof(dev->name), "%.*s", - (int)min(count, sizeof(dev->name) - 1), buf); - return count; -} - -static DEVICE_ATTR(name, S_IRUGO, show_name, store_name); - - -（注意：真正的实现不允许用户空间设置设备名。） - -顶层目录布局 -~~~~~~~~~~~~ - -sysfs 目录的安排显示了内核数据结构之间的关系。 - -顶层 sysfs 目录如下: - -block/ -bus/ -class/ -dev/ -devices/ -firmware/ -net/ -fs/ - -devices/ 包含了一个设备树的文件系统表示。他直接映射了内部的内核 -设备树，反映了设备的层次结构。 - -bus/ 包含了内核中各种总线类型的平面目录布局。每个总线目录包含两个 -子目录: - - devices/ - drivers/ - -devices/ 包含了系统中出现的每个设备的符号链接，他们指向 root/ 下的 -设备目录。 - -drivers/ 包含了每个已为特定总线上的设备而挂载的驱动程序的目录(这里 -假定驱动没有跨越多个总线类型)。 - -fs/ 包含了一个为文件系统设立的目录。现在每个想要导出属性的文件系统必须 -在 fs/ 下创建自己的层次结构(参见Documentation/filesystems/fuse.txt)。 - -dev/ 包含两个子目录： char/ 和 block/。在这两个子目录中，有以 -: 格式命名的符号链接。这些符号链接指向 sysfs 目录 -中相应的设备。/sys/dev 提供一个通过一个 stat(2) 操作结果，查找 -设备 sysfs 接口快捷的方法。 - -更多有关 driver-model 的特性信息可以在 Documentation/driver-model/ -中找到。 - - -TODO: 完成这一节。 - - -当前接口 -~~~~~~~~ - -以下的接口层普遍存在于当前的sysfs中: - -- 设备 (include/linux/device.h) ----------------------------------- -结构体: - -struct device_attribute { - struct attribute attr; - ssize_t (*show)(struct device *dev, struct device_attribute *attr, - char *buf); - ssize_t (*store)(struct device *dev, struct device_attribute *attr, - const char *buf, size_t count); -}; - -声明: - -DEVICE_ATTR(_name, _mode, _show, _store); - -增/删属性: - -int device_create_file(struct device *dev, const struct device_attribute * attr); -void device_remove_file(struct device *dev, const struct device_attribute * attr); - - -- 总线驱动程序 (include/linux/device.h) --------------------------------------- -结构体: - -struct bus_attribute { - struct attribute attr; - ssize_t (*show)(struct bus_type *, char * buf); - ssize_t (*store)(struct bus_type *, const char * buf, size_t count); -}; - -声明: - -BUS_ATTR(_name, _mode, _show, _store) - -增/删属性: - -int bus_create_file(struct bus_type *, struct bus_attribute *); -void bus_remove_file(struct bus_type *, struct bus_attribute *); - - -- 设备驱动程序 (include/linux/device.h) ------------------------------------------ - -结构体: - -struct driver_attribute { - struct attribute attr; - ssize_t (*show)(struct device_driver *, char * buf); - ssize_t (*store)(struct device_driver *, const char * buf, - size_t count); -}; - -声明: - -DRIVER_ATTR(_name, _mode, _show, _store) - -增/删属性： - -int driver_create_file(struct device_driver *, const struct driver_attribute *); -void driver_remove_file(struct device_driver *, const struct driver_attribute *); - - -文档 -~~~~ - -sysfs 目录结构以及其中包含的属性定义了一个内核与用户空间之间的 ABI。 -对于任何 ABI，其自身的稳定和适当的文档是非常重要的。所有新的 sysfs -属性必须在 Documentation/ABI 中有文档。详见 Documentation/ABI/README。 diff --git a/trunk/Documentation/zh_CN/gpio.txt b/trunk/Documentation/zh_CN/gpio.txt deleted file mode 100644 index 4fa7b4e6f856..000000000000 --- a/trunk/Documentation/zh_CN/gpio.txt +++ /dev/null @@ -1,658 +0,0 @@ -Chinese translated version of Documentation/gpio.txt - -If you have any comment or update to the content, please contact the -original document maintainer directly. However, if you have a problem -communicating in English you can also ask the Chinese maintainer for -help. Contact the Chinese maintainer if this translation is outdated -or if there is a problem with the translation. - -Maintainer: Grant Likely - Linus Walleij -Chinese maintainer: Fu Wei ---------------------------------------------------------------------- -Documentation/gpio.txt 的中文翻译 - -如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 -交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 -译存在问题，请联系中文版维护者。 -英文版维护者： Grant Likely - Linus Walleij -中文版维护者： 傅炜 Fu Wei -中文版翻译者： 傅炜 Fu Wei -中文版校译者： 傅炜 Fu Wei - - -以下为正文 ---------------------------------------------------------------------- -GPIO 接口 - -本文档提供了一个在Linux下访问GPIO的公约概述。 - -这些函数以 gpio_* 作为前缀。其他的函数不允许使用这样的前缀或相关的 -__gpio_* 前缀。 - - -什么是GPIO? -========== -"通用输入/输出口"(GPIO)是一个灵活的由软件控制的数字信号。他们可 -由多种芯片提供,且对于从事嵌入式和定制硬件的 Linux 开发者来说是 -比较熟悉。每个GPIO 都代表一个连接到特定引脚或球栅阵列(BGA)封装中 -“球珠”的一个位。电路板原理图显示了 GPIO 与外部硬件的连接关系。 -驱动可以编写成通用代码，以使板级启动代码可传递引脚配置数据给驱动。 - -片上系统 (SOC) 处理器对 GPIO 有很大的依赖。在某些情况下,每个 -非专用引脚都可配置为 GPIO,且大多数芯片都最少有一些 GPIO。 -可编程逻辑器件(类似 FPGA) 可以方便地提供 GPIO。像电源管理和 -音频编解码器这样的多功能芯片经常留有一些这样的引脚来帮助那些引脚 -匮乏的 SOC。同时还有通过 I2C 或 SPI 串行总线连接的“GPIO扩展器” -芯片。大多数 PC 的南桥有一些拥有 GPIO 能力的引脚 (只有BIOS -固件才知道如何使用他们)。 - -GPIO 的实际功能因系统而异。通常用法有: - - - 输出值可写 (高电平=1，低电平=0)。一些芯片也有如何驱动这些值的选项, - 例如只允许输出一个值、支持“线与”及其他取值类似的模式(值得注意的是 - “开漏”信号) - - - 输入值可读(1、0)。一些芯片支持引脚在配置为“输出”时回读，这对于类似 - “线与”的情况(以支持双向信号)是非常有用的。GPIO 控制器可能有输入 - 去毛刺/消抖逻辑,这有时需要软件控制。 - - - 输入通常可作为 IRQ 信号,一般是沿触发,但有时是电平触发。这样的 IRQ - 可能配置为系统唤醒事件,以将系统从低功耗状态下唤醒。 - - - 通常一个 GPIO 根据不同产品电路板的需求,可以配置为输入或输出,也有仅 - 支持单向的。 - - - 大部分 GPIO 可以在持有自旋锁时访问,但是通常由串行总线扩展的 GPIO - 不允许持有自旋锁。但某些系统也支持这种类型。 - -对于给定的电路板,每个 GPIO 都用于某个特定的目的,如监控 MMC/SD 卡的 -插入/移除、检测卡的写保护状态、驱动 LED、配置收发器、模拟串行总线、 -复位硬件看门狗、感知开关状态等等。 - - -GPIO 公约 -========= -注意,这个叫做“公约”，因为这不是强制性的，不遵循这个公约是无伤大雅的， -因为此时可移植性并不重要。GPIO 常用于板级特定的电路逻辑,甚至可能 -随着电路板的版本而改变，且不可能在不同走线的电路板上使用。仅有在少数 -功能上才具有可移植性，其他功能是平台特定。这也是由于“胶合”的逻辑造成的。 - -此外，这不需要任何的执行框架，只是一个接口。某个平台可能通过一个简单地 -访问芯片寄存器的内联函数来实现它，其他平台可能通过委托一系列不同的GPIO -控制器的抽象函数来实现它。(有一些可选的代码能支持这种策略的实现,本文档 -后面会介绍，但作为 GPIO 接口的客户端驱动程序必须与它的实现无关。) - -也就是说,如果在他们的平台上支持这个公约，驱动应尽可能的使用它。平台 -必须在 Kconfig 中声明对 GENERIC_GPIO的支持 (布尔型 true)，并提供 -一个 文件。那些调用标准 GPIO 函数的驱动应该在 Kconfig -入口中声明依赖GENERIC_GPIO。当驱动包含文件: - - #include - -则 GPIO 函数是可用,无论是“真实代码”还是经优化过的语句。如果你遵守 -这个公约，当你的代码完成后，对其他的开发者来说会更容易看懂和维护。 - -注意，这些操作包含所用平台的 I/O 屏障代码，驱动无须显式地调用他们。 - - -标识 GPIO ---------- -GPIO 是通过无符号整型来标识的,范围是 0 到 MAX_INT。保留“负”数 -用于其他目的,例如标识信号“在这个板子上不可用”或指示错误。未接触底层 -硬件的代码会忽略这些整数。 - -平台会定义这些整数的用法,且通常使用 #define 来定义 GPIO，这样 -板级特定的启动代码可以直接关联相应的原理图。相对来说，驱动应该仅使用 -启动代码传递过来的 GPIO 编号，使用 platform_data 保存板级特定 -引脚配置数据 (同时还有其他须要的板级特定数据)，避免可能出现的问题。 - -例如一个平台使用编号 32-159 来标识 GPIO,而在另一个平台使用编号0-63 -标识一组 GPIO 控制器,64-79标识另一类 GPIO 控制器,且在一个含有 -FPGA 的特定板子上使用 80-95。编号不一定要连续,那些平台中，也可以 -使用编号2000-2063来标识一个 I2C 接口的 GPIO 扩展器中的 GPIO。 - -如果你要初始化一个带有无效 GPIO 编号的结构体,可以使用一些负编码 -(如"-EINVAL")，那将使其永远不会是有效。来测试这样一个结构体中的编号 -是否关联一个 GPIO，你可使用以下断言: - - int gpio_is_valid(int number); - -如果编号不存在，则请求和释放 GPIO 的函数将拒绝执行相关操作(见下文)。 -其他编号也可能被拒绝,比如一个编号可能存在，但暂时在给定的电路上不可用。 - -一个平台是否支持多个 GPIO 控制器为平台特定的实现问题，就像是否可以 -在 GPIO 编号空间中有“空洞”和是否可以在运行时添加新的控制器一样。 -这些问题会影响其他事情，包括相邻的 GPIO 编号是否存在等。 - -使用 GPIO ---------- -对于一个 GPIO，系统应该做的第一件事情就是通过 gpio_request() -函数分配它，见下文。 - -接下来是设置I/O方向，这通常是在板级启动代码中为所使用的 GPIO 设置 -platform_device 时完成。 - - /* 设置为输入或输出, 返回 0 或负的错误代码 */ - int gpio_direction_input(unsigned gpio); - int gpio_direction_output(unsigned gpio, int value); - -返回值为零代表成功，否则返回一个负的错误代码。这个返回值需要检查，因为 -get/set(获取/设置)函数调用没法返回错误,且有可能是配置错误。通常， -你应该在进程上下文中调用这些函数。然而,对于自旋锁安全的 GPIO，在板子 -启动的早期、进程启动前使用他们也是可以的。 - -对于作为输出的 GPIO，为其提供初始输出值，对于避免在系统启动期间出现 -信号毛刺是很有帮助的。 - -为了与传统的 GPIO 接口兼容, 在设置一个 GPIO 方向时，如果它还未被申请， -则隐含了申请那个 GPIO 的操作(见下文)。这种兼容性正在从可选的 gpiolib -框架中移除。 - -如果这个 GPIO 编码不存在，或者特定的 GPIO 不能用于那种模式，则方向 -设置可能失败。依赖启动固件来正确地设置方向通常是一个坏主意，因为它可能 -除了启动Linux，并没有做更多的验证工作。(同理, 板子的启动代码可能需要 -将这个复用的引脚设置为 GPIO，并正确地配置上拉/下拉电阻。) - - -访问自旋锁安全的 GPIO -------------------- -大多数 GPIO 控制器可以通过内存读/写指令来访问。这些指令不会休眠,可以 -安全地在硬(非线程)中断例程和类似的上下文中完成。 - -对于那些用 gpio_cansleep()测试总是返回失败的 GPIO(见下文)，使用 -以下的函数访问: - - /* GPIO 输入:返回零或非零 */ - int gpio_get_value(unsigned gpio); - - /* GPIO 输出 */ - void gpio_set_value(unsigned gpio, int value); - -GPIO值是布尔值，零表示低电平，非零表示高电平。当读取一个输出引脚的值时， -返回值应该是引脚上的值。这个值不总是和输出值相符，因为存在开漏输出信号和 -输出延迟问题。 - -以上的 get/set 函数无错误返回值，因为之前 gpio_direction_*()应已检查过 -其是否为“无效GPIO”。此外，还需要注意的是并不是所有平台都可以从输出引脚 -中读取数据，对于不能读取的引脚应总返回零。另外，对那些在原子上下文中无法 -安全访问的 GPIO (译者注：因为访问可能导致休眠)使用这些函数是不合适的 -(见下文)。 - -在 GPIO 编号(还有输出、值)为常数的情况下,鼓励通过平台特定的实现来优化 -这两个函数来访问 GPIO 值。这种情况(读写一个硬件寄存器)下只需要几条指令 -是很正常的,且无须自旋锁。这种优化函数比起那些在子程序上花费许多指令的 -函数可以使得模拟接口(译者注:例如 GPIO 模拟 I2C、1-wire 或 SPI)的 -应用(在空间和时间上都)更具效率。 - - -访问可能休眠的 GPIO ------------------ -某些 GPIO 控制器必须通过基于总线(如 I2C 或 SPI)的消息访问。读或写这些 -GPIO 值的命令需要等待其信息排到队首才发送命令，再获得其反馈。期间需要 -休眠，这不能在 IRQ 例程(中断上下文)中执行。 - -支持此类 GPIO 的平台通过以下函数返回非零值来区分出这种 GPIO。(此函数需要 -一个之前通过 gpio_request 分配到的有效 GPIO 编号): - - int gpio_cansleep(unsigned gpio); - -为了访问这种 GPIO,内核定义了一套不同的函数: - - /* GPIO 输入:返回零或非零 ,可能会休眠 */ - int gpio_get_value_cansleep(unsigned gpio); - - /* GPIO 输出,可能会休眠 */ - void gpio_set_value_cansleep(unsigned gpio, int value); - - -访问这样的 GPIO 需要一个允许休眠的上下文，例如线程 IRQ 处理例程，并用以上的 -访问函数替换那些没有 cansleep()后缀的自旋锁安全访问函数。 - -除了这些访问函数可能休眠，且它们操作的 GPIO 不能在硬件 IRQ 处理例程中访问的 -事实，这些处理例程实际上和自旋锁安全的函数是一样的。 - -** 除此之外 ** 调用设置和配置此类 GPIO 的函数也必须在允许休眠的上下文中， -因为它们可能也需要访问 GPIO 控制器芯片: (这些设置函数通常在板级启动代码或者 -驱动探测/断开代码中，所以这是一个容易满足的约束条件。) - - gpio_direction_input() - gpio_direction_output() - gpio_request() - -## gpio_request_one() -## gpio_request_array() -## gpio_free_array() - - gpio_free() - gpio_set_debounce() - - - -声明和释放 GPIO ----------------------------- -为了有助于捕获系统配置错误,定义了两个函数。 - - /* 申请 GPIO, 返回 0 或负的错误代码. - * 非空标签可能有助于诊断. - */ - int gpio_request(unsigned gpio, const char *label); - - /* 释放之前声明的 GPIO */ - void gpio_free(unsigned gpio); - -将无效的 GPIO 编码传递给 gpio_request()会导致失败，申请一个已使用这个 -函数声明过的 GPIO 也会失败。gpio_request()的返回值必须检查。你应该在 -进程上下文中调用这些函数。然而,对于自旋锁安全的 GPIO,在板子启动的早期、 -进入进程之前是可以申请的。 - -这个函数完成两个基本的目标。一是标识那些实际上已作为 GPIO 使用的信号线， -这样便于更好地诊断;系统可能需要服务几百个可用的 GPIO，但是对于任何一个 -给定的电路板通常只有一些被使用。另一个目的是捕获冲突，查明错误:如两个或 -更多驱动错误地认为他们已经独占了某个信号线,或是错误地认为移除一个管理着 -某个已激活信号的驱动是安全的。也就是说，申请 GPIO 的作用类似一种锁机制。 - -某些平台可能也使用 GPIO 作为电源管理激活信号(例如通过关闭未使用芯片区和 -简单地关闭未使用时钟)。 - -对于 GPIO 使用 pinctrl 子系统已知的引脚，子系统应该被告知其使用情况； -一个 gpiolib 驱动的 .request()操作应调用 pinctrl_request_gpio()， -而 gpiolib 驱动的 .free()操作应调用 pinctrl_free_gpio()。pinctrl -子系统允许 pinctrl_request_gpio()在某个引脚或引脚组以复用形式“属于” -一个设备时都成功返回。 - -任何须将 GPIO 信号导向适当引脚的引脚复用硬件的编程应该发生在 GPIO -驱动的 .direction_input()或 .direction_output()函数中，以及 -任何输出 GPIO 值的设置之后。这样可使从引脚特殊功能到 GPIO 的转换 -不会在引脚产生毛刺波形。有时当用一个 GPIO 实现其信号驱动一个非 GPIO -硬件模块的解决方案时，就需要这种机制。 - -某些平台允许部分或所有 GPIO 信号使用不同的引脚。类似的，GPIO 或引脚的 -其他方面也需要配置，如上拉/下拉。平台软件应该在对这些 GPIO 调用 -gpio_request()前将这类细节配置好，例如使用 pinctrl 子系统的映射表， -使得 GPIO 的用户无须关注这些细节。 - -还有一个值得注意的是在释放 GPIO 前，你必须停止使用它。 - - -注意:申请一个 GPIO 并没有以任何方式配置它，只不过标识那个 GPIO 处于使用 -状态。必须有另外的代码来处理引脚配置(如控制 GPIO 使用的引脚、上拉/下拉)。 -考虑到大多数情况下声明 GPIO 之后就会立即配置它们,所以定义了以下三个辅助函数: - - /* 申请一个 GPIO 信号, 同时通过特定的'flags'初始化配置, - * 其他和 gpio_request()的参数和返回值相同 - * - */ - int gpio_request_one(unsigned gpio, unsigned long flags, const char *label); - - /* 在单个函数中申请多个 GPIO - */ - int gpio_request_array(struct gpio *array, size_t num); - - /* 在单个函数中释放多个 GPIO - */ - void gpio_free_array(struct gpio *array, size_t num); - -这里 'flags' 当前定义可指定以下属性: - - * GPIOF_DIR_IN - 配置方向为输入 - * GPIOF_DIR_OUT - 配置方向为输出 - - * GPIOF_INIT_LOW - 在作为输出时,初始值为低电平 - * GPIOF_INIT_HIGH - 在作为输出时,初始值为高电平 - * GPIOF_OPEN_DRAIN - gpio引脚为开漏信号 - * GPIOF_OPEN_SOURCE - gpio引脚为源极开路信号 - - * GPIOF_EXPORT_DIR_FIXED - 将 gpio 导出到 sysfs，并保持方向 - * GPIOF_EXPORT_DIR_CHANGEABLE - 同样是导出, 但允许改变方向 - -因为 GPIOF_INIT_* 仅有在配置为输出的时候才存在,所以有效的组合为: - - * GPIOF_IN - 配置为输入 - * GPIOF_OUT_INIT_LOW - 配置为输出,并初始化为低电平 - * GPIOF_OUT_INIT_HIGH - 配置为输出,并初始化为高电平 - -当设置 flag 为 GPIOF_OPEN_DRAIN 时，则假设引脚是开漏信号。这样的引脚 -将不会在输出模式下置1。这样的引脚需要连接上拉电阻。通过使能这个标志，gpio库 -将会在被要求输出模式下置1时将引脚变为输入状态来使引脚置高。引脚在输出模式下 -通过置0使其输出低电平。 - -当设置 flag 为 GPIOF_OPEN_SOURCE 时，则假设引脚为源极开路信号。这样的引脚 -将不会在输出模式下置0。这样的引脚需要连接下拉电阻。通过使能这个标志，gpio库 -将会在被要求输出模式下置0时将引脚变为输入状态来使引脚置低。引脚在输出模式下 -通过置1使其输出高电平。 - -将来这些标志可能扩展到支持更多的属性。 - -更进一步,为了更简单地声明/释放多个 GPIO,'struct gpio'被引进来封装所有 -这三个领域: - - struct gpio { - unsigned gpio; - unsigned long flags; - const char *label; - }; - -一个典型的用例: - - static struct gpio leds_gpios[] = { - { 32, GPIOF_OUT_INIT_HIGH, "Power LED" }, /* 默认开启 */ - { 33, GPIOF_OUT_INIT_LOW, "Green LED" }, /* 默认关闭 */ - { 34, GPIOF_OUT_INIT_LOW, "Red LED" }, /* 默认关闭 */ - { 35, GPIOF_OUT_INIT_LOW, "Blue LED" }, /* 默认关闭 */ - { ... }, - }; - - err = gpio_request_one(31, GPIOF_IN, "Reset Button"); - if (err) - ... - - err = gpio_request_array(leds_gpios, ARRAY_SIZE(leds_gpios)); - if (err) - ... - - gpio_free_array(leds_gpios, ARRAY_SIZE(leds_gpios)); - - -GPIO 映射到 IRQ --------------------- -GPIO 编号是无符号整数;IRQ 编号也是。这些构成了两个逻辑上不同的命名空间 -(GPIO 0 不一定使用 IRQ 0)。你可以通过以下函数在它们之间实现映射: - - /* 映射 GPIO 编号到 IRQ 编号 */ - int gpio_to_irq(unsigned gpio); - - /* 映射 IRQ 编号到 GPIO 编号 (尽量避免使用) */ - int irq_to_gpio(unsigned irq); - -它们的返回值为对应命名空间的相关编号，或是负的错误代码(如果无法映射)。 -(例如,某些 GPIO 无法做为 IRQ 使用。)以下的编号错误是未经检测的:使用一个 -未通过 gpio_direction_input()配置为输入的 GPIO 编号，或者使用一个 -并非来源于gpio_to_irq()的 IRQ 编号。 - -这两个映射函数可能会在信号编号的加减计算过程上花些时间。它们不可休眠。 - -gpio_to_irq()返回的非错误值可以传递给 request_irq()或者 free_irq()。 -它们通常通过板级特定的初始化代码存放到平台设备的 IRQ 资源中。注意:IRQ -触发选项是 IRQ 接口的一部分，如 IRQF_TRIGGER_FALLING，系统唤醒能力 -也是如此。 - -irq_to_gpio()返回的非错误值大多数通常可以被 gpio_get_value()所使用， -比如在 IRQ 是沿触发时初始化或更新驱动状态。注意某些平台不支持反映射,所以 -你应该尽量避免使用它。 - - -模拟开漏信号 ----------------------------- -有时在只有低电平信号作为实际驱动结果(译者注:多个输出连接于一点，逻辑电平 -结果为所有输出的逻辑与)的时候,共享的信号线需要使用“开漏”信号。(该术语 -适用于 CMOS 管；而 TTL 用“集电极开路”。)一个上拉电阻使信号为高电平。这 -有时被称为“线与”。实际上，从负逻辑(低电平为真)的角度来看，这是一个“线或”。 - -一个开漏信号的常见例子是共享的低电平使能 IRQ 信号线。此外,有时双向数据总线 -信号也使用漏极开路信号。 - -某些 GPIO 控制器直接支持开漏输出，还有许多不支持。当你需要开漏信号，但 -硬件又不直接支持的时候，一个常用的方法是用任何即可作输入也可作输出的 GPIO -引脚来模拟: - - LOW: gpio_direction_output(gpio, 0) ... 这代码驱动信号并覆盖 - 上拉配置。 - - HIGH: gpio_direction_input(gpio) ... 这代码关闭输出,所以上拉电阻 - (或其他的一些器件)控制了信号。 - -如果你将信号线“驱动”为高电平，但是 gpio_get_value(gpio)报告了一个 -低电平(在适当的上升时间后)，你就可以知道是其他的一些组件将共享信号线拉低了。 -这不一定是错误的。一个常见的例子就是 I2C 时钟的延长：一个需要较慢时钟的 -从设备延迟 SCK 的上升沿，而 I2C 主设备相应地调整其信号传输速率。 - - -这些公约忽略了什么? -================ -这些公约忽略的最大一件事就是引脚复用，因为这属于高度芯片特定的属性且 -没有可移植性。某个平台可能不需要明确的复用信息；有的对于任意给定的引脚 -可能只有两个功能选项；有的可能每个引脚有八个功能选项；有的可能可以将 -几个引脚中的任何一个作为给定的 GPIO。(是的，这些例子都来自于当前运行 -Linux 的系统。) - -在某些系统中,与引脚复用相关的是配置和使能集成的上、下拉模式。并不是所有 -平台都支持这种模式,或者不会以相同的方式来支持这种模式；且任何给定的电路板 -可能使用外置的上拉(或下拉)电阻,这时芯片上的就不应该使用。(当一个电路需要 -5kOhm 的拉动电阻,芯片上的 100 kOhm 电阻就不能做到。)同样的，驱动能力 -(2 mA vs 20 mA)和电压(1.8V vs 3.3V)是平台特定问题,就像模型一样在 -可配置引脚和 GPIO 之间(没)有一一对应的关系。 - -还有其他一些系统特定的机制没有在这里指出，例如上述的输入去毛刺和线与输出 -选项。硬件可能支持批量读或写 GPIO，但是那一般是配置相关的：对于处于同一 -块区(bank)的GPIO。(GPIO 通常以 16 或 32 个组成一个区块，一个给定的 -片上系统一般有几个这样的区块。)某些系统可以通过输出 GPIO 触发 IRQ， -或者从并非以 GPIO 管理的引脚取值。这些机制的相关代码没有必要具有可移植性。 - -当前，动态定义 GPIO 并不是标准的，例如作为配置一个带有某些 GPIO 扩展器的 -附加电路板的副作用。 - -GPIO 实现者的框架 (可选) -===================== -前面提到了，有一个可选的实现框架，让平台使用相同的编程接口，更加简单地支持 -不同种类的 GPIO 控制器。这个框架称为"gpiolib"。 - -作为一个辅助调试功能，如果 debugfs 可用，就会有一个 /sys/kernel/debug/gpio -文件。通过这个框架，它可以列出所有注册的控制器,以及当前正在使用中的 GPIO -的状态。 - - -控制器驱动: gpio_chip -------------------- -在框架中每个 GPIO 控制器都包装为一个 "struct gpio_chip"，他包含了 -该类型的每个控制器的常用信息: - - - 设置 GPIO 方向的方法 - - 用于访问 GPIO 值的方法 - - 告知调用其方法是否可能休眠的标志 - - 可选的 debugfs 信息导出方法 (显示类似上拉配置一样的额外状态) - - 诊断标签 - -也包含了来自 device.platform_data 的每个实例的数据：它第一个 GPIO 的 -编号和它可用的 GPIO 的数量。 - -实现 gpio_chip 的代码应支持多控制器实例，这可能使用驱动模型。那些代码要 -配置每个 gpio_chip，并发起gpiochip_add()。卸载一个 GPIO 控制器很少见， -但在必要的时候可以使用 gpiochip_remove()。 - -大部分 gpio_chip 是一个实例特定结构体的一部分，而并不将 GPIO 接口单独 -暴露出来,比如编址、电源管理等。类似编解码器这样的芯片会有复杂的非 GPIO -状态。 - -任何一个 debugfs 信息导出方法通常应该忽略还未申请作为 GPIO 的信号线。 -他们可以使用 gpiochip_is_requested()测试，当这个 GPIO 已经申请过了 -就返回相关的标签，否则返回 NULL。 - - -平台支持 -------- -为了支持这个框架，一个平台的 Kconfig 文件将会 "select"(选择) -ARCH_REQUIRE_GPIOLIB 或 ARCH_WANT_OPTIONAL_GPIOLIB，并让它的 - 包含 ，同时定义三个方法: -gpio_get_value()、gpio_set_value()和 gpio_cansleep()。 - -它也应提供一个 ARCH_NR_GPIOS 的定义值，这样可以更好地反映该平台 GPIO -的实际数量,节省静态表的空间。(这个定义值应该包含片上系统内建 GPIO 和 -GPIO 扩展器中的数据。) - -ARCH_REQUIRE_GPIOLIB 意味着 gpiolib 核心在这个构架中将总是编译进内核。 - -ARCH_WANT_OPTIONAL_GPIOLIB 意味着 gpiolib 核心默认关闭,且用户可以 -使能它,并将其编译进内核(可选)。 - -如果这些选项都没被选择,该平台就不通过 GPIO-lib 支持 GPIO,且代码不可以 -被用户使能。 - -以下这些方法的实现可以直接使用框架代码,并总是通过 gpio_chip 调度: - - #define gpio_get_value __gpio_get_value - #define gpio_set_value __gpio_set_value - #define gpio_cansleep __gpio_cansleep - -这些定义可以用更理想的实现方法替代，那就是使用经过逻辑优化的内联函数来访问 -基于特定片上系统的 GPIO。例如,若引用的 GPIO (寄存器位偏移)是常量“12”， -读取或设置它可能只需少则两或三个指令，且不会休眠。当这样的优化无法实现时， -那些函数必须使用框架提供的代码，那就至少要几十条指令才可以实现。对于用 GPIO -模拟的 I/O 接口, 如此精简指令是很有意义的。 - -对于片上系统，平台特定代码为片上 GPIO 每个区(bank)定义并注册 gpio_chip -实例。那些 GPIO 应该根据芯片厂商的文档进行编码/标签,并直接和电路板原理图 -对应。他们应该开始于零并终止于平台特定的限制。这些 GPIO(代码)通常从 -arch_initcall()或者更早的地方集成进平台初始化代码，使这些 GPIO 总是可用， -且他们通常可以作为 IRQ 使用。 - -板级支持 -------- -对于外部 GPIO 控制器(例如 I2C 或 SPI 扩展器、专用芯片、多功能器件、FPGA -或 CPLD)，大多数常用板级特定代码都可以注册控制器设备，并保证他们的驱动知道 -gpiochip_add()所使用的 GPIO 编号。他们的起始编号通常跟在平台特定的 GPIO -编号之后。 - -例如板级启动代码应该创建结构体指明芯片公开的 GPIO 范围，并使用 platform_data -将其传递给每个 GPIO 扩展器芯片。然后芯片驱动中的 probe()例程可以将这个 -数据传递给 gpiochip_add()。 - -初始化顺序很重要。例如，如果一个设备依赖基于 I2C 的(扩展)GPIO，那么它的 -probe()例程就应该在那个 GPIO 有效以后才可以被调用。这意味着设备应该在 -GPIO 可以工作之后才可被注册。解决这类依赖的的一种方法是让这种 gpio_chip -控制器向板级特定代码提供 setup()和 teardown()回调函数。一旦所有必须的 -资源可用之后，这些板级特定的回调函数将会注册设备，并可以在这些 GPIO 控制器 -设备变成无效时移除它们。 - - -用户空间的 Sysfs 接口(可选) -======================== -使用“gpiolib”实现框架的平台可以选择配置一个 GPIO 的 sysfs 用户接口。 -这不同于 debugfs 接口，因为它提供的是对 GPIO方向和值的控制，而不只显示 -一个GPIO 的状态摘要。此外,它可以出现在没有调试支持的产品级系统中。 - -例如，通过适当的系统硬件文档，用户空间可以知道 GIOP #23 控制 Flash -存储器的写保护(用于保护其中 Bootloader 分区)。产品的系统升级可能需要 -临时解除这个保护：首先导入一个 GPIO，改变其输出状态，然后在重新使能写保护 -前升级代码。通常情况下,GPIO #23 是不会被触及的，并且内核也不需要知道他。 - -根据适当的硬件文档，某些系统的用户空间 GPIO 可以用于确定系统配置数据， -这些数据是标准内核不知道的。在某些任务中，简单的用户空间 GPIO 驱动可能是 -系统真正需要的。 - -注意：标准内核驱动中已经存在通用的“LED 和按键”GPIO 任务，分别是: -"leds-gpio" 和 "gpio_keys"。请使用这些来替代直接访问 GPIO，因为集成在 -内核框架中的这类驱动比你在用户空间的代码更好。 - - -Sysfs 中的路径 --------------- -在/sys/class/gpio 中有 3 类入口: - - - 用于在用户空间控制 GPIO 的控制接口; - - - GPIOs 本身;以及 - - - GPIO 控制器 ("gpio_chip" 实例)。 - -除了这些标准的文件,还包含“device”符号链接。 - -控制接口是只写的: - - /sys/class/gpio/ - - "export" ... 用户空间可以通过写其编号到这个文件，要求内核导出 - 一个 GPIO 的控制到用户空间。 - - 例如: 如果内核代码没有申请 GPIO #19,"echo 19 > export" - 将会为 GPIO #19 创建一个 "gpio19" 节点。 - - "unexport" ... 导出到用户空间的逆操作。 - - 例如: "echo 19 > unexport" 将会移除使用"export"文件导出的 - "gpio19" 节点。 - -GPIO 信号的路径类似 /sys/class/gpio/gpio42/ (对于 GPIO #42 来说)， -并有如下的读/写属性: - - /sys/class/gpio/gpioN/ - - "direction" ... 读取得到 "in" 或 "out"。这个值通常运行写入。 - 写入"out" 时,其引脚的默认输出为低电平。为了确保无故障运行， - "low" 或 "high" 的电平值应该写入 GPIO 的配置，作为初始输出值。 - - 注意:如果内核不支持改变 GPIO 的方向，或者在导出时内核代码没有 - 明确允许用户空间可以重新配置 GPIO 方向，那么这个属性将不存在。 - - "value" ... 读取得到 0 (低电平) 或 1 (高电平)。如果 GPIO 配置为 - 输出,这个值允许写操作。任何非零值都以高电平看待。 - - 如果引脚可以配置为中断信号，且如果已经配置了产生中断的模式 - （见"edge"的描述），你可以对这个文件使用轮询操作(poll(2))， - 且轮询操作会在任何中断触发时返回。如果你使用轮询操作(poll(2))， - 请在 events 中设置 POLLPRI 和 POLLERR。如果你使用轮询操作 - (select(2))，请在 exceptfds 设置你期望的文件描述符。在 - 轮询操作(poll(2))返回之后，既可以通过 lseek(2)操作读取 - sysfs 文件的开始部分，也可以关闭这个文件并重新打开它来读取数据。 - - "edge" ... 读取得到“none”、“rising”、“falling”或者“both”。 - 将这些字符串写入这个文件可以选择沿触发模式，会使得轮询操作 - (select(2))在"value"文件中返回。 - - 这个文件仅有在这个引脚可以配置为可产生中断输入引脚时，才存在。 - - "active_low" ... 读取得到 0 (假) 或 1 (真)。写入任何非零值可以 - 翻转这个属性的(读写)值。已存在或之后通过"edge"属性设置了"rising" - 和 "falling" 沿触发模式的轮询操作(poll(2))将会遵循这个设置。 - -GPIO 控制器的路径类似 /sys/class/gpio/gpiochip42/ (对于从#42 GPIO -开始实现控制的控制器),并有着以下只读属性: - - /sys/class/gpio/gpiochipN/ - - "base" ... 与以上的 N 相同,代表此芯片管理的第一个 GPIO 的编号 - - "label" ... 用于诊断 (并不总是只有唯一值) - - "ngpio" ... 此控制器所管理的 GPIO 数量(而 GPIO 编号从 N 到 - N + ngpio - 1) - -大多数情况下,电路板的文档应当标明每个 GPIO 的使用目的。但是那些编号并不总是 -固定的,例如在扩展卡上的 GPIO会根据所使用的主板或所在堆叠架构中其他的板子而 -有所不同。在这种情况下,你可能需要使用 gpiochip 节点(尽可能地结合电路图)来 -确定给定信号所用的 GPIO 编号。 - - -从内核代码中导出 -------------- -内核代码可以明确地管理那些已通过 gpio_request()申请的 GPIO 的导出: - - /* 导出 GPIO 到用户空间 */ - int gpio_export(unsigned gpio, bool direction_may_change); - - /* gpio_export()的逆操作 */ - void gpio_unexport(); - - /* 创建一个 sysfs 连接到已导出的 GPIO 节点 */ - int gpio_export_link(struct device *dev, const char *name, - unsigned gpio) - - /* 改变 sysfs 中的一个 GPIO 节点的极性 */ - int gpio_sysfs_set_active_low(unsigned gpio, int value); - -在一个内核驱动申请一个 GPIO 之后，它可以通过 gpio_export()使其在 sysfs -接口中可见。该驱动可以控制信号方向是否可修改。这有助于防止用户空间代码无意间 -破坏重要的系统状态。 - -这个明确的导出有助于(通过使某些实验更容易来)调试，也可以提供一个始终存在的接口， -与文档配合作为板级支持包的一部分。 - -在 GPIO 被导出之后，gpio_export_link()允许在 sysfs 文件系统的任何地方 -创建一个到这个 GPIO sysfs 节点的符号链接。这样驱动就可以通过一个描述性的 -名字，在 sysfs 中他们所拥有的设备下提供一个(到这个 GPIO sysfs 节点的)接口。 - -驱动可以使用 gpio_sysfs_set_active_low() 来在用户空间隐藏电路板之间 -GPIO 线的极性差异。这个仅对 sysfs 接口起作用。极性的改变可以在 gpio_export() -前后进行,且之前使能的轮询操作(poll(2))支持(上升或下降沿)将会被重新配置来遵循 -这个设置。 diff --git a/trunk/Documentation/zh_CN/video4linux/omap3isp.txt b/trunk/Documentation/zh_CN/video4linux/omap3isp.txt deleted file mode 100644 index 67ffbf352ae0..000000000000 --- a/trunk/Documentation/zh_CN/video4linux/omap3isp.txt +++ /dev/null @@ -1,277 +0,0 @@ -Chinese translated version of Documentation/video4linux/omap3isp.txt - -If you have any comment or update to the content, please contact the -original document maintainer directly. However, if you have a problem -communicating in English you can also ask the Chinese maintainer for -help. Contact the Chinese maintainer if this translation is outdated -or if there is a problem with the translation. - -Maintainer: Laurent Pinchart - Sakari Ailus - David Cohen -Chinese maintainer: Fu Wei ---------------------------------------------------------------------- -Documentation/video4linux/omap3isp.txt 的中文翻译 - -如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 -交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 -译存在问题，请联系中文版维护者。 -英文版维护者： Laurent Pinchart - Sakari Ailus - David Cohen -中文版维护者： 傅炜 Fu Wei -中文版翻译者： 傅炜 Fu Wei -中文版校译者： 傅炜 Fu Wei - - -以下为正文 ---------------------------------------------------------------------- -OMAP 3 图像信号处理器 (ISP) 驱动 - -Copyright (C) 2010 Nokia Corporation -Copyright (C) 2009 Texas Instruments, Inc. - -联系人: Laurent Pinchart - Sakari Ailus - David Cohen - - -介绍 -=== - -本文档介绍了由 drivers/media/video/omap3isp 加载的德州仪器 -（TI）OMAP 3 图像信号处理器 (ISP) 驱动。原始驱动由德州仪器（TI） -编写，但此后由诺基亚重写了两次。 - -驱动已在以下 OMAP 3 系列的芯片中成功使用： - - 3430 - 3530 - 3630 - -驱动实现了 V4L2、媒体控制器和 v4l2_subdev 接口。支持内核中使用 -v4l2_subdev 接口的传感器、镜头和闪光灯驱动。 - - -拆分为子设备 -========== - -OMAP 3 ISP 被拆分为 V4L2 子设备，ISP中的每个模块都由一个子设备 -来表示。每个子设备向用户空间提供一个 V4L2 子设备接口。 - - OMAP3 ISP CCP2 - OMAP3 ISP CSI2a - OMAP3 ISP CCDC - OMAP3 ISP preview - OMAP3 ISP resizer - OMAP3 ISP AEWB - OMAP3 ISP AF - OMAP3 ISP histogram - -ISP 中每个可能的连接都通过一个链接嵌入到媒体控制器接口中。详见例程 [2]。 - - -控制 OMAP 3 ISP -============== - -通常，对 OMAP 3 ISP 的配置会在下一帧起始时生效。在传感器垂直消隐期间， -模块变为空闲时完成配置。在内存到内存的操作中，视频管道一次处理一帧。 -应用配置应在帧间完成。 - -ISP 中的所有模块，除 CSI-2 和 （可能存在的）CCP2 接收器外，都必须 -接收完整的帧数据。因此，传感器必须保证从不发送部分帧数据给ISP。 - -Autoidle（自动空闲）功能至少在 3430 的 ISP 模块中确实存在一些问题。 -当 omap3isp 模块参数 autoidle 非零时，autoidle（自动空闲）功能 -仅在 3630 中启用了。 - - -事件机制 -====== - -OMAP 3 ISP 驱动在 CCDC 和统计（AEWB、AF 和 直方图）子设备中支持 -V4L2 事件机制接口。 - -CCDC 子设备通过 HS_VS 中断，处理 V4L2_EVENT_FRAME_SYNC 类型 -事件，用于告知帧起始。早期版本的驱动则使用 V4L2_EVENT_OMAP3ISP_HS_VS。 -当在 CCDC 模块中接收到起始帧的第一行时，会准确地触发事件。这个事件 -可以在 CCDC 子设备中“订阅”。 - -（当使用并行接口时，必须注意正确地配置 VS 信号极性。而当使用串行接收时 -这个会自动校正。） - -每个统计子设备都可以产生事件。每当一个统计缓冲区可由用户空间应用程序 -通过 VIDIOC_OMAP3ISP_STAT_REQ IOCTL 操作获取时，就会产生一个 -事件。当前存在以下事件： - - V4L2_EVENT_OMAP3ISP_AEWB - V4L2_EVENT_OMAP3ISP_AF - V4L2_EVENT_OMAP3ISP_HIST - -这些 ioctl 的事件数据类型为 struct omap3isp_stat_event_status -结构体。如果出现计算错误的统计，也同样会产生一个事件，但没有相关的统计 -数据缓冲区。这种情况下 omap3isp_stat_event_status.buf_err 会被 -设置为非零值。 - - -私有 IOCTL -========== - -OMAP 3 ISP 驱动支持标准的 V4L2 IOCTL 以及可能存在且实用的控制。但 -ISP 提供的许多功能都不在标准 IOCTL 之列，例如 gamma（伽马）表和统计 -数据采集配置等。 - -通常，会有一个私有 ioctl 用于配置每个包含硬件依赖功能的模块。 - -支持以下私有 IOCTL： - - VIDIOC_OMAP3ISP_CCDC_CFG - VIDIOC_OMAP3ISP_PRV_CFG - VIDIOC_OMAP3ISP_AEWB_CFG - VIDIOC_OMAP3ISP_HIST_CFG - VIDIOC_OMAP3ISP_AF_CFG - VIDIOC_OMAP3ISP_STAT_REQ - VIDIOC_OMAP3ISP_STAT_EN - -在 include/linux/omap3isp.h 中描述了这些 ioctl 使用的参数结构体。 -与特定 ISP 模块相关的 ISP 自身的详细功能在技术参考手册 (TRMs)中有 -描述，详见文档结尾。 - -虽然在不使用任何私有 IOCTL 的情况下使用 ISP 驱动是可能的，但这样无法 -获得最佳的图像质量。AEWB、AF 和 直方图（译者注：一般用于自动曝光和增益 -控制，以及图像均衡等）模块无法在未使用适当的私有 IOCTL 配置的情况下使用。 - - -CCDC 和 preview（预览）模块 IOCTL -=============================== - -VIDIOC_OMAP3ISP_CCDC_CFG 和 VIDIOC_OMAP3ISP_PRV_CFG IOCTL -被分别用于配置、启用和禁用 CCDC 和 preview（预览）模块的功能。在它们 -所控制的模块中，两个 IOCTL 控制多种功能。VIDIOC_OMAP3ISP_CCDC_CFG IOCTL -接受一个指向 omap3isp_ccdc_update_config 结构体的指针作为它的参数。 -同样的，VIDIOC_OMAP3ISP_PRV_CFG 接受一个指向 omap3isp_prev_update_config -结构体的指针。以上两个结构体定义位于 [1]。 - -这些结构体中的 update 域标识是否针对指定的功能更新配置，而 flag 域 -则标识是启用还是禁用此功能。 - -update 和 flag 位接受以下掩码值。CCDC 和 preview（预览）模块的 -每个单独功能都与一个 flag 关联（禁用或启用；在结构体中 flag 域的 -一部分）和一个指向功能配置数据的指针。 - -对于 VIDIOC_OMAP3ISP_CCDC_CFG，下面列出了 update 和 flag 域 -中的有效值。 这些值可能会在同一个 IOCTL 调用中配置多个功能。 - - OMAP3ISP_CCDC_ALAW - OMAP3ISP_CCDC_LPF - OMAP3ISP_CCDC_BLCLAMP - OMAP3ISP_CCDC_BCOMP - OMAP3ISP_CCDC_FPC - OMAP3ISP_CCDC_CULL - OMAP3ISP_CCDC_CONFIG_LSC - OMAP3ISP_CCDC_TBL_LSC - -针对 VIDIOC_OMAP3ISP_PRV_CFG 的相应值如下： - - OMAP3ISP_PREV_LUMAENH - OMAP3ISP_PREV_INVALAW - OMAP3ISP_PREV_HRZ_MED - OMAP3ISP_PREV_CFA - OMAP3ISP_PREV_CHROMA_SUPP - OMAP3ISP_PREV_WB - OMAP3ISP_PREV_BLKADJ - OMAP3ISP_PREV_RGB2RGB - OMAP3ISP_PREV_COLOR_CONV - OMAP3ISP_PREV_YC_LIMIT - OMAP3ISP_PREV_DEFECT_COR - OMAP3ISP_PREV_GAMMABYPASS - OMAP3ISP_PREV_DRK_FRM_CAPTURE - OMAP3ISP_PREV_DRK_FRM_SUBTRACT - OMAP3ISP_PREV_LENS_SHADING - OMAP3ISP_PREV_NF - OMAP3ISP_PREV_GAMMA - -在启用某个功能的时候，相关的配置数据指针不可为 NULL。在禁用某个功能时， -配置数据指针会被忽略。 - - -统计模块 IOCTL -============= - -统计子设备相较于其他子设备提供了更多动态配置选项。在图像处理流水线处于 -工作状态时，它们可以被启用、禁用和重配。 - -统计模块总是从 CCDC 中获取输入的图像数据（由于直方图内存读取未实现）。 -统计数据可由用户通过统计子设备节点使用私有 IOCTL 获取。 - -AEWB、AF 和 直方图子设备提供的私有 IOCTL 极大程度上反应了 ISP 硬件 -提供的寄存器级接口。有些方面纯粹和驱动程序的实现相关，这些将在下面讨论。 - -VIDIOC_OMAP3ISP_STAT_EN ------------------------ - -这个私有 IOCTL 启用/禁用 一个统计模块。如果这个申请在视频流启动前完成， -它将在视频流水线开始工作时生效。如果视频流水线已经处于工作状态了，它将在 -CCDC 变为空闲时生效。 - -VIDIOC_OMAP3ISP_AEWB_CFG, VIDIOC_OMAP3ISP_HIST_CFG and VIDIOC_OMAP3ISP_AF_CFG ------------------------------------------------------------------------------ - -这些 IOCTL 用于配置模块。它们要求用户应用程序对硬件有深入的认识。对 -大多数域的解释可以在 OMAP 的 TRM 中找到。以下两个域对于以上所有的 -私有 IOCTL 配置都很常见，由于他们没有在 TRM 中提及，故需要对其有 -更好的认识。 - -omap3isp_[h3a_af/h3a_aewb/hist]_config.buf_size: - -模块在内部处理自身缓冲。对模块数据输出所必需的缓存大小依赖于已申请的配置。 -虽然驱动支持在视频流工作时重新配置，但对于所需缓存量大于模块启用时内部 -所分配数量的情况，则不支持重新配置。在这种情况下将返回 -EBUSY。为了避免 -此类状况，无论是禁用/重配/启用模块，还是第一次配置时申请必须的缓存大小， -都应在模块禁用的情况下进行。 - -内部缓冲分配的大小需综合考虑所申请配置的最小缓存量以及 buf_size 域中 -所设的值。如果 buf_size 域在[minimum（最小值）, maximum（最大值）] -缓冲大小范围之外，则应该将其调整到其范围中。驱动则会选择最大值。正确的 -buf_size 值将回写到用户应用程序中。 - -omap3isp_[h3a_af/h3a_aewb/hist]_config.config_counter: - -由于配置并未在申请之后同步生效，驱动必须提供一个跟踪这类信息的方法， -以提供更准确的数据。在一个配置被申请之后，返回到用户空间应用程序的 -config_counter 是一个与其配置相关的唯一值。当用户应用程序接收到 -一个缓冲可用或一个新的缓冲申请事件时，这个 config_counter 用于 -一个缓冲数据和一个配置的匹配。 - -VIDIOC_OMAP3ISP_STAT_REQ ------------------------- - -将内部缓冲队列中最早的数据发送到用户空间，然后丢弃此缓冲区。 -omap3isp_stat_data.frame_number 域与视频缓冲的 field_count -域相匹配。 - - -技术参考手册 (TRMs) 和其他文档 -========================== - -OMAP 3430 TRM: - -参考于 2011-03-05. - -OMAP 35xx TRM: - 参考于 2011-03-05. - -OMAP 3630 TRM: - -参考于 2011-03-05. - -DM 3730 TRM: - 参考于 2011-03-06. - - -参考资料 -======= - -[1] include/linux/omap3isp.h - -[2] http://git.ideasonboard.org/?p=media-ctl.git;a=summary diff --git a/trunk/Documentation/zh_CN/video4linux/v4l2-framework.txt b/trunk/Documentation/zh_CN/video4linux/v4l2-framework.txt deleted file mode 100644 index 3e74f13af426..000000000000 --- a/trunk/Documentation/zh_CN/video4linux/v4l2-framework.txt +++ /dev/null @@ -1,983 +0,0 @@ -Chinese translated version of Documentation/video4linux/v4l2-framework.txt - -If you have any comment or update to the content, please contact the -original document maintainer directly. However, if you have a problem -communicating in English you can also ask the Chinese maintainer for -help. Contact the Chinese maintainer if this translation is outdated -or if there is a problem with the translation. - -Maintainer: Mauro Carvalho Chehab -Chinese maintainer: Fu Wei ---------------------------------------------------------------------- -Documentation/video4linux/v4l2-framework.txt 的中文翻译 - -如果想评论或更新本文的内容，请直接联系原文档的维护者。如果你使用英文 -交流有困难的话，也可以向中文版维护者求助。如果本翻译更新不及时或者翻 -译存在问题，请联系中文版维护者。 -英文版维护者： Mauro Carvalho Chehab -中文版维护者： 傅炜 Fu Wei -中文版翻译者： 傅炜 Fu Wei -中文版校译者： 傅炜 Fu Wei - - -以下为正文 ---------------------------------------------------------------------- -V4L2 驱动框架概览 -============== - -本文档描述 V4L2 框架所提供的各种结构和它们之间的关系。 - - -介绍 ----- - -大部分现代 V4L2 设备由多个 IC 组成，在 /dev 下导出多个设备节点， -并同时创建非 V4L2 设备（如 DVB、ALSA、FB、I2C 和红外输入设备）。 -由于这种硬件的复杂性，V4L2 驱动也变得非常复杂。 - -尤其是 V4L2 必须支持 IC 实现音视频的多路复用和编解码，这就更增加了其 -复杂性。通常这些 IC 通过一个或多个 I2C 总线连接到主桥驱动器，但也可 -使用其他总线。这些设备称为“子设备”。 - -长期以来，这个框架仅限于通过 video_device 结构体创建 V4L 设备节点， -并使用 video_buf 处理视频缓冲（注：本文不讨论 video_buf 框架）。 - -这意味着所有驱动必须自己设置设备实例并连接到子设备。其中一部分要正确地 -完成是比较复杂的，使得许多驱动都没有正确地实现。 - -由于框架的缺失，有很多通用代码都不可重复利用。 - -因此，这个框架构建所有驱动都需要的基本结构块，而统一的框架将使通用代码 -创建成实用函数并在所有驱动中共享变得更加容易。 - - -驱动结构 -------- - -所有 V4L2 驱动都有如下结构： - -1) 每个设备实例的结构体--包含其设备状态。 - -2) 初始化和控制子设备的方法（如果有）。 - -3) 创建 V4L2 设备节点 (/dev/videoX、/dev/vbiX 和 /dev/radioX) - 并跟踪设备节点的特定数据。 - -4) 特定文件句柄结构体--包含每个文件句柄的数据。 - -5) 视频缓冲处理。 - -以下是它们的初略关系图： - - device instances（设备实例） - | - +-sub-device instances（子设备实例） - | - \-V4L2 device nodes（V4L2 设备节点） - | - \-filehandle instances（文件句柄实例） - - -框架结构 -------- - -该框架非常类似驱动结构：它有一个 v4l2_device 结构用于保存设备 -实例的数据；一个 v4l2_subdev 结构体代表子设备实例；video_device -结构体保存 V4L2 设备节点的数据；将来 v4l2_fh 结构体将跟踪文件句柄 -实例（暂未尚未实现）。 - -V4L2 框架也可与媒体框架整合（可选的）。如果驱动设置了 v4l2_device -结构体的 mdev 域，子设备和视频节点的入口将自动出现在媒体框架中。 - - -v4l2_device 结构体 ----------------- - -每个设备实例都通过 v4l2_device (v4l2-device.h)结构体来表示。 -简单设备可以仅分配这个结构体，但在大多数情况下，都会将这个结构体 -嵌入到一个更大的结构体中。 - -你必须注册这个设备实例： - - v4l2_device_register(struct device *dev, struct v4l2_device *v4l2_dev); - -注册操作将会初始化 v4l2_device 结构体。如果 dev->driver_data 域 -为 NULL，就将其指向 v4l2_dev。 - -需要与媒体框架整合的驱动必须手动设置 dev->driver_data，指向包含 -v4l2_device 结构体实例的驱动特定设备结构体。这可以在注册 V4L2 设备 -实例前通过 dev_set_drvdata() 函数完成。同时必须设置 v4l2_device -结构体的 mdev 域，指向适当的初始化并注册过的 media_device 实例。 - -如果 v4l2_dev->name 为空，则它将被设置为从 dev 中衍生出的值（为了 -更加精确，形式为驱动名后跟 bus_id）。如果你在调用 v4l2_device_register -前已经设置好了，则不会被修改。如果 dev 为 NULL，则你*必须*在调用 -v4l2_device_register 前设置 v4l2_dev->name。 - -你可以基于驱动名和驱动的全局 atomic_t 类型的实例编号，通过 -v4l2_device_set_name() 设置 name。这样会生成类似 ivtv0、ivtv1 等 -名字。若驱动名以数字结尾，则会在编号和驱动名间插入一个破折号，如： -cx18-0、cx18-1 等。此函数返回实例编号。 - -第一个 “dev” 参数通常是一个指向 pci_dev、usb_interface 或 -platform_device 的指针。很少使其为 NULL，除非是一个ISA设备或者 -当一个设备创建了多个 PCI 设备，使得 v4l2_dev 无法与一个特定的父设备 -关联。 - -你也可以提供一个 notify() 回调，使子设备可以调用它实现事件通知。 -但这个设置与子设备相关。子设备支持的任何通知必须在 -include/media/.h 中定义一个消息头。 - -注销 v4l2_device 使用如下函数： - - v4l2_device_unregister(struct v4l2_device *v4l2_dev); - -如果 dev->driver_data 域指向 v4l2_dev，将会被重置为 NULL。注销同时 -会自动从设备中注销所有子设备。 - -如果你有一个热插拔设备（如USB设备），则当断开发生时，父设备将无效。 -由于 v4l2_device 有一个指向父设备的指针必须被清除，同时标志父设备 -已消失，所以必须调用以下函数： - - v4l2_device_disconnect(struct v4l2_device *v4l2_dev); - -这个函数并*不*注销子设备，因此你依然要调用 v4l2_device_unregister() -函数。如果你的驱动器并非热插拔的，就没有必要调用 v4l2_device_disconnect()。 - -有时你需要遍历所有被特定驱动注册的设备。这通常发生在多个设备驱动使用 -同一个硬件的情况下。如：ivtvfb 驱动是一个使用 ivtv 硬件的帧缓冲驱动， -同时 alsa 驱动也使用此硬件。 - -你可以使用如下例程遍历所有注册的设备： - -static int callback(struct device *dev, void *p) -{ - struct v4l2_device *v4l2_dev = dev_get_drvdata(dev); - - /* 测试这个设备是否已经初始化 */ - if (v4l2_dev == NULL) - return 0; - ... - return 0; -} - -int iterate(void *p) -{ - struct device_driver *drv; - int err; - - /* 在PCI 总线上查找ivtv驱动。 - pci_bus_type是全局的. 对于USB总线使用usb_bus_type。 */ - drv = driver_find("ivtv", &pci_bus_type); - /* 遍历所有的ivtv设备实例 */ - err = driver_for_each_device(drv, NULL, p, callback); - put_driver(drv); - return err; -} - -有时你需要一个设备实例的运行计数。这个通常用于映射一个设备实例到一个 -模块选择数组的索引。 - -推荐方法如下： - -static atomic_t drv_instance = ATOMIC_INIT(0); - -static int __devinit drv_probe(struct pci_dev *pdev, - const struct pci_device_id *pci_id) -{ - ... - state->instance = atomic_inc_return(&drv_instance) - 1; -} - -如果你有多个设备节点，对于热插拔设备，知道何时注销 v4l2_device 结构体 -就比较困难。为此 v4l2_device 有引用计数支持。当调用 video_register_device -时增加引用计数，而设备节点释放时减小引用计数。当引用计数为零，则 -v4l2_device 的release() 回调将被执行。你就可以在此时做最后的清理工作。 - -如果创建了其他设备节点（比如 ALSA），则你可以通过以下函数手动增减 -引用计数： - -void v4l2_device_get(struct v4l2_device *v4l2_dev); - -或: - -int v4l2_device_put(struct v4l2_device *v4l2_dev); - -由于引用技术初始化为 1 ，你也需要在 disconnect() 回调（对于 USB 设备）中 -调用 v4l2_device_put，或者 remove() 回调（例如对于 PCI 设备），否则 -引用计数将永远不会为 0 。 - -v4l2_subdev结构体 ------------------- - -许多驱动需要与子设备通信。这些设备可以完成各种任务，但通常他们负责 -音视频复用和编解码。如网络摄像头的子设备通常是传感器和摄像头控制器。 - -这些一般为 I2C 接口设备，但并不一定都是。为了给驱动提供调用子设备的 -统一接口，v4l2_subdev 结构体（v4l2-subdev.h）产生了。 - -每个子设备驱动都必须有一个 v4l2_subdev 结构体。这个结构体可以单独 -代表一个简单的子设备，也可以嵌入到一个更大的结构体中，与更多设备状态 -信息保存在一起。通常有一个下级设备结构体（比如：i2c_client）包含了 -内核创建的设备数据。建议使用 v4l2_set_subdevdata() 将这个结构体的 -指针保存在 v4l2_subdev 的私有数据域(dev_priv)中。这使得通过 v4l2_subdev -找到实际的低层总线特定设备数据变得容易。 - -你同时需要一个从低层结构体获取 v4l2_subdev 指针的方法。对于常用的 -i2c_client 结构体，i2c_set_clientdata() 函数可用于保存一个 v4l2_subdev -指针；对于其他总线你可能需要使用其他相关函数。 - -桥驱动中也应保存每个子设备的私有数据，比如一个指向特定桥的各设备私有 -数据的指针。为此 v4l2_subdev 结构体提供主机私有数据域(host_priv)， -并可通过 v4l2_get_subdev_hostdata() 和 v4l2_set_subdev_hostdata() -访问。 - -从总线桥驱动的视角，驱动加载子设备模块并以某种方式获得 v4l2_subdev -结构体指针。对于 i2c 总线设备相对简单：调用 i2c_get_clientdata()。 -对于其他总线也需要做类似的操作。针对 I2C 总线上的子设备辅助函数帮你 -完成了大部分复杂的工作。 - -每个 v4l2_subdev 都包含子设备驱动需要实现的函数指针（如果对此设备 -不适用，可为NULL）。由于子设备可完成许多不同的工作，而在一个庞大的 -函数指针结构体中通常仅有少数有用的函数实现其功能肯定不合适。所以， -函数指针根据其实现的功能被分类，每一类都有自己的函数指针结构体。 - -顶层函数指针结构体包含了指向各类函数指针结构体的指针，如果子设备驱动 -不支持该类函数中的任何一个功能，则指向该类结构体的指针为NULL。 - -这些结构体定义如下： - -struct v4l2_subdev_core_ops { - int (*g_chip_ident)(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip); - int (*log_status)(struct v4l2_subdev *sd); - int (*init)(struct v4l2_subdev *sd, u32 val); - ... -}; - -struct v4l2_subdev_tuner_ops { - ... -}; - -struct v4l2_subdev_audio_ops { - ... -}; - -struct v4l2_subdev_video_ops { - ... -}; - -struct v4l2_subdev_pad_ops { - ... -}; - -struct v4l2_subdev_ops { - const struct v4l2_subdev_core_ops *core; - const struct v4l2_subdev_tuner_ops *tuner; - const struct v4l2_subdev_audio_ops *audio; - const struct v4l2_subdev_video_ops *video; - const struct v4l2_subdev_pad_ops *video; -}; - -其中 core（核心）函数集通常可用于所有子设备，其他类别的实现依赖于 -子设备。如视频设备可能不支持音频操作函数，反之亦然。 - -这样的设置在限制了函数指针数量的同时，还使增加新的操作函数和分类 -变得较为容易。 - -子设备驱动可使用如下函数初始化 v4l2_subdev 结构体： - - v4l2_subdev_init(sd, &ops); - -然后，你必须用一个唯一的名字初始化 subdev->name，并初始化模块的 -owner 域。若使用 i2c 辅助函数，这些都会帮你处理好。 - -若需同媒体框架整合，你必须调用 media_entity_init() 初始化 v4l2_subdev -结构体中的 media_entity 结构体（entity 域）： - - struct media_pad *pads = &my_sd->pads; - int err; - - err = media_entity_init(&sd->entity, npads, pads, 0); - -pads 数组必须预先初始化。无须手动设置 media_entity 的 type 和 -name 域，但如有必要，revision 域必须初始化。 - -当（任何）子设备节点被打开/关闭，对 entity 的引用将被自动获取/释放。 - -在子设备被注销之后，不要忘记清理 media_entity 结构体： - - media_entity_cleanup(&sd->entity); - -如果子设备驱动趋向于处理视频并整合进了媒体框架，必须使用 v4l2_subdev_pad_ops -替代 v4l2_subdev_video_ops 实现格式相关的功能。 - -这种情况下，子设备驱动应该设置 link_validate 域，以提供它自身的链接 -验证函数。链接验证函数应对管道（两端链接的都是 V4L2 子设备）中的每个 -链接调用。驱动还要负责验证子设备和视频节点间格式配置的正确性。 - -如果 link_validate 操作没有设置，默认的 v4l2_subdev_link_validate_default() -函数将会被调用。这个函数保证宽、高和媒体总线像素格式在链接的收发两端 -都一致。子设备驱动除了它们自己的检测外，也可以自由使用这个函数以执行 -上面提到的检查。 - -设备（桥）驱动程序必须向 v4l2_device 注册 v4l2_subdev： - - int err = v4l2_device_register_subdev(v4l2_dev, sd); - -如果子设备模块在它注册前消失，这个操作可能失败。在这个函数成功返回后， -subdev->dev 域就指向了 v4l2_device。 - -如果 v4l2_device 父设备的 mdev 域为非 NULL 值，则子设备实体将被自动 -注册为媒体设备。 - -注销子设备则可用如下函数： - - v4l2_device_unregister_subdev(sd); - -此后，子设备模块就可卸载，且 sd->dev == NULL。 - -注册之设备后，可通过以下方式直接调用其操作函数： - - err = sd->ops->core->g_chip_ident(sd, &chip); - -但使用如下宏会比较容易且合适： - - err = v4l2_subdev_call(sd, core, g_chip_ident, &chip); - -这个宏将会做 NULL 指针检查，如果 subdev 为 NULL，则返回-ENODEV；如果 -subdev->core 或 subdev->core->g_chip_ident 为 NULL，则返回 -ENOIOCTLCMD； -否则将返回 subdev->ops->core->g_chip_ident ops 调用的实际结果。 - -有时也可能同时调用所有或一系列子设备的某个操作函数： - - v4l2_device_call_all(v4l2_dev, 0, core, g_chip_ident, &chip); - -任何不支持此操作的子设备都会被跳过，并忽略错误返回值。但如果你需要 -检查出错码，则可使用如下函数： - - err = v4l2_device_call_until_err(v4l2_dev, 0, core, g_chip_ident, &chip); - -除 -ENOIOCTLCMD 外的任何错误都会跳出循环并返回错误值。如果（除 -ENOIOCTLCMD -外）没有错误发生，则返回 0。 - -对于以上两个函数的第二个参数为组 ID。如果为 0，则所有子设备都会执行 -这个操作。如果为非 0 值，则只有那些组 ID 匹配的子设备才会执行此操作。 -在桥驱动注册一个子设备前，可以设置 sd->grp_id 为任何期望值（默认值为 -0）。这个值属于桥驱动，且子设备驱动将不会修改和使用它。 - -组 ID 赋予了桥驱动更多对于如何调用回调的控制。例如，电路板上有多个 -音频芯片，每个都有改变音量的能力。但当用户想要改变音量的时候，通常 -只有一个会被实际使用。你可以对这样的子设备设置组 ID 为（例如 AUDIO_CONTROLLER） -并在调用 v4l2_device_call_all() 时指定它为组 ID 值。这就保证了只有 -需要的子设备才会执行这个回调。 - -如果子设备需要通知它的 v4l2_device 父设备一个事件，可以调用 -v4l2_subdev_notify(sd, notification, arg)。这个宏检查是否有一个 -notify() 回调被注册，如果没有，返回 -ENODEV。否则返回 notify() 调用 -结果。 - -使用 v4l2_subdev 的好处在于它是一个通用结构体，且不包含任何底层硬件 -信息。所有驱动可以包含多个 I2C 总线的子设备，但也有子设备是通过 GPIO -控制。这个区别仅在配置设备时有关系，一旦子设备注册完成，对于 v4l2 -子系统来说就完全透明了。 - - -V4L2 子设备用户空间API --------------------- - -除了通过 v4l2_subdev_ops 结构导出的内核 API，V4L2 子设备也可以直接 -通过用户空间应用程序来控制。 - -可以在 /dev 中创建名为 v4l-subdevX 设备节点，以通过其直接访问子设备。 -如果子设备支持用户空间直接配置，必须在注册前设置 V4L2_SUBDEV_FL_HAS_DEVNODE -标志。 - -注册子设备之后， v4l2_device 驱动会通过调用 v4l2_device_register_subdev_nodes() -函数为所有已注册并设置了 V4L2_SUBDEV_FL_HAS_DEVNODE 的子设备创建 -设备节点。这些设备节点会在子设备注销时自动删除。 - -这些设备节点处理 V4L2 API 的一个子集。 - -VIDIOC_QUERYCTRL -VIDIOC_QUERYMENU -VIDIOC_G_CTRL -VIDIOC_S_CTRL -VIDIOC_G_EXT_CTRLS -VIDIOC_S_EXT_CTRLS -VIDIOC_TRY_EXT_CTRLS - - 这些 ioctls 控制与 V4L2 中定义的一致。他们行为相同，唯一的 - 不同是他们只处理子设备的控制实现。根据驱动程序，这些控制也 - 可以通过一个（或多个） V4L2 设备节点访问。 - -VIDIOC_DQEVENT -VIDIOC_SUBSCRIBE_EVENT -VIDIOC_UNSUBSCRIBE_EVENT - - 这些 ioctls 事件与 V4L2 中定义的一致。他们行为相同，唯一的 - 不同是他们只处理子设备产生的事件。根据驱动程序，这些事件也 - 可以通过一个（或多个） V4L2 设备节点上报。 - - 要使用事件通知的子设备驱动，在注册子设备前必须在 v4l2_subdev::flags - 中设置 V4L2_SUBDEV_USES_EVENTS 并在 v4l2_subdev::nevents - 中初始化事件队列深度。注册完成后，事件会在 v4l2_subdev::devnode - 设备节点中像通常一样被排队。 - - 为正确支持事件机制，poll() 文件操作也应被实现。 - -私有 ioctls - - 不在以上列表中的所有 ioctls 会通过 core::ioctl 操作直接传递 - 给子设备驱动。 - - -I2C 子设备驱动 -------------- - -由于这些驱动很常见，所以内特提供了特定的辅助函数(v4l2-common.h)让这些 -设备的使用更加容易。 - -添加 v4l2_subdev 支持的推荐方法是让 I2C 驱动将 v4l2_subdev 结构体 -嵌入到为每个 I2C 设备实例创建的状态结构体中。而最简单的设备没有状态 -结构体，此时可以直接创建一个 v4l2_subdev 结构体。 - -一个典型的状态结构体如下所示（‘chipname’用芯片名代替）： - -struct chipname_state { - struct v4l2_subdev sd; - ... /* 附加的状态域*/ -}; - -初始化 v4l2_subdev 结构体的方法如下： - - v4l2_i2c_subdev_init(&state->sd, client, subdev_ops); - -这个函数将填充 v4l2_subdev 结构体中的所有域，并保证 v4l2_subdev 和 -i2c_client 都指向彼此。 - -同时，你也应该为从 v4l2_subdev 指针找到 chipname_state 结构体指针 -添加一个辅助内联函数。 - -static inline struct chipname_state *to_state(struct v4l2_subdev *sd) -{ - return container_of(sd, struct chipname_state, sd); -} - -使用以下函数可以通过 v4l2_subdev 结构体指针获得 i2c_client 结构体 -指针： - - struct i2c_client *client = v4l2_get_subdevdata(sd); - -而以下函数则相反，通过 i2c_client 结构体指针获得 v4l2_subdev 结构体 -指针： - - struct v4l2_subdev *sd = i2c_get_clientdata(client); - -当 remove()函数被调用前，必须保证先调用 v4l2_device_unregister_subdev(sd)。 -此操作将会从桥驱动中注销子设备。即使子设备没有注册，调用此函数也是 -安全的。 - -必须这样做的原因是：当桥驱动注销 i2c 适配器时，remove()回调函数 -会被那个适配器上的 i2c 设备调用。此后，相应的 v4l2_subdev 结构体 -就不存在了，所有它们必须先被注销。在 remove()回调函数中调用 -v4l2_device_unregister_subdev(sd)，可以保证执行总是正确的。 - - -桥驱动也有一些辅组函数可用： - -struct v4l2_subdev *sd = v4l2_i2c_new_subdev(v4l2_dev, adapter, - "module_foo", "chipid", 0x36, NULL); - -这个函数会加载给定的模块（如果没有模块需要加载，可以为 NULL）， -并用给定的 i2c 适配器结构体指针（i2c_adapter）和 器件地址（chip/address） -作为参数调用 i2c_new_device()。如果一切顺利，则就在 v4l2_device -中注册了子设备。 - -你也可以利用 v4l2_i2c_new_subdev()的最后一个参数，传递一个可能的 -I2C 地址数组，让函数自动探测。这些探测地址只有在前一个参数为 0 的 -情况下使用。非零参数意味着你知道准确的 i2c 地址，所以此时无须进行 -探测。 - -如果出错，两个函数都返回 NULL。 - -注意：传递给 v4l2_i2c_new_subdev()的 chipid 通常与模块名一致。 -它允许你指定一个芯片的变体，比如“saa7114”或“saa7115”。一般通过 -i2c 驱动自动探测。chipid 的使用是在今后需要深入了解的事情。这个与 -i2c 驱动不同，较容易混淆。要知道支持哪些芯片变体，你可以查阅 i2c -驱动代码的 i2c_device_id 表，上面列出了所有可能支持的芯片。 - -还有两个辅助函数： - -v4l2_i2c_new_subdev_cfg：这个函数添加新的 irq 和 platform_data -参数，并有‘addr’和‘probed_addrs’参数：如果 addr 非零，则被使用 -（不探测变体），否则 probed_addrs 中的地址将用于自动探测。 - -例如：以下代码将会探测地址（0x10）： - -struct v4l2_subdev *sd = v4l2_i2c_new_subdev_cfg(v4l2_dev, adapter, - "module_foo", "chipid", 0, NULL, 0, I2C_ADDRS(0x10)); - -v4l2_i2c_new_subdev_board 使用一个 i2c_board_info 结构体，将其 -替代 irq、platform_data 和 add r参数传递给 i2c 驱动。 - -如果子设备支持 s_config 核心操作，这个操作会在子设备配置好之后以 irq 和 -platform_data 为参数调用。早期的 v4l2_i2c_new_(probed_)subdev 函数 -同样也会调用 s_config，但仅在 irq 为 0 且 platform_data 为 NULL 时。 - -video_device结构体 ------------------ - -在 /dev 目录下的实际设备节点根据 video_device 结构体(v4l2-dev.h) -创建。此结构体既可以动态分配也可以嵌入到一个更大的结构体中。 - -动态分配方法如下： - - struct video_device *vdev = video_device_alloc(); - - if (vdev == NULL) - return -ENOMEM; - - vdev->release = video_device_release; - -如果将其嵌入到一个大结构体中，则必须自己实现 release()回调。 - - struct video_device *vdev = &my_vdev->vdev; - - vdev->release = my_vdev_release; - -release()回调必须被设置，且在最后一个 video_device 用户退出之后 -被调用。 - -默认的 video_device_release()回调只是调用 kfree 来释放之前分配的 -内存。 - -你应该设置这些域： - -- v4l2_dev: 设置为 v4l2_device 父设备。 - -- name: 设置为唯一的描述性设备名。 - -- fops: 设置为已有的 v4l2_file_operations 结构体。 - -- ioctl_ops: 如果你使用v4l2_ioctl_ops 来简化 ioctl 的维护 - (强烈建议使用，且将来可能变为强制性的!)，然后设置你自己的 - v4l2_ioctl_ops 结构体. - -- lock: 如果你要在驱动中实现所有的锁操作，则设为 NULL 。否则 - 就要设置一个指向 struct mutex_lock 结构体的指针，这个锁将 - 在 unlocked_ioctl 文件操作被调用前由内核获得，并在调用返回后 - 释放。详见下一节。 - -- prio: 保持对优先级的跟踪。用于实现 VIDIOC_G/S_PRIORITY。如果 - 设置为 NULL，则会使用 v4l2_device 中的 v4l2_prio_state 结构体。 - 如果要对每个设备节点（组）实现独立的优先级，可以将其指向自己 - 实现的 v4l2_prio_state 结构体。 - -- parent: 仅在使用 NULL 作为父设备结构体参数注册 v4l2_device 时 - 设置此参数。只有在一个硬件设备包含多一个 PCI 设备，共享同一个 - v4l2_device 核心时才会发生。 - - cx88 驱动就是一个例子：一个 v4l2_device 结构体核心，被一个裸的 - 视频 PCI 设备(cx8800)和一个 MPEG PCI 设备(cx8802)共用。由于 - v4l2_device 无法与特定的 PCI 设备关联，所有没有设置父设备。但当 - video_device 配置后，就知道使用哪个父 PCI 设备了。 - -- flags：可选。如果你要让框架处理设置 VIDIOC_G/S_PRIORITY ioctls， - 请设置 V4L2_FL_USE_FH_PRIO。这要求你使用 v4l2_fh 结构体。 - 一旦所有驱动使用了核心的优先级处理，最终这个标志将消失。但现在它 - 必须被显式设置。 - -如果你使用 v4l2_ioctl_ops，则应该在 v4l2_file_operations 结构体中 -设置 .unlocked_ioctl 指向 video_ioctl2。 - -请勿使用 .ioctl！它已被废弃，今后将消失。 - -某些情况下你要告诉核心：你在 v4l2_ioctl_ops 指定的某个函数应被忽略。 -你可以在 video_device_register 被调用前通过以下函数标记这个 ioctls。 - -void v4l2_disable_ioctl(struct video_device *vdev, unsigned int cmd); - -基于外部因素（例如某个板卡已被使用），在不创建新结构体的情况下，你想 -要关闭 v4l2_ioctl_ops 中某个特性往往需要这个机制。 - -v4l2_file_operations 结构体是 file_operations 的一个子集。其主要 -区别在于：因 inode 参数从未被使用，它将被忽略。 - -如果需要与媒体框架整合，你必须通过调用 media_entity_init() 初始化 -嵌入在 video_device 结构体中的 media_entity（entity 域）结构体： - - struct media_pad *pad = &my_vdev->pad; - int err; - - err = media_entity_init(&vdev->entity, 1, pad, 0); - -pads 数组必须预先初始化。没有必要手动设置 media_entity 的 type 和 -name 域。 - -当（任何）子设备节点被打开/关闭，对 entity 的引用将被自动获取/释放。 - -v4l2_file_operations 与锁 --------------------------- - -你可以在 video_device 结构体中设置一个指向 mutex_lock 的指针。通常 -这既可是一个顶层互斥锁也可为设备节点自身的互斥锁。默认情况下，此锁 -用于 unlocked_ioctl，但为了使用 ioctls 你通过以下函数可禁用锁定： - - void v4l2_disable_ioctl_locking(struct video_device *vdev, unsigned int cmd); - -例如: v4l2_disable_ioctl_locking(vdev, VIDIOC_DQBUF); - -你必须在注册 video_device 前调用这个函数。 - -特别是对于 USB 驱动程序，某些命令（如设置控制）需要很长的时间，可能 -需要自行为缓冲区队列的 ioctls 实现锁定。 - -如果你需要更细粒度的锁，你必须设置 mutex_lock 为 NULL，并完全自己实现 -锁机制。 - -这完全由驱动开发者决定使用何种方法。然而，如果你的驱动存在长延时操作 -（例如，改变 USB 摄像头的曝光时间可能需要较长时间），而你又想让用户 -在等待长延时操作完成期间做其他的事，则你最好自己实现锁机制。 - -如果指定一个锁，则所有 ioctl 操作将在这个锁的作用下串行执行。如果你 -使用 videobuf，则必须将同一个锁传递给 videobuf 队列初始化函数；如 -videobuf 必须等待一帧的到达，则可临时解锁并在这之后重新上锁。如果驱动 -也在代码执行期间等待，则可做同样的工作（临时解锁，再上锁）让其他进程 -可以在第一个进程阻塞时访问设备节点。 - -在使用 videobuf2 的情况下，必须实现 wait_prepare 和 wait_finish 回调 -在适当的时候解锁/加锁。进一步来说，如果你在 video_device 结构体中使用 -锁，则必须在 wait_prepare 和 wait_finish 中对这个互斥锁进行解锁/加锁。 - -热插拔的断开实现也必须在调用 v4l2_device_disconnect 前获得锁。 - -video_device注册 ---------------- - -接下来你需要注册视频设备：这会为你创建一个字符设备。 - - err = video_register_device(vdev, VFL_TYPE_GRABBER, -1); - if (err) { - video_device_release(vdev); /* or kfree(my_vdev); */ - return err; - } - -如果 v4l2_device 父设备的 mdev 域为非 NULL 值，视频设备实体将自动 -注册为媒体设备。 - -注册哪种设备是根据类型（type）参数。存在以下类型： - -VFL_TYPE_GRABBER: 用于视频输入/输出设备的 videoX -VFL_TYPE_VBI: 用于垂直消隐数据的 vbiX (例如，隐藏式字幕，图文电视) -VFL_TYPE_RADIO: 用于广播调谐器的 radioX - -最后一个参数让你确定一个所控制设备的设备节点号数量(例如 videoX 中的 X)。 -通常你可以传入-1，让 v4l2 框架自己选择第一个空闲的编号。但是有时用户 -需要选择一个特定的节点号。驱动允许用户通过驱动模块参数选择一个特定的 -设备节点号是很普遍的。这个编号将会传递给这个函数，且 video_register_device -将会试图选择这个设备节点号。如果这个编号被占用，下一个空闲的设备节点 -编号将被选中，并向内核日志中发送一个警告信息。 - -另一个使用场景是当驱动创建多个设备时。这种情况下，对不同的视频设备在 -编号上使用不同的范围是很有用的。例如，视频捕获设备从 0 开始，视频 -输出设备从 16 开始。所以你可以使用最后一个参数来指定设备节点号最小值， -而 v4l2 框架会试图选择第一个的空闲编号（等于或大于你提供的编号）。 -如果失败，则它会就选择第一个空闲的编号。 - -由于这种情况下，你会忽略无法选择特定设备节点号的警告，则可调用 -video_register_device_no_warn() 函数避免警告信息的产生。 - -只要设备节点被创建，一些属性也会同时创建。在 /sys/class/video4linux -目录中你会找到这些设备。例如进入其中的 video0 目录，你会看到‘name’和 -‘index’属性。‘name’属性值就是 video_device 结构体中的‘name’域。 - -‘index’属性值就是设备节点的索引值：每次调用 video_register_device()， -索引值都递增 1 。第一个视频设备节点总是从索引值 0 开始。 - -用户可以设置 udev 规则，利用索引属性生成花哨的设备名（例如：用‘mpegX’ -代表 MPEG 视频捕获设备节点）。 - -在设备成功注册后，就可以使用这些域： - -- vfl_type: 传递给 video_register_device 的设备类型。 -- minor: 已指派的次设备号。 -- num: 设备节点编号 (例如 videoX 中的 X)。 -- index: 设备索引号。 - -如果注册失败，你必须调用 video_device_release() 来释放已分配的 -video_device 结构体；如果 video_device 是嵌入在自己创建的结构体中， -你也必须释放它。vdev->release() 回调不会在注册失败之后被调用， -你也不应试图在注册失败后注销设备。 - - -video_device 注销 ----------------- - -当视频设备节点已被移除，不论是卸载驱动还是USB设备断开，你都应注销 -它们： - - video_unregister_device(vdev); - -这个操作将从 sysfs 中移除设备节点（导致 udev 将其从 /dev 中移除）。 - -video_unregister_device() 返回之后，就无法完成打开操作。尽管如此， -USB 设备的情况则不同，某些应用程序可能依然打开着其中一个已注销设备 -节点。所以在注销之后，所有文件操作（当然除了 release ）也应返回错误值。 - -当最后一个视频设备节点的用户退出，则 vdev->release() 回调会被调用， -并且你可以做最后的清理操作。 - -不要忘记清理与视频设备相关的媒体入口（如果被初始化过）： - - media_entity_cleanup(&vdev->entity); - -这可以在 release 回调中完成。 - - -video_device 辅助函数 ---------------------- - -一些有用的辅助函数如下： - -- file/video_device 私有数据 - -你可以用以下函数在 video_device 结构体中设置/获取驱动私有数据： - -void *video_get_drvdata(struct video_device *vdev); -void video_set_drvdata(struct video_device *vdev, void *data); - -注意：在调用 video_register_device() 前执行 video_set_drvdata() -是安全的。 - -而以下函数： - -struct video_device *video_devdata(struct file *file); - -返回 file 结构体中拥有的的 video_device 指针。 - -video_drvdata 辅助函数结合了 video_get_drvdata 和 video_devdata -的功能： - -void *video_drvdata(struct file *file); - -你可以使用如下代码从 video_device 结构体中获取 v4l2_device 结构体 -指针： - -struct v4l2_device *v4l2_dev = vdev->v4l2_dev; - -- 设备节点名 - -video_device 设备节点在内核中的名称可以通过以下函数获得 - -const char *video_device_node_name(struct video_device *vdev); - -这个名字被用户空间工具（例如 udev）作为提示信息使用。应尽可能使用 -此功能，而非访问 video_device::num 和 video_device::minor 域。 - - -视频缓冲辅助函数 ---------------- - -v4l2 核心 API 提供了一个处理视频缓冲的标准方法(称为“videobuf”)。 -这些方法使驱动可以通过统一的方式实现 read()、mmap() 和 overlay()。 -目前在设备上支持视频缓冲的方法有分散/聚集 DMA(videobuf-dma-sg)、 -线性 DMA(videobuf-dma-contig)以及大多用于 USB 设备的用 vmalloc -分配的缓冲(videobuf-vmalloc)。 - -请参阅 Documentation/video4linux/videobuf，以获得更多关于 videobuf -层的使用信息。 - -v4l2_fh 结构体 -------------- - -v4l2_fh 结构体提供一个保存用于 V4L2 框架的文件句柄特定数据的简单方法。 -如果 video_device 的 flag 设置了 V4L2_FL_USE_FH_PRIO 标志，新驱动 -必须使用 v4l2_fh 结构体，因为它也用于实现优先级处理（VIDIOC_G/S_PRIORITY）。 - -v4l2_fh 的用户（位于 V4l2 框架中，并非驱动）可通过测试 -video_device->flags 中的 V4L2_FL_USES_V4L2_FH 位得知驱动是否使用 -v4l2_fh 作为他的 file->private_data 指针。这个位会在调用 v4l2_fh_init() -时被设置。 - -v4l2_fh 结构体作为驱动自身文件句柄结构体的一部分被分配，且驱动在 -其打开函数中将 file->private_data 指向它。 - -在许多情况下，v4l2_fh 结构体会嵌入到一个更大的结构体中。这钟情况下， -应该在 open() 中调用 v4l2_fh_init+v4l2_fh_add，并在 release() 中 -调用 v4l2_fh_del+v4l2_fh_exit。 - -驱动可以通过使用 container_of 宏提取他们自己的文件句柄结构体。例如： - -struct my_fh { - int blah; - struct v4l2_fh fh; -}; - -... - -int my_open(struct file *file) -{ - struct my_fh *my_fh; - struct video_device *vfd; - int ret; - - ... - - my_fh = kzalloc(sizeof(*my_fh), GFP_KERNEL); - - ... - - v4l2_fh_init(&my_fh->fh, vfd); - - ... - - file->private_data = &my_fh->fh; - v4l2_fh_add(&my_fh->fh); - return 0; -} - -int my_release(struct file *file) -{ - struct v4l2_fh *fh = file->private_data; - struct my_fh *my_fh = container_of(fh, struct my_fh, fh); - - ... - v4l2_fh_del(&my_fh->fh); - v4l2_fh_exit(&my_fh->fh); - kfree(my_fh); - return 0; -} - -以下是 v4l2_fh 函数使用的简介： - -void v4l2_fh_init(struct v4l2_fh *fh, struct video_device *vdev) - - 初始化文件句柄。这*必须*在驱动的 v4l2_file_operations->open() - 函数中执行。 - -void v4l2_fh_add(struct v4l2_fh *fh) - - 添加一个 v4l2_fh 到 video_device 文件句柄列表。一旦文件句柄 - 初始化完成就必须调用。 - -void v4l2_fh_del(struct v4l2_fh *fh) - - 从 video_device() 中解除文件句柄的关联。文件句柄的退出函数也 - 将被调用。 - -void v4l2_fh_exit(struct v4l2_fh *fh) - - 清理文件句柄。在清理完 v4l2_fh 后，相关内存会被释放。 - - -如果 v4l2_fh 不是嵌入在其他结构体中的，则可以用这些辅助函数： - -int v4l2_fh_open(struct file *filp) - - 分配一个 v4l2_fh 结构体空间，初始化并将其添加到 file 结构体相关的 - video_device 结构体中。 - -int v4l2_fh_release(struct file *filp) - - 从 file 结构体相关的 video_device 结构体中删除 v4l2_fh ，清理 - v4l2_fh 并释放空间。 - -这两个函数可以插入到 v4l2_file_operation 的 open() 和 release() -操作中。 - - -某些驱动需要在第一个文件句柄打开和最后一个文件句柄关闭的时候做些 -工作。所以加入了两个辅助函数以检查 v4l2_fh 结构体是否是相关设备 -节点打开的唯一文件句柄。 - -int v4l2_fh_is_singular(struct v4l2_fh *fh) - - 如果此文件句柄是唯一打开的文件句柄，则返回 1 ，否则返回 0 。 - -int v4l2_fh_is_singular_file(struct file *filp) - - 功能相同，但通过 filp->private_data 调用 v4l2_fh_is_singular。 - - -V4L2 事件机制 ------------ - -V4L2 事件机制提供了一个通用的方法将事件传递到用户空间。驱动必须使用 -v4l2_fh 才能支持 V4L2 事件机制。 - - -事件通过一个类型和选择 ID 来定义。ID 对应一个 V4L2 对象，例如 -一个控制 ID。如果未使用，则 ID 为 0。 - -当用户订阅一个事件，驱动会为此分配一些 kevent 结构体。所以每个 -事件组（类型、ID）都会有自己的一套 kevent 结构体。这保证了如果 -一个驱动短时间内产生了许多同类事件，不会覆盖其他类型的事件。 - -但如果你收到的事件数量大于同类事件 kevent 的保存数量，则最早的 -事件将被丢弃，并加入新事件。 - -此外，v4l2_subscribed_event 结构体内部有可供驱动设置的 merge() 和 -replace() 回调，这些回调会在新事件产生且没有多余空间的时候被调用。 -replace() 回调让你可以将早期事件的净荷替换为新事件的净荷，将早期 -净荷的相关数据合并到替换进来的新净荷中。当该类型的事件仅分配了一个 -kevent 结构体时，它将被调用。merge() 回调让你可以合并最早的事件净荷 -到在它之后的那个事件净荷中。当该类型的事件分配了两个或更多 kevent -结构体时，它将被调用。 - -这种方法不会有状态信息丢失，只会导致中间步骤信息丢失。 - - -关于 replace/merge 回调的一个不错的例子在 v4l2-event.c 中：用于 -控制事件的 ctrls_replace() 和 ctrls_merge() 回调。 - -注意：这些回调可以在中断上下文中调用，所以它们必须尽快完成并退出。 - -有用的函数： - -void v4l2_event_queue(struct video_device *vdev, const struct v4l2_event *ev) - - 将事件加入视频设备的队列。驱动仅负责填充 type 和 data 域。 - 其他域由 V4L2 填充。 - -int v4l2_event_subscribe(struct v4l2_fh *fh, - struct v4l2_event_subscription *sub, unsigned elems, - const struct v4l2_subscribed_event_ops *ops) - - video_device->ioctl_ops->vidioc_subscribe_event 必须检测驱动能 - 产生特定 id 的事件。然后调用 v4l2_event_subscribe() 来订阅该事件。 - - elems 参数是该事件的队列大小。若为 0，V4L2 框架将会（根据事件类型） - 填充默认值。 - - ops 参数允许驱动指定一系列回调： - * add: 当添加一个新监听者时调用（重复订阅同一个事件，此回调 - 仅被执行一次）。 - * del: 当一个监听者停止监听时调用。 - * replace: 用‘新’事件替换‘早期‘事件。 - * merge: 将‘早期‘事件合并到‘新’事件中。 - 这四个调用都是可选的，如果不想指定任何回调，则 ops 可为 NULL。 - -int v4l2_event_unsubscribe(struct v4l2_fh *fh, - struct v4l2_event_subscription *sub) - - v4l2_ioctl_ops 结构体中的 vidioc_unsubscribe_event 回调函数。 - 驱动程序可以直接使用 v4l2_event_unsubscribe() 实现退订事件过程。 - - 特殊的 V4L2_EVENT_ALL 类型，可用于退订所有事件。驱动可能在特殊 - 情况下需要做此操作。 - -int v4l2_event_pending(struct v4l2_fh *fh) - - 返回未决事件的数量。有助于实现轮询（poll）操作。 - -事件通过 poll 系统调用传递到用户空间。驱动可用 -v4l2_fh->wait (wait_queue_head_t 类型)作为参数调用 poll_wait()。 - -事件分为标准事件和私有事件。新的标准事件必须使用可用的最小事件类型 -编号。驱动必须从他们本类型的编号起始处分配事件。类型的编号起始为 -V4L2_EVENT_PRIVATE_START + n * 1000 ，其中 n 为可用最小编号。每个 -类型中的第一个事件类型编号是为以后的使用保留的，所以第一个可用事件 -类型编号是‘class base + 1’。 - -V4L2 事件机制的使用实例可以在 OMAP3 ISP 的驱动 -(drivers/media/video/omap3isp)中找到。 diff --git a/trunk/MAINTAINERS b/trunk/MAINTAINERS index 8443eda055dd..94b823f71e94 100644 --- a/trunk/MAINTAINERS +++ b/trunk/MAINTAINERS @@ -595,6 +595,7 @@ M: Will Deacon S: Maintained F: arch/arm/kernel/perf_event* F: arch/arm/oprofile/common.c +F: arch/arm/kernel/pmu.c F: arch/arm/include/asm/pmu.h F: arch/arm/kernel/hw_breakpoint.c F: arch/arm/include/asm/hw_breakpoint.h @@ -826,24 +827,24 @@ F: arch/arm/mach-pxa/colibri-pxa270-income.c ARM/INTEL IOP32X ARM ARCHITECTURE M: Lennert Buytenhek -M: Dan Williams +M: Dan Williams L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained ARM/INTEL IOP33X ARM ARCHITECTURE -M: Dan Williams +M: Dan Williams L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained ARM/INTEL IOP13XX ARM ARCHITECTURE M: Lennert Buytenhek -M: Dan Williams +M: Dan Williams L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained ARM/INTEL IQ81342EX MACHINE SUPPORT M: Lennert Buytenhek -M: Dan Williams +M: Dan Williams L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained @@ -868,7 +869,7 @@ F: drivers/pcmcia/pxa2xx_stargate2.c ARM/INTEL XSC3 (MANZANO) ARM CORE M: Lennert Buytenhek -M: Dan Williams +M: Dan Williams L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained @@ -912,12 +913,6 @@ W: http://www.digriz.org.uk/ts78xx/kernel S: Maintained F: arch/arm/mach-orion5x/ts78xx-* -ARM/MICREL KS8695 ARCHITECTURE -M: Greg Ungerer -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -F: arch/arm/mach-ks8695 -S: Odd Fixes - ARM/MIOA701 MACHINE SUPPORT M: Robert Jarzmik L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -930,14 +925,14 @@ S: Maintained ARM/NOMADIK ARCHITECTURE M: Alessandro Rubini -M: Linus Walleij +M: Linus Walleij M: STEricsson L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-nomadik/ F: arch/arm/plat-nomadik/ F: drivers/i2c/busses/i2c-nomadik.c -T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT M: Nelson Castillo @@ -1151,7 +1146,7 @@ F: drivers/usb/host/ehci-w90x900.c F: drivers/video/nuc900fb.c ARM/U300 MACHINE SUPPORT -M: Linus Walleij +M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported F: arch/arm/mach-u300/ @@ -1166,20 +1161,15 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git ARM/Ux500 ARM ARCHITECTURE M: Srinidhi Kasagar -M: Linus Walleij +M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-ux500/ -F: drivers/clocksource/clksrc-dbx500-prcmu.c F: drivers/dma/ste_dma40* -F: drivers/hwspinlock/u8500_hsem.c F: drivers/mfd/abx500* F: drivers/mfd/ab8500* -F: drivers/mfd/dbx500* -F: drivers/mfd/db8500* -F: drivers/pinctrl/pinctrl-nomadik* +F: drivers/mfd/stmpe* F: drivers/rtc/rtc-ab8500.c -F: drivers/rtc/rtc-pl031.c T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git ARM/VFP SUPPORT @@ -1214,12 +1204,6 @@ S: Maintained F: arch/arm/mach-pxa/z2.c F: arch/arm/mach-pxa/include/mach/z2.h -ARM64 PORT (AARCH64 ARCHITECTURE) -M: Catalin Marinas -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm64/ - ASC7621 HARDWARE MONITOR DRIVER M: George Joseph L: lm-sensors@lm-sensors.org @@ -1243,9 +1227,9 @@ S: Maintained F: drivers/hwmon/asb100.c ASYNCHRONOUS TRANSFERS/TRANSFORMS (IOAT) API -M: Dan Williams +M: Dan Williams W: http://sourceforge.net/projects/xscaleiop -S: Maintained +S: Supported F: Documentation/crypto/async-tx-api.txt F: crypto/async_tx/ F: drivers/dma/ @@ -2228,7 +2212,7 @@ S: Maintained F: drivers/scsi/tmscsim.* DC395x SCSI driver -M: Oliver Neukum +M: Oliver Neukum M: Ali Akcaagac M: Jamie Lenehan W: http://twibble.org/dist/dc395x/ @@ -2375,7 +2359,7 @@ T: git git://git.linaro.org/people/sumitsemwal/linux-dma-buf.git DMA GENERIC OFFLOAD ENGINE SUBSYSTEM M: Vinod Koul -M: Dan Williams +M: Dan Williams S: Supported F: drivers/dma/ F: include/linux/dma* @@ -2870,9 +2854,7 @@ F: include/linux/firewire*.h F: tools/firewire/ FIRMWARE LOADER (request_firmware) -M: Ming Lei -L: linux-kernel@vger.kernel.org -S: Maintained +S: Orphan F: Documentation/firmware_class/ F: drivers/base/firmware*.c F: include/linux/firmware.h @@ -3112,7 +3094,7 @@ F: include/linux/gigaset_dev.h GPIO SUBSYSTEM M: Grant Likely -M: Linus Walleij +M: Linus Walleij S: Maintained T: git git://git.secretlab.ca/git/linux-2.6.git F: Documentation/gpio.txt @@ -3401,7 +3383,7 @@ M: "Wolfram Sang (embedded platforms)" L: linux-i2c@vger.kernel.org W: http://i2c.wiki.kernel.org/ T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-i2c/ -T: git git://git.pengutronix.de/git/wsa/linux.git +T: git git://git.fluff.org/bjdooks/linux.git S: Maintained F: Documentation/i2c/ F: drivers/i2c/ @@ -3565,12 +3547,12 @@ K: \b(ABS|SYN)_MT_ INTEL C600 SERIES SAS CONTROLLER DRIVER M: Intel SCU Linux support -M: Lukasz Dorau -M: Maciej Patelczyk +M: Dan Williams M: Dave Jiang +M: Ed Nadolski L: linux-scsi@vger.kernel.org -T: git git://git.code.sf.net/p/intel-sas/isci -S: Supported +T: git git://git.kernel.org/pub/scm/linux/kernel/git/djbw/isci.git +S: Maintained F: drivers/scsi/isci/ F: firmware/isci/ @@ -3608,8 +3590,8 @@ F: arch/x86/kernel/microcode_core.c F: arch/x86/kernel/microcode_intel.c INTEL I/OAT DMA DRIVER -M: Dan Williams -S: Maintained +M: Dan Williams +S: Supported F: drivers/dma/ioat* INTEL IOMMU (VT-d) @@ -3621,8 +3603,8 @@ F: drivers/iommu/intel-iommu.c F: include/linux/intel-iommu.h INTEL IOP-ADMA DMA DRIVER -M: Dan Williams -S: Odd fixes +M: Dan Williams +S: Maintained F: drivers/dma/iop-adma.c INTEL IXP4XX QMGR, NPE, ETHERNET and HSS SUPPORT @@ -3680,12 +3662,11 @@ F: Documentation/networking/README.ipw2200 F: drivers/net/wireless/ipw2x00/ INTEL(R) TRUSTED EXECUTION TECHNOLOGY (TXT) -M: Richard L Maliszewski -M: Gang Wei +M: Joseph Cihula M: Shane Wang L: tboot-devel@lists.sourceforge.net W: http://tboot.sourceforge.net -T: hg http://tboot.hg.sourceforge.net:8000/hgroot/tboot/tboot +T: Mercurial http://www.bughost.org/repos.hg/tboot.hg S: Supported F: Documentation/intel_txt.txt F: include/linux/tboot.h @@ -4552,7 +4533,7 @@ S: Supported F: arch/microblaze/ MICROTEK X6 SCANNER -M: Oliver Neukum +M: Oliver Neukum S: Maintained F: drivers/usb/image/microtek.* @@ -5335,12 +5316,6 @@ L: linux-mtd@lists.infradead.org S: Maintained F: drivers/mtd/devices/phram.c -PICOLCD HID DRIVER -M: Bruno Prémont -L: linux-input@vger.kernel.org -S: Maintained -F: drivers/hid/hid-picolcd* - PICOXCELL SUPPORT M: Jamie Iles L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -5354,15 +5329,14 @@ PIN CONTROL SUBSYSTEM M: Linus Walleij S: Maintained F: drivers/pinctrl/ -F: include/linux/pinctrl/ PIN CONTROLLER - ST SPEAR -M: Viresh Kumar +M: Viresh Kumar L: spear-devel@list.st.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) W: http://www.st.com/spear S: Maintained -F: drivers/pinctrl/spear/ +F: driver/pinctrl/spear/ PKTCDVD DRIVER M: Peter Osterlund @@ -5564,8 +5538,6 @@ F: Documentation/devicetree/bindings/pwm/ F: include/linux/pwm.h F: include/linux/of_pwm.h F: drivers/pwm/ -F: drivers/video/backlight/pwm_bl.c -F: include/linux/pwm_backlight.h PXA2xx/PXA3xx SUPPORT M: Eric Miao @@ -6799,14 +6771,14 @@ F: drivers/net/team/ F: include/linux/if_team.h TEGRA SUPPORT +M: Colin Cross +M: Olof Johansson M: Stephen Warren L: linux-tegra@vger.kernel.org Q: http://patchwork.ozlabs.org/project/linux-tegra/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git S: Supported F: arch/arm/mach-tegra -F: arch/arm/boot/dts/tegra* -F: arch/arm/configs/tegra_defconfig TEHUTI ETHERNET DRIVER M: Andy Gospodarek @@ -7099,7 +7071,7 @@ F: include/linux/mtd/ubi.h F: include/mtd/ubi-user.h USB ACM DRIVER -M: Oliver Neukum +M: Oliver Neukum L: linux-usb@vger.kernel.org S: Maintained F: Documentation/usb/acm.txt @@ -7120,7 +7092,7 @@ S: Supported F: drivers/block/ub.c USB CDC ETHERNET DRIVER -M: Oliver Neukum +M: Oliver Neukum L: linux-usb@vger.kernel.org S: Maintained F: drivers/net/usb/cdc_*.c @@ -7193,7 +7165,7 @@ F: drivers/usb/host/isp116x* F: include/linux/usb/isp116x.h USB KAWASAKI LSI DRIVER -M: Oliver Neukum +M: Oliver Neukum L: linux-usb@vger.kernel.org S: Maintained F: drivers/usb/serial/kl5kusb105.* @@ -7311,12 +7283,6 @@ W: http://www.connecttech.com S: Supported F: drivers/usb/serial/whiteheat* -USB SMSC75XX ETHERNET DRIVER -M: Steve Glendinning -L: netdev@vger.kernel.org -S: Maintained -F: drivers/net/usb/smsc75xx.* - USB SMSC95XX ETHERNET DRIVER M: Steve Glendinning L: netdev@vger.kernel.org @@ -7699,28 +7665,23 @@ S: Supported F: Documentation/hwmon/wm83?? F: arch/arm/mach-s3c64xx/mach-crag6410* F: drivers/clk/clk-wm83*.c -F: drivers/extcon/extcon-arizona.c F: drivers/leds/leds-wm83*.c F: drivers/gpio/gpio-*wm*.c -F: drivers/gpio/gpio-arizona.c F: drivers/hwmon/wm83??-hwmon.c F: drivers/input/misc/wm831x-on.c F: drivers/input/touchscreen/wm831x-ts.c F: drivers/input/touchscreen/wm97*.c -F: drivers/mfd/arizona* -F: drivers/mfd/wm*.c +F: drivers/mfd/wm8*.c F: drivers/power/wm83*.c F: drivers/rtc/rtc-wm83*.c F: drivers/regulator/wm8*.c F: drivers/video/backlight/wm83*_bl.c F: drivers/watchdog/wm83*_wdt.c -F: include/linux/mfd/arizona/ F: include/linux/mfd/wm831x/ F: include/linux/mfd/wm8350/ F: include/linux/mfd/wm8400* F: include/linux/wm97xx.h F: include/sound/wm????.h -F: sound/soc/codecs/arizona.? F: sound/soc/codecs/wm* WORKQUEUE diff --git a/trunk/Makefile b/trunk/Makefile index 846dd7607854..ddf5be952e45 100644 --- a/trunk/Makefile +++ b/trunk/Makefile @@ -1,8 +1,8 @@ VERSION = 3 PATCHLEVEL = 6 SUBLEVEL = 0 -EXTRAVERSION = -NAME = Terrified Chipmunk +EXTRAVERSION = -rc1 +NAME = Saber-toothed Squirrel # *DOCUMENTATION* # To see a list of typical targets execute "make help" @@ -609,11 +609,7 @@ KBUILD_CFLAGS += $(call cc-option, -femit-struct-debug-baseonly) endif ifdef CONFIG_FUNCTION_TRACER -ifdef CONFIG_HAVE_FENTRY -CC_USING_FENTRY := $(call cc-option, -mfentry -DCC_USING_FENTRY) -endif -KBUILD_CFLAGS += -pg $(CC_USING_FENTRY) -KBUILD_AFLAGS += $(CC_USING_FENTRY) +KBUILD_CFLAGS += -pg ifdef CONFIG_DYNAMIC_FTRACE ifdef CONFIG_HAVE_C_RECORDMCOUNT BUILD_C_RECORDMCOUNT := y diff --git a/trunk/arch/Kconfig b/trunk/arch/Kconfig index a62965d057f6..72f2fa189cc5 100644 --- a/trunk/arch/Kconfig +++ b/trunk/arch/Kconfig @@ -222,19 +222,6 @@ config HAVE_PERF_EVENTS_NMI subsystem. Also has support for calculating CPU cycle events to determine how many clock cycles in a given period. -config HAVE_PERF_REGS - bool - help - Support selective register dumps for perf events. This includes - bit-mapping of each registers and a unique architecture id. - -config HAVE_PERF_USER_STACK_DUMP - bool - help - Support user stack dumps for perf event samples. This needs - access to the user stack pointer which is not unified across - architectures. - config HAVE_ARCH_JUMP_LABEL bool @@ -294,23 +281,4 @@ config SECCOMP_FILTER See Documentation/prctl/seccomp_filter.txt for details. -config HAVE_RCU_USER_QS - bool - help - Provide kernel entry/exit hooks necessary for userspace - RCU extended quiescent state. Syscalls need to be wrapped inside - rcu_user_exit()-rcu_user_enter() through the slow path using - TIF_NOHZ flag. Exceptions handlers must be wrapped as well. Irqs - are already protected inside rcu_irq_enter/rcu_irq_exit() but - preemption or signal handling on irq exit still need to be protected. - -config HAVE_VIRT_CPU_ACCOUNTING - bool - -config HAVE_IRQ_TIME_ACCOUNTING - bool - help - Archs need to ensure they use a high enough resolution clock to - support irq time accounting and then call enable_sched_clock_irqtime(). - source "kernel/gcov/Kconfig" diff --git a/trunk/arch/alpha/Kconfig b/trunk/arch/alpha/Kconfig index 9944dedee5b1..d5b9b5e645cc 100644 --- a/trunk/arch/alpha/Kconfig +++ b/trunk/arch/alpha/Kconfig @@ -18,8 +18,6 @@ config ALPHA select ARCH_HAVE_NMI_SAFE_CMPXCHG select GENERIC_SMP_IDLE_THREAD select GENERIC_CMOS_UPDATE - select GENERIC_STRNCPY_FROM_USER - select GENERIC_STRNLEN_USER help The Alpha is a 64-bit general-purpose processor designed and marketed by the Digital Equipment Corporation of blessed memory, diff --git a/trunk/arch/alpha/include/asm/atomic.h b/trunk/arch/alpha/include/asm/atomic.h index c2cbe4fc391c..3bb7ffeae3bc 100644 --- a/trunk/arch/alpha/include/asm/atomic.h +++ b/trunk/arch/alpha/include/asm/atomic.h @@ -14,8 +14,8 @@ */ -#define ATOMIC_INIT(i) { (i) } -#define ATOMIC64_INIT(i) { (i) } +#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) +#define ATOMIC64_INIT(i) ( (atomic64_t) { (i) } ) #define atomic_read(v) (*(volatile int *)&(v)->counter) #define atomic64_read(v) (*(volatile long *)&(v)->counter) diff --git a/trunk/arch/alpha/include/asm/fpu.h b/trunk/arch/alpha/include/asm/fpu.h index e477bcd5b94a..db00f7885faa 100644 --- a/trunk/arch/alpha/include/asm/fpu.h +++ b/trunk/arch/alpha/include/asm/fpu.h @@ -1,9 +1,7 @@ #ifndef __ASM_ALPHA_FPU_H #define __ASM_ALPHA_FPU_H -#ifdef __KERNEL__ #include -#endif /* * Alpha floating-point control register defines: diff --git a/trunk/arch/alpha/include/asm/ptrace.h b/trunk/arch/alpha/include/asm/ptrace.h index b87755a19554..fd698a174f26 100644 --- a/trunk/arch/alpha/include/asm/ptrace.h +++ b/trunk/arch/alpha/include/asm/ptrace.h @@ -76,10 +76,7 @@ struct switch_stack { #define task_pt_regs(task) \ ((struct pt_regs *) (task_stack_page(task) + 2*PAGE_SIZE) - 1) -#define current_pt_regs() \ - ((struct pt_regs *) ((char *)current_thread_info() + 2*PAGE_SIZE) - 1) - -#define force_successful_syscall_return() (current_pt_regs()->r0 = 0) +#define force_successful_syscall_return() (task_pt_regs(current)->r0 = 0) #endif diff --git a/trunk/arch/alpha/include/asm/socket.h b/trunk/arch/alpha/include/asm/socket.h index 7d2f75be932e..dcb221a4b5be 100644 --- a/trunk/arch/alpha/include/asm/socket.h +++ b/trunk/arch/alpha/include/asm/socket.h @@ -76,11 +76,9 @@ /* Instruct lower device to use last 4-bytes of skb data as FCS */ #define SO_NOFCS 43 -#ifdef __KERNEL__ /* O_NONBLOCK clashes with the bits used for socket types. Therefore we * have to define SOCK_NONBLOCK to a different value here. */ #define SOCK_NONBLOCK 0x40000000 -#endif /* __KERNEL__ */ #endif /* _ASM_SOCKET_H */ diff --git a/trunk/arch/alpha/include/asm/uaccess.h b/trunk/arch/alpha/include/asm/uaccess.h index 766fdfde2b7a..b49ec2f8d6e3 100644 --- a/trunk/arch/alpha/include/asm/uaccess.h +++ b/trunk/arch/alpha/include/asm/uaccess.h @@ -433,12 +433,36 @@ clear_user(void __user *to, long len) #undef __module_address #undef __module_call -#define user_addr_max() \ - (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL) +/* Returns: -EFAULT if exception before terminator, N if the entire + buffer filled, else strlen. */ -extern long strncpy_from_user(char *dest, const char __user *src, long count); -extern __must_check long strlen_user(const char __user *str); -extern __must_check long strnlen_user(const char __user *str, long n); +extern long __strncpy_from_user(char *__to, const char __user *__from, long __to_len); + +extern inline long +strncpy_from_user(char *to, const char __user *from, long n) +{ + long ret = -EFAULT; + if (__access_ok((unsigned long)from, 0, get_fs())) + ret = __strncpy_from_user(to, from, n); + return ret; +} + +/* Returns: 0 if bad, string length+1 (memory size) of string if ok */ +extern long __strlen_user(const char __user *); + +extern inline long strlen_user(const char __user *str) +{ + return access_ok(VERIFY_READ,str,0) ? __strlen_user(str) : 0; +} + +/* Returns: 0 if exception before NUL or reaching the supplied limit (N), + * a value greater than N if the limit would be exceeded, else strlen. */ +extern long __strnlen_user(const char __user *, long); + +extern inline long strnlen_user(const char __user *str, long n) +{ + return access_ok(VERIFY_READ,str,0) ? __strnlen_user(str, n) : 0; +} /* * About the exception table: diff --git a/trunk/arch/alpha/include/asm/unistd.h b/trunk/arch/alpha/include/asm/unistd.h index a31a78eac9b9..633b23b0664a 100644 --- a/trunk/arch/alpha/include/asm/unistd.h +++ b/trunk/arch/alpha/include/asm/unistd.h @@ -465,12 +465,10 @@ #define __NR_setns 501 #define __NR_accept4 502 #define __NR_sendmmsg 503 -#define __NR_process_vm_readv 504 -#define __NR_process_vm_writev 505 #ifdef __KERNEL__ -#define NR_SYSCALLS 506 +#define NR_SYSCALLS 504 #define __ARCH_WANT_OLD_READDIR #define __ARCH_WANT_STAT64 diff --git a/trunk/arch/alpha/include/asm/word-at-a-time.h b/trunk/arch/alpha/include/asm/word-at-a-time.h deleted file mode 100644 index 6b340d0f1521..000000000000 --- a/trunk/arch/alpha/include/asm/word-at-a-time.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef _ASM_WORD_AT_A_TIME_H -#define _ASM_WORD_AT_A_TIME_H - -#include - -/* - * word-at-a-time interface for Alpha. - */ - -/* - * We do not use the word_at_a_time struct on Alpha, but it needs to be - * implemented to humour the generic code. - */ -struct word_at_a_time { - const unsigned long unused; -}; - -#define WORD_AT_A_TIME_CONSTANTS { 0 } - -/* Return nonzero if val has a zero */ -static inline unsigned long has_zero(unsigned long val, unsigned long *bits, const struct word_at_a_time *c) -{ - unsigned long zero_locations = __kernel_cmpbge(0, val); - *bits = zero_locations; - return zero_locations; -} - -static inline unsigned long prep_zero_mask(unsigned long val, unsigned long bits, const struct word_at_a_time *c) -{ - return bits; -} - -#define create_zero_mask(bits) (bits) - -static inline unsigned long find_zero(unsigned long bits) -{ -#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67) - /* Simple if have CIX instructions */ - return __kernel_cttz(bits); -#else - unsigned long t1, t2, t3; - /* Retain lowest set bit only */ - bits &= -bits; - /* Binary search for lowest set bit */ - t1 = bits & 0xf0; - t2 = bits & 0xcc; - t3 = bits & 0xaa; - if (t1) t1 = 4; - if (t2) t2 = 2; - if (t3) t3 = 1; - return t1 + t2 + t3; -#endif -} - -#endif /* _ASM_WORD_AT_A_TIME_H */ diff --git a/trunk/arch/alpha/kernel/alpha_ksyms.c b/trunk/arch/alpha/kernel/alpha_ksyms.c index 15fa821d09cd..d96e742d4dc2 100644 --- a/trunk/arch/alpha/kernel/alpha_ksyms.c +++ b/trunk/arch/alpha/kernel/alpha_ksyms.c @@ -52,6 +52,7 @@ EXPORT_SYMBOL(alpha_write_fp_reg_s); /* entry.S */ EXPORT_SYMBOL(kernel_thread); +EXPORT_SYMBOL(kernel_execve); /* Networking helper routines. */ EXPORT_SYMBOL(csum_tcpudp_magic); @@ -73,6 +74,8 @@ EXPORT_SYMBOL(alpha_fp_emul); */ EXPORT_SYMBOL(__copy_user); EXPORT_SYMBOL(__do_clear_user); +EXPORT_SYMBOL(__strncpy_from_user); +EXPORT_SYMBOL(__strnlen_user); /* * SMP-specific symbols. diff --git a/trunk/arch/alpha/kernel/entry.S b/trunk/arch/alpha/kernel/entry.S index ec0da0567ab5..6d159cee5f2f 100644 --- a/trunk/arch/alpha/kernel/entry.S +++ b/trunk/arch/alpha/kernel/entry.S @@ -663,6 +663,58 @@ kernel_thread: br ret_to_kernel .end kernel_thread +/* + * kernel_execve(path, argv, envp) + */ + .align 4 + .globl kernel_execve + .ent kernel_execve +kernel_execve: + /* We can be called from a module. */ + ldgp $gp, 0($27) + lda $sp, -(32+SIZEOF_PT_REGS+8)($sp) + .frame $sp, 32+SIZEOF_PT_REGS+8, $26, 0 + stq $26, 0($sp) + stq $16, 8($sp) + stq $17, 16($sp) + stq $18, 24($sp) + .prologue 1 + + lda $16, 32($sp) + lda $17, 0 + lda $18, SIZEOF_PT_REGS + bsr $26, memset !samegp + + /* Avoid the HAE being gratuitously wrong, which would cause us + to do the whole turn off interrupts thing and restore it. */ + ldq $2, alpha_mv+HAE_CACHE + stq $2, 152+32($sp) + + ldq $16, 8($sp) + ldq $17, 16($sp) + ldq $18, 24($sp) + lda $19, 32($sp) + bsr $26, do_execve !samegp + + ldq $26, 0($sp) + bne $0, 1f /* error! */ + + /* Move the temporary pt_regs struct from its current location + to the top of the kernel stack frame. See copy_thread for + details for a normal process. */ + lda $16, 0x4000 - SIZEOF_PT_REGS($8) + lda $17, 32($sp) + lda $18, SIZEOF_PT_REGS + bsr $26, memmove !samegp + + /* Take that over as our new stack frame and visit userland! */ + lda $sp, 0x4000 - SIZEOF_PT_REGS($8) + br $31, ret_from_sys_call + +1: lda $sp, 32+SIZEOF_PT_REGS+8($sp) + ret +.end kernel_execve + /* * Special system calls. Most of these are special in that they either @@ -744,6 +796,115 @@ sys_rt_sigreturn: br ret_from_sys_call .end sys_rt_sigreturn + .align 4 + .globl sys_sethae + .ent sys_sethae +sys_sethae: + .prologue 0 + stq $16, 152($sp) + ret +.end sys_sethae + + .align 4 + .globl osf_getpriority + .ent osf_getpriority +osf_getpriority: + lda $sp, -16($sp) + stq $26, 0($sp) + .prologue 0 + + jsr $26, sys_getpriority + + ldq $26, 0($sp) + blt $0, 1f + + /* Return value is the unbiased priority, i.e. 20 - prio. + This does result in negative return values, so signal + no error by writing into the R0 slot. */ + lda $1, 20 + stq $31, 16($sp) + subl $1, $0, $0 + unop + +1: lda $sp, 16($sp) + ret +.end osf_getpriority + + .align 4 + .globl sys_getxuid + .ent sys_getxuid +sys_getxuid: + .prologue 0 + ldq $2, TI_TASK($8) + ldq $3, TASK_CRED($2) + ldl $0, CRED_UID($3) + ldl $1, CRED_EUID($3) + stq $1, 80($sp) + ret +.end sys_getxuid + + .align 4 + .globl sys_getxgid + .ent sys_getxgid +sys_getxgid: + .prologue 0 + ldq $2, TI_TASK($8) + ldq $3, TASK_CRED($2) + ldl $0, CRED_GID($3) + ldl $1, CRED_EGID($3) + stq $1, 80($sp) + ret +.end sys_getxgid + + .align 4 + .globl sys_getxpid + .ent sys_getxpid +sys_getxpid: + .prologue 0 + ldq $2, TI_TASK($8) + + /* See linux/kernel/timer.c sys_getppid for discussion + about this loop. */ + ldq $3, TASK_GROUP_LEADER($2) + ldq $4, TASK_REAL_PARENT($3) + ldl $0, TASK_TGID($2) +1: ldl $1, TASK_TGID($4) +#ifdef CONFIG_SMP + mov $4, $5 + mb + ldq $3, TASK_GROUP_LEADER($2) + ldq $4, TASK_REAL_PARENT($3) + cmpeq $4, $5, $5 + beq $5, 1b +#endif + stq $1, 80($sp) + ret +.end sys_getxpid + + .align 4 + .globl sys_alpha_pipe + .ent sys_alpha_pipe +sys_alpha_pipe: + lda $sp, -16($sp) + stq $26, 0($sp) + .prologue 0 + + mov $31, $17 + lda $16, 8($sp) + jsr $26, do_pipe_flags + + ldq $26, 0($sp) + bne $0, 1f + + /* The return values are in $0 and $20. */ + ldl $1, 12($sp) + ldl $0, 8($sp) + + stq $1, 80+16($sp) +1: lda $sp, 16($sp) + ret +.end sys_alpha_pipe + .align 4 .globl sys_execve .ent sys_execve diff --git a/trunk/arch/alpha/kernel/osf_sys.c b/trunk/arch/alpha/kernel/osf_sys.c index bc1acdda7a5e..98a103621af6 100644 --- a/trunk/arch/alpha/kernel/osf_sys.c +++ b/trunk/arch/alpha/kernel/osf_sys.c @@ -1404,52 +1404,3 @@ SYSCALL_DEFINE3(osf_writev, unsigned long, fd, } #endif - -SYSCALL_DEFINE2(osf_getpriority, int, which, int, who) -{ - int prio = sys_getpriority(which, who); - if (prio >= 0) { - /* Return value is the unbiased priority, i.e. 20 - prio. - This does result in negative return values, so signal - no error */ - force_successful_syscall_return(); - prio = 20 - prio; - } - return prio; -} - -SYSCALL_DEFINE0(getxuid) -{ - current_pt_regs()->r20 = sys_geteuid(); - return sys_getuid(); -} - -SYSCALL_DEFINE0(getxgid) -{ - current_pt_regs()->r20 = sys_getegid(); - return sys_getgid(); -} - -SYSCALL_DEFINE0(getxpid) -{ - current_pt_regs()->r20 = sys_getppid(); - return sys_getpid(); -} - -SYSCALL_DEFINE0(alpha_pipe) -{ - int fd[2]; - int res = do_pipe_flags(fd, 0); - if (!res) { - /* The return values are in $0 and $20. */ - current_pt_regs()->r20 = fd[1]; - res = fd[0]; - } - return res; -} - -SYSCALL_DEFINE1(sethae, unsigned long, val) -{ - current_pt_regs()->hae = val; - return 0; -} diff --git a/trunk/arch/alpha/kernel/pci.c b/trunk/arch/alpha/kernel/pci.c index ef757147cbf9..9816d5a4d176 100644 --- a/trunk/arch/alpha/kernel/pci.c +++ b/trunk/arch/alpha/kernel/pci.c @@ -256,6 +256,12 @@ pcibios_fixup_bus(struct pci_bus *bus) } } +void __init +pcibios_update_irq(struct pci_dev *dev, int irq) +{ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} + int pcibios_enable_device(struct pci_dev *dev, int mask) { diff --git a/trunk/arch/alpha/kernel/process.c b/trunk/arch/alpha/kernel/process.c index 83638aa096d5..153d3fce3e8e 100644 --- a/trunk/arch/alpha/kernel/process.c +++ b/trunk/arch/alpha/kernel/process.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include @@ -55,12 +54,9 @@ cpu_idle(void) /* FIXME -- EV6 and LCA45 know how to power down the CPU. */ - rcu_idle_enter(); while (!need_resched()) cpu_relax(); - - rcu_idle_exit(); - schedule_preempt_disabled(); + schedule(); } } @@ -459,22 +455,3 @@ get_wchan(struct task_struct *p) } return pc; } - -int kernel_execve(const char *path, const char *const argv[], const char *const envp[]) -{ - /* Avoid the HAE being gratuitously wrong, which would cause us - to do the whole turn off interrupts thing and restore it. */ - struct pt_regs regs = {.hae = alpha_mv.hae_cache}; - int err = do_execve(path, argv, envp, ®s); - if (!err) { - struct pt_regs *p = current_pt_regs(); - /* copy regs to normal position and off to userland we go... */ - *p = regs; - __asm__ __volatile__ ( - "mov %0, $sp;" - "br $31, ret_from_sys_call" - : : "r"(p)); - } - return err; -} -EXPORT_SYMBOL(kernel_execve); diff --git a/trunk/arch/alpha/kernel/smp.c b/trunk/arch/alpha/kernel/smp.c index a41ad90a97a6..35ddc02bfa4a 100644 --- a/trunk/arch/alpha/kernel/smp.c +++ b/trunk/arch/alpha/kernel/smp.c @@ -166,7 +166,6 @@ smp_callin(void) DBGS(("smp_callin: commencing CPU %d current %p active_mm %p\n", cpuid, current, current->active_mm)); - preempt_disable(); /* Do nothing. */ cpu_idle(); } diff --git a/trunk/arch/alpha/kernel/srmcons.c b/trunk/arch/alpha/kernel/srmcons.c index 5d5865204a1d..3ea809430eda 100644 --- a/trunk/arch/alpha/kernel/srmcons.c +++ b/trunk/arch/alpha/kernel/srmcons.c @@ -223,7 +223,6 @@ srmcons_init(void) driver->subtype = SYSTEM_TYPE_SYSCONS; driver->init_termios = tty_std_termios; tty_set_operations(driver, &srmcons_ops); - tty_port_link_device(&srmcons_singleton.port, driver, 0); err = tty_register_driver(driver); if (err) { put_tty_driver(driver); diff --git a/trunk/arch/alpha/kernel/systbls.S b/trunk/arch/alpha/kernel/systbls.S index 2ac6b45c3e00..87835235f114 100644 --- a/trunk/arch/alpha/kernel/systbls.S +++ b/trunk/arch/alpha/kernel/systbls.S @@ -111,7 +111,7 @@ sys_call_table: .quad sys_socket .quad sys_connect .quad sys_accept - .quad sys_osf_getpriority /* 100 */ + .quad osf_getpriority /* 100 */ .quad sys_send .quad sys_recv .quad sys_sigreturn @@ -522,8 +522,6 @@ sys_call_table: .quad sys_setns .quad sys_accept4 .quad sys_sendmmsg - .quad sys_process_vm_readv - .quad sys_process_vm_writev /* 505 */ .size sys_call_table, . - sys_call_table .type sys_call_table, @object diff --git a/trunk/arch/alpha/lib/Makefile b/trunk/arch/alpha/lib/Makefile index 59660743237c..c0a83ab62b78 100644 --- a/trunk/arch/alpha/lib/Makefile +++ b/trunk/arch/alpha/lib/Makefile @@ -31,6 +31,8 @@ lib-y = __divqu.o __remqu.o __divlu.o __remlu.o \ $(ev6-y)memchr.o \ $(ev6-y)copy_user.o \ $(ev6-y)clear_user.o \ + $(ev6-y)strncpy_from_user.o \ + $(ev67-y)strlen_user.o \ $(ev6-y)csum_ipv6_magic.o \ $(ev6-y)clear_page.o \ $(ev6-y)copy_page.o \ diff --git a/trunk/arch/alpha/lib/ev6-strncpy_from_user.S b/trunk/arch/alpha/lib/ev6-strncpy_from_user.S new file mode 100644 index 000000000000..d2e28178cacc --- /dev/null +++ b/trunk/arch/alpha/lib/ev6-strncpy_from_user.S @@ -0,0 +1,424 @@ +/* + * arch/alpha/lib/ev6-strncpy_from_user.S + * 21264 version contributed by Rick Gorton + * + * Just like strncpy except in the return value: + * + * -EFAULT if an exception occurs before the terminator is copied. + * N if the buffer filled. + * + * Otherwise the length of the string is returned. + * + * Much of the information about 21264 scheduling/coding comes from: + * Compiler Writer's Guide for the Alpha 21264 + * abbreviated as 'CWG' in other comments here + * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html + * Scheduling notation: + * E - either cluster + * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1 + * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1 + * A bunch of instructions got moved and temp registers were changed + * to aid in scheduling. Control flow was also re-arranged to eliminate + * branches, and to provide longer code sequences to enable better scheduling. + * A total rewrite (using byte load/stores for start & tail sequences) + * is desirable, but very difficult to do without a from-scratch rewrite. + * Save that for the future. + */ + + +#include +#include + + +/* Allow an exception for an insn; exit if we get one. */ +#define EX(x,y...) \ + 99: x,##y; \ + .section __ex_table,"a"; \ + .long 99b - .; \ + lda $31, $exception-99b($0); \ + .previous + + + .set noat + .set noreorder + .text + + .globl __strncpy_from_user + .ent __strncpy_from_user + .frame $30, 0, $26 + .prologue 0 + + .align 4 +__strncpy_from_user: + and a0, 7, t3 # E : find dest misalignment + beq a2, $zerolength # U : + + /* Are source and destination co-aligned? */ + mov a0, v0 # E : save the string start + xor a0, a1, t4 # E : + EX( ldq_u t1, 0(a1) ) # L : Latency=3 load first quadword + ldq_u t0, 0(a0) # L : load first (partial) aligned dest quadword + + addq a2, t3, a2 # E : bias count by dest misalignment + subq a2, 1, a3 # E : + addq zero, 1, t10 # E : + and t4, 7, t4 # E : misalignment between the two + + and a3, 7, t6 # E : number of tail bytes + sll t10, t6, t10 # E : t10 = bitmask of last count byte + bne t4, $unaligned # U : + lda t2, -1 # E : build a mask against false zero + + /* + * We are co-aligned; take care of a partial first word. + * On entry to this basic block: + * t0 == the first destination word for masking back in + * t1 == the first source word. + */ + + srl a3, 3, a2 # E : a2 = loop counter = (count - 1)/8 + addq a1, 8, a1 # E : + mskqh t2, a1, t2 # U : detection in the src word + nop + + /* Create the 1st output word and detect 0's in the 1st input word. */ + mskqh t1, a1, t3 # U : + mskql t0, a1, t0 # U : assemble the first output word + ornot t1, t2, t2 # E : + nop + + cmpbge zero, t2, t8 # E : bits set iff null found + or t0, t3, t0 # E : + beq a2, $a_eoc # U : + bne t8, $a_eos # U : 2nd branch in a quad. Bad. + + /* On entry to this basic block: + * t0 == a source quad not containing a null. + * a0 - current aligned destination address + * a1 - current aligned source address + * a2 - count of quadwords to move. + * NOTE: Loop improvement - unrolling this is going to be + * a huge win, since we're going to stall otherwise. + * Fix this later. For _really_ large copies, look + * at using wh64 on a look-ahead basis. See the code + * in clear_user.S and copy_user.S. + * Presumably, since (a0) and (a1) do not overlap (by C definition) + * Lots of nops here: + * - Separate loads from stores + * - Keep it to 1 branch/quadpack so the branch predictor + * can train. + */ +$a_loop: + stq_u t0, 0(a0) # L : + addq a0, 8, a0 # E : + nop + subq a2, 1, a2 # E : + + EX( ldq_u t0, 0(a1) ) # L : + addq a1, 8, a1 # E : + cmpbge zero, t0, t8 # E : Stall 2 cycles on t0 + beq a2, $a_eoc # U : + + beq t8, $a_loop # U : + nop + nop + nop + + /* Take care of the final (partial) word store. At this point + * the end-of-count bit is set in t8 iff it applies. + * + * On entry to this basic block we have: + * t0 == the source word containing the null + * t8 == the cmpbge mask that found it. + */ +$a_eos: + negq t8, t12 # E : find low bit set + and t8, t12, t12 # E : + + /* We're doing a partial word store and so need to combine + our source and original destination words. */ + ldq_u t1, 0(a0) # L : + subq t12, 1, t6 # E : + + or t12, t6, t8 # E : + zapnot t0, t8, t0 # U : clear src bytes > null + zap t1, t8, t1 # U : clear dst bytes <= null + or t0, t1, t0 # E : + + stq_u t0, 0(a0) # L : + br $finish_up # L0 : + nop + nop + + /* Add the end-of-count bit to the eos detection bitmask. */ + .align 4 +$a_eoc: + or t10, t8, t8 + br $a_eos + nop + nop + + +/* The source and destination are not co-aligned. Align the destination + and cope. We have to be very careful about not reading too much and + causing a SEGV. */ + + .align 4 +$u_head: + /* We know just enough now to be able to assemble the first + full source word. We can still find a zero at the end of it + that prevents us from outputting the whole thing. + + On entry to this basic block: + t0 == the first dest word, unmasked + t1 == the shifted low bits of the first source word + t6 == bytemask that is -1 in dest word bytes */ + + EX( ldq_u t2, 8(a1) ) # L : load second src word + addq a1, 8, a1 # E : + mskql t0, a0, t0 # U : mask trailing garbage in dst + extqh t2, a1, t4 # U : + + or t1, t4, t1 # E : first aligned src word complete + mskqh t1, a0, t1 # U : mask leading garbage in src + or t0, t1, t0 # E : first output word complete + or t0, t6, t6 # E : mask original data for zero test + + cmpbge zero, t6, t8 # E : + beq a2, $u_eocfin # U : + bne t8, $u_final # U : bad news - 2nd branch in a quad + lda t6, -1 # E : mask out the bits we have + + mskql t6, a1, t6 # U : already seen + stq_u t0, 0(a0) # L : store first output word + or t6, t2, t2 # E : + cmpbge zero, t2, t8 # E : find nulls in second partial + + addq a0, 8, a0 # E : + subq a2, 1, a2 # E : + bne t8, $u_late_head_exit # U : + nop + + /* Finally, we've got all the stupid leading edge cases taken care + of and we can set up to enter the main loop. */ + + extql t2, a1, t1 # U : position hi-bits of lo word + EX( ldq_u t2, 8(a1) ) # L : read next high-order source word + addq a1, 8, a1 # E : + cmpbge zero, t2, t8 # E : + + beq a2, $u_eoc # U : + bne t8, $u_eos # U : + nop + nop + + /* Unaligned copy main loop. In order to avoid reading too much, + the loop is structured to detect zeros in aligned source words. + This has, unfortunately, effectively pulled half of a loop + iteration out into the head and half into the tail, but it does + prevent nastiness from accumulating in the very thing we want + to run as fast as possible. + + On entry to this basic block: + t1 == the shifted high-order bits from the previous source word + t2 == the unshifted current source word + + We further know that t2 does not contain a null terminator. */ + + /* + * Extra nops here: + * separate load quads from store quads + * only one branch/quad to permit predictor training + */ + + .align 4 +$u_loop: + extqh t2, a1, t0 # U : extract high bits for current word + addq a1, 8, a1 # E : + extql t2, a1, t3 # U : extract low bits for next time + addq a0, 8, a0 # E : + + or t0, t1, t0 # E : current dst word now complete + EX( ldq_u t2, 0(a1) ) # L : load high word for next time + subq a2, 1, a2 # E : + nop + + stq_u t0, -8(a0) # L : save the current word + mov t3, t1 # E : + cmpbge zero, t2, t8 # E : test new word for eos + beq a2, $u_eoc # U : + + beq t8, $u_loop # U : + nop + nop + nop + + /* We've found a zero somewhere in the source word we just read. + If it resides in the lower half, we have one (probably partial) + word to write out, and if it resides in the upper half, we + have one full and one partial word left to write out. + + On entry to this basic block: + t1 == the shifted high-order bits from the previous source word + t2 == the unshifted current source word. */ + .align 4 +$u_eos: + extqh t2, a1, t0 # U : + or t0, t1, t0 # E : first (partial) source word complete + cmpbge zero, t0, t8 # E : is the null in this first bit? + nop + + bne t8, $u_final # U : + stq_u t0, 0(a0) # L : the null was in the high-order bits + addq a0, 8, a0 # E : + subq a2, 1, a2 # E : + + .align 4 +$u_late_head_exit: + extql t2, a1, t0 # U : + cmpbge zero, t0, t8 # E : + or t8, t10, t6 # E : + cmoveq a2, t6, t8 # E : + + /* Take care of a final (probably partial) result word. + On entry to this basic block: + t0 == assembled source word + t8 == cmpbge mask that found the null. */ + .align 4 +$u_final: + negq t8, t6 # E : isolate low bit set + and t6, t8, t12 # E : + ldq_u t1, 0(a0) # L : + subq t12, 1, t6 # E : + + or t6, t12, t8 # E : + zapnot t0, t8, t0 # U : kill source bytes > null + zap t1, t8, t1 # U : kill dest bytes <= null + or t0, t1, t0 # E : + + stq_u t0, 0(a0) # E : + br $finish_up # U : + nop + nop + + .align 4 +$u_eoc: # end-of-count + extqh t2, a1, t0 # U : + or t0, t1, t0 # E : + cmpbge zero, t0, t8 # E : + nop + + .align 4 +$u_eocfin: # end-of-count, final word + or t10, t8, t8 # E : + br $u_final # U : + nop + nop + + /* Unaligned copy entry point. */ + .align 4 +$unaligned: + + srl a3, 3, a2 # U : a2 = loop counter = (count - 1)/8 + and a0, 7, t4 # E : find dest misalignment + and a1, 7, t5 # E : find src misalignment + mov zero, t0 # E : + + /* Conditionally load the first destination word and a bytemask + with 0xff indicating that the destination byte is sacrosanct. */ + + mov zero, t6 # E : + beq t4, 1f # U : + ldq_u t0, 0(a0) # L : + lda t6, -1 # E : + + mskql t6, a0, t6 # E : + nop + nop + nop + + .align 4 +1: + subq a1, t4, a1 # E : sub dest misalignment from src addr + /* If source misalignment is larger than dest misalignment, we need + extra startup checks to avoid SEGV. */ + cmplt t4, t5, t12 # E : + extql t1, a1, t1 # U : shift src into place + lda t2, -1 # E : for creating masks later + + beq t12, $u_head # U : + mskqh t2, t5, t2 # U : begin src byte validity mask + cmpbge zero, t1, t8 # E : is there a zero? + nop + + extql t2, a1, t2 # U : + or t8, t10, t5 # E : test for end-of-count too + cmpbge zero, t2, t3 # E : + cmoveq a2, t5, t8 # E : Latency=2, extra map slot + + nop # E : goes with cmov + andnot t8, t3, t8 # E : + beq t8, $u_head # U : + nop + + /* At this point we've found a zero in the first partial word of + the source. We need to isolate the valid source data and mask + it into the original destination data. (Incidentally, we know + that we'll need at least one byte of that original dest word.) */ + + ldq_u t0, 0(a0) # L : + negq t8, t6 # E : build bitmask of bytes <= zero + mskqh t1, t4, t1 # U : + and t6, t8, t12 # E : + + subq t12, 1, t6 # E : + or t6, t12, t8 # E : + zapnot t2, t8, t2 # U : prepare source word; mirror changes + zapnot t1, t8, t1 # U : to source validity mask + + andnot t0, t2, t0 # E : zero place for source to reside + or t0, t1, t0 # E : and put it there + stq_u t0, 0(a0) # L : + nop + + .align 4 +$finish_up: + zapnot t0, t12, t4 # U : was last byte written null? + and t12, 0xf0, t3 # E : binary search for the address of the + cmovne t4, 1, t4 # E : Latency=2, extra map slot + nop # E : with cmovne + + and t12, 0xcc, t2 # E : last byte written + and t12, 0xaa, t1 # E : + cmovne t3, 4, t3 # E : Latency=2, extra map slot + nop # E : with cmovne + + bic a0, 7, t0 + cmovne t2, 2, t2 # E : Latency=2, extra map slot + nop # E : with cmovne + nop + + cmovne t1, 1, t1 # E : Latency=2, extra map slot + nop # E : with cmovne + addq t0, t3, t0 # E : + addq t1, t2, t1 # E : + + addq t0, t1, t0 # E : + addq t0, t4, t0 # add one if we filled the buffer + subq t0, v0, v0 # find string length + ret # L0 : + + .align 4 +$zerolength: + nop + nop + nop + clr v0 + +$exception: + nop + nop + nop + ret + + .end __strncpy_from_user diff --git a/trunk/arch/alpha/lib/ev67-strlen_user.S b/trunk/arch/alpha/lib/ev67-strlen_user.S new file mode 100644 index 000000000000..57e0d77b81a6 --- /dev/null +++ b/trunk/arch/alpha/lib/ev67-strlen_user.S @@ -0,0 +1,107 @@ +/* + * arch/alpha/lib/ev67-strlen_user.S + * 21264 version contributed by Rick Gorton + * + * Return the length of the string including the NULL terminator + * (strlen+1) or zero if an error occurred. + * + * In places where it is critical to limit the processing time, + * and the data is not trusted, strnlen_user() should be used. + * It will return a value greater than its second argument if + * that limit would be exceeded. This implementation is allowed + * to access memory beyond the limit, but will not cross a page + * boundary when doing so. + * + * Much of the information about 21264 scheduling/coding comes from: + * Compiler Writer's Guide for the Alpha 21264 + * abbreviated as 'CWG' in other comments here + * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html + * Scheduling notation: + * E - either cluster + * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1 + * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1 + * Try not to change the actual algorithm if possible for consistency. + */ + +#include + + +/* Allow an exception for an insn; exit if we get one. */ +#define EX(x,y...) \ + 99: x,##y; \ + .section __ex_table,"a"; \ + .long 99b - .; \ + lda v0, $exception-99b(zero); \ + .previous + + + .set noreorder + .set noat + .text + + .globl __strlen_user + .ent __strlen_user + .frame sp, 0, ra + + .align 4 +__strlen_user: + ldah a1, 32767(zero) # do not use plain strlen_user() for strings + # that might be almost 2 GB long; you should + # be using strnlen_user() instead + nop + nop + nop + + .globl __strnlen_user + + .align 4 +__strnlen_user: + .prologue 0 + EX( ldq_u t0, 0(a0) ) # L : load first quadword (a0 may be misaligned) + lda t1, -1(zero) # E : + + insqh t1, a0, t1 # U : + andnot a0, 7, v0 # E : + or t1, t0, t0 # E : + subq a0, 1, a0 # E : get our +1 for the return + + cmpbge zero, t0, t1 # E : t1 <- bitmask: bit i == 1 <==> i-th byte == 0 + subq a1, 7, t2 # E : + subq a0, v0, t0 # E : + bne t1, $found # U : + + addq t2, t0, t2 # E : + addq a1, 1, a1 # E : + nop # E : + nop # E : + + .align 4 +$loop: ble t2, $limit # U : + EX( ldq t0, 8(v0) ) # L : + nop # E : + nop # E : + + cmpbge zero, t0, t1 # E : + subq t2, 8, t2 # E : + addq v0, 8, v0 # E : addr += 8 + beq t1, $loop # U : + +$found: cttz t1, t2 # U0 : + addq v0, t2, v0 # E : + subq v0, a0, v0 # E : + ret # L0 : + +$exception: + nop + nop + nop + ret + + .align 4 # currently redundant +$limit: + nop + nop + subq a1, t2, v0 + ret + + .end __strlen_user diff --git a/trunk/arch/alpha/lib/strlen_user.S b/trunk/arch/alpha/lib/strlen_user.S new file mode 100644 index 000000000000..508a18e96479 --- /dev/null +++ b/trunk/arch/alpha/lib/strlen_user.S @@ -0,0 +1,91 @@ +/* + * arch/alpha/lib/strlen_user.S + * + * Return the length of the string including the NUL terminator + * (strlen+1) or zero if an error occurred. + * + * In places where it is critical to limit the processing time, + * and the data is not trusted, strnlen_user() should be used. + * It will return a value greater than its second argument if + * that limit would be exceeded. This implementation is allowed + * to access memory beyond the limit, but will not cross a page + * boundary when doing so. + */ + +#include + + +/* Allow an exception for an insn; exit if we get one. */ +#define EX(x,y...) \ + 99: x,##y; \ + .section __ex_table,"a"; \ + .long 99b - .; \ + lda v0, $exception-99b(zero); \ + .previous + + + .set noreorder + .set noat + .text + + .globl __strlen_user + .ent __strlen_user + .frame sp, 0, ra + + .align 3 +__strlen_user: + ldah a1, 32767(zero) # do not use plain strlen_user() for strings + # that might be almost 2 GB long; you should + # be using strnlen_user() instead + + .globl __strnlen_user + + .align 3 +__strnlen_user: + .prologue 0 + + EX( ldq_u t0, 0(a0) ) # load first quadword (a0 may be misaligned) + lda t1, -1(zero) + insqh t1, a0, t1 + andnot a0, 7, v0 + or t1, t0, t0 + subq a0, 1, a0 # get our +1 for the return + cmpbge zero, t0, t1 # t1 <- bitmask: bit i == 1 <==> i-th byte == 0 + subq a1, 7, t2 + subq a0, v0, t0 + bne t1, $found + + addq t2, t0, t2 + addq a1, 1, a1 + + .align 3 +$loop: ble t2, $limit + EX( ldq t0, 8(v0) ) + subq t2, 8, t2 + addq v0, 8, v0 # addr += 8 + cmpbge zero, t0, t1 + beq t1, $loop + +$found: negq t1, t2 # clear all but least set bit + and t1, t2, t1 + + and t1, 0xf0, t2 # binary search for that set bit + and t1, 0xcc, t3 + and t1, 0xaa, t4 + cmovne t2, 4, t2 + cmovne t3, 2, t3 + cmovne t4, 1, t4 + addq t2, t3, t2 + addq v0, t4, v0 + addq v0, t2, v0 + nop # dual issue next two on ev4 and ev5 + subq v0, a0, v0 +$exception: + ret + + .align 3 # currently redundant +$limit: + subq a1, t2, v0 + ret + + .end __strlen_user diff --git a/trunk/arch/alpha/lib/strncpy_from_user.S b/trunk/arch/alpha/lib/strncpy_from_user.S new file mode 100644 index 000000000000..73ee21160ff7 --- /dev/null +++ b/trunk/arch/alpha/lib/strncpy_from_user.S @@ -0,0 +1,339 @@ +/* + * arch/alpha/lib/strncpy_from_user.S + * Contributed by Richard Henderson (rth@tamu.edu) + * + * Just like strncpy except in the return value: + * + * -EFAULT if an exception occurs before the terminator is copied. + * N if the buffer filled. + * + * Otherwise the length of the string is returned. + */ + + +#include +#include + + +/* Allow an exception for an insn; exit if we get one. */ +#define EX(x,y...) \ + 99: x,##y; \ + .section __ex_table,"a"; \ + .long 99b - .; \ + lda $31, $exception-99b($0); \ + .previous + + + .set noat + .set noreorder + .text + + .globl __strncpy_from_user + .ent __strncpy_from_user + .frame $30, 0, $26 + .prologue 0 + + .align 3 +$aligned: + /* On entry to this basic block: + t0 == the first destination word for masking back in + t1 == the first source word. */ + + /* Create the 1st output word and detect 0's in the 1st input word. */ + lda t2, -1 # e1 : build a mask against false zero + mskqh t2, a1, t2 # e0 : detection in the src word + mskqh t1, a1, t3 # e0 : + ornot t1, t2, t2 # .. e1 : + mskql t0, a1, t0 # e0 : assemble the first output word + cmpbge zero, t2, t8 # .. e1 : bits set iff null found + or t0, t3, t0 # e0 : + beq a2, $a_eoc # .. e1 : + bne t8, $a_eos # .. e1 : + + /* On entry to this basic block: + t0 == a source word not containing a null. */ + +$a_loop: + stq_u t0, 0(a0) # e0 : + addq a0, 8, a0 # .. e1 : + EX( ldq_u t0, 0(a1) ) # e0 : + addq a1, 8, a1 # .. e1 : + subq a2, 1, a2 # e0 : + cmpbge zero, t0, t8 # .. e1 (stall) + beq a2, $a_eoc # e1 : + beq t8, $a_loop # e1 : + + /* Take care of the final (partial) word store. At this point + the end-of-count bit is set in t8 iff it applies. + + On entry to this basic block we have: + t0 == the source word containing the null + t8 == the cmpbge mask that found it. */ + +$a_eos: + negq t8, t12 # e0 : find low bit set + and t8, t12, t12 # e1 (stall) + + /* For the sake of the cache, don't read a destination word + if we're not going to need it. */ + and t12, 0x80, t6 # e0 : + bne t6, 1f # .. e1 (zdb) + + /* We're doing a partial word store and so need to combine + our source and original destination words. */ + ldq_u t1, 0(a0) # e0 : + subq t12, 1, t6 # .. e1 : + or t12, t6, t8 # e0 : + unop # + zapnot t0, t8, t0 # e0 : clear src bytes > null + zap t1, t8, t1 # .. e1 : clear dst bytes <= null + or t0, t1, t0 # e1 : + +1: stq_u t0, 0(a0) + br $finish_up + + /* Add the end-of-count bit to the eos detection bitmask. */ +$a_eoc: + or t10, t8, t8 + br $a_eos + + /*** The Function Entry Point ***/ + .align 3 +__strncpy_from_user: + mov a0, v0 # save the string start + beq a2, $zerolength + + /* Are source and destination co-aligned? */ + xor a0, a1, t1 # e0 : + and a0, 7, t0 # .. e1 : find dest misalignment + and t1, 7, t1 # e0 : + addq a2, t0, a2 # .. e1 : bias count by dest misalignment + subq a2, 1, a2 # e0 : + and a2, 7, t2 # e1 : + srl a2, 3, a2 # e0 : a2 = loop counter = (count - 1)/8 + addq zero, 1, t10 # .. e1 : + sll t10, t2, t10 # e0 : t10 = bitmask of last count byte + bne t1, $unaligned # .. e1 : + + /* We are co-aligned; take care of a partial first word. */ + + EX( ldq_u t1, 0(a1) ) # e0 : load first src word + addq a1, 8, a1 # .. e1 : + + beq t0, $aligned # avoid loading dest word if not needed + ldq_u t0, 0(a0) # e0 : + br $aligned # .. e1 : + + +/* The source and destination are not co-aligned. Align the destination + and cope. We have to be very careful about not reading too much and + causing a SEGV. */ + + .align 3 +$u_head: + /* We know just enough now to be able to assemble the first + full source word. We can still find a zero at the end of it + that prevents us from outputting the whole thing. + + On entry to this basic block: + t0 == the first dest word, unmasked + t1 == the shifted low bits of the first source word + t6 == bytemask that is -1 in dest word bytes */ + + EX( ldq_u t2, 8(a1) ) # e0 : load second src word + addq a1, 8, a1 # .. e1 : + mskql t0, a0, t0 # e0 : mask trailing garbage in dst + extqh t2, a1, t4 # e0 : + or t1, t4, t1 # e1 : first aligned src word complete + mskqh t1, a0, t1 # e0 : mask leading garbage in src + or t0, t1, t0 # e0 : first output word complete + or t0, t6, t6 # e1 : mask original data for zero test + cmpbge zero, t6, t8 # e0 : + beq a2, $u_eocfin # .. e1 : + bne t8, $u_final # e1 : + + lda t6, -1 # e1 : mask out the bits we have + mskql t6, a1, t6 # e0 : already seen + stq_u t0, 0(a0) # e0 : store first output word + or t6, t2, t2 # .. e1 : + cmpbge zero, t2, t8 # e0 : find nulls in second partial + addq a0, 8, a0 # .. e1 : + subq a2, 1, a2 # e0 : + bne t8, $u_late_head_exit # .. e1 : + + /* Finally, we've got all the stupid leading edge cases taken care + of and we can set up to enter the main loop. */ + + extql t2, a1, t1 # e0 : position hi-bits of lo word + EX( ldq_u t2, 8(a1) ) # .. e1 : read next high-order source word + addq a1, 8, a1 # e0 : + cmpbge zero, t2, t8 # e1 (stall) + beq a2, $u_eoc # e1 : + bne t8, $u_eos # e1 : + + /* Unaligned copy main loop. In order to avoid reading too much, + the loop is structured to detect zeros in aligned source words. + This has, unfortunately, effectively pulled half of a loop + iteration out into the head and half into the tail, but it does + prevent nastiness from accumulating in the very thing we want + to run as fast as possible. + + On entry to this basic block: + t1 == the shifted high-order bits from the previous source word + t2 == the unshifted current source word + + We further know that t2 does not contain a null terminator. */ + + .align 3 +$u_loop: + extqh t2, a1, t0 # e0 : extract high bits for current word + addq a1, 8, a1 # .. e1 : + extql t2, a1, t3 # e0 : extract low bits for next time + addq a0, 8, a0 # .. e1 : + or t0, t1, t0 # e0 : current dst word now complete + EX( ldq_u t2, 0(a1) ) # .. e1 : load high word for next time + stq_u t0, -8(a0) # e0 : save the current word + mov t3, t1 # .. e1 : + subq a2, 1, a2 # e0 : + cmpbge zero, t2, t8 # .. e1 : test new word for eos + beq a2, $u_eoc # e1 : + beq t8, $u_loop # e1 : + + /* We've found a zero somewhere in the source word we just read. + If it resides in the lower half, we have one (probably partial) + word to write out, and if it resides in the upper half, we + have one full and one partial word left to write out. + + On entry to this basic block: + t1 == the shifted high-order bits from the previous source word + t2 == the unshifted current source word. */ +$u_eos: + extqh t2, a1, t0 # e0 : + or t0, t1, t0 # e1 : first (partial) source word complete + + cmpbge zero, t0, t8 # e0 : is the null in this first bit? + bne t8, $u_final # .. e1 (zdb) + + stq_u t0, 0(a0) # e0 : the null was in the high-order bits + addq a0, 8, a0 # .. e1 : + subq a2, 1, a2 # e1 : + +$u_late_head_exit: + extql t2, a1, t0 # .. e0 : + cmpbge zero, t0, t8 # e0 : + or t8, t10, t6 # e1 : + cmoveq a2, t6, t8 # e0 : + nop # .. e1 : + + /* Take care of a final (probably partial) result word. + On entry to this basic block: + t0 == assembled source word + t8 == cmpbge mask that found the null. */ +$u_final: + negq t8, t6 # e0 : isolate low bit set + and t6, t8, t12 # e1 : + + and t12, 0x80, t6 # e0 : avoid dest word load if we can + bne t6, 1f # .. e1 (zdb) + + ldq_u t1, 0(a0) # e0 : + subq t12, 1, t6 # .. e1 : + or t6, t12, t8 # e0 : + zapnot t0, t8, t0 # .. e1 : kill source bytes > null + zap t1, t8, t1 # e0 : kill dest bytes <= null + or t0, t1, t0 # e1 : + +1: stq_u t0, 0(a0) # e0 : + br $finish_up + +$u_eoc: # end-of-count + extqh t2, a1, t0 + or t0, t1, t0 + cmpbge zero, t0, t8 + +$u_eocfin: # end-of-count, final word + or t10, t8, t8 + br $u_final + + /* Unaligned copy entry point. */ + .align 3 +$unaligned: + + EX( ldq_u t1, 0(a1) ) # e0 : load first source word + + and a0, 7, t4 # .. e1 : find dest misalignment + and a1, 7, t5 # e0 : find src misalignment + + /* Conditionally load the first destination word and a bytemask + with 0xff indicating that the destination byte is sacrosanct. */ + + mov zero, t0 # .. e1 : + mov zero, t6 # e0 : + beq t4, 1f # .. e1 : + ldq_u t0, 0(a0) # e0 : + lda t6, -1 # .. e1 : + mskql t6, a0, t6 # e0 : +1: + subq a1, t4, a1 # .. e1 : sub dest misalignment from src addr + + /* If source misalignment is larger than dest misalignment, we need + extra startup checks to avoid SEGV. */ + + cmplt t4, t5, t12 # e1 : + extql t1, a1, t1 # .. e0 : shift src into place + lda t2, -1 # e0 : for creating masks later + beq t12, $u_head # e1 : + + mskqh t2, t5, t2 # e0 : begin src byte validity mask + cmpbge zero, t1, t8 # .. e1 : is there a zero? + extql t2, a1, t2 # e0 : + or t8, t10, t5 # .. e1 : test for end-of-count too + cmpbge zero, t2, t3 # e0 : + cmoveq a2, t5, t8 # .. e1 : + andnot t8, t3, t8 # e0 : + beq t8, $u_head # .. e1 (zdb) + + /* At this point we've found a zero in the first partial word of + the source. We need to isolate the valid source data and mask + it into the original destination data. (Incidentally, we know + that we'll need at least one byte of that original dest word.) */ + + ldq_u t0, 0(a0) # e0 : + negq t8, t6 # .. e1 : build bitmask of bytes <= zero + mskqh t1, t4, t1 # e0 : + and t6, t8, t12 # .. e1 : + subq t12, 1, t6 # e0 : + or t6, t12, t8 # e1 : + + zapnot t2, t8, t2 # e0 : prepare source word; mirror changes + zapnot t1, t8, t1 # .. e1 : to source validity mask + + andnot t0, t2, t0 # e0 : zero place for source to reside + or t0, t1, t0 # e1 : and put it there + stq_u t0, 0(a0) # e0 : + +$finish_up: + zapnot t0, t12, t4 # was last byte written null? + cmovne t4, 1, t4 + + and t12, 0xf0, t3 # binary search for the address of the + and t12, 0xcc, t2 # last byte written + and t12, 0xaa, t1 + bic a0, 7, t0 + cmovne t3, 4, t3 + cmovne t2, 2, t2 + cmovne t1, 1, t1 + addq t0, t3, t0 + addq t1, t2, t1 + addq t0, t1, t0 + addq t0, t4, t0 # add one if we filled the buffer + + subq t0, v0, v0 # find string length + ret + +$zerolength: + clr v0 +$exception: + ret + + .end __strncpy_from_user diff --git a/trunk/arch/alpha/mm/fault.c b/trunk/arch/alpha/mm/fault.c index 0c4132dd3507..5eecab1a84ef 100644 --- a/trunk/arch/alpha/mm/fault.c +++ b/trunk/arch/alpha/mm/fault.c @@ -89,8 +89,6 @@ do_page_fault(unsigned long address, unsigned long mmcsr, const struct exception_table_entry *fixup; int fault, si_code = SEGV_MAPERR; siginfo_t info; - unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE | - (cause > 0 ? FAULT_FLAG_WRITE : 0)); /* As of EV6, a load into $31/$f31 is a prefetch, and never faults (or is suppressed by the PALcode). Support that for older CPUs @@ -116,7 +114,6 @@ do_page_fault(unsigned long address, unsigned long mmcsr, goto vmalloc_fault; #endif -retry: down_read(&mm->mmap_sem); vma = find_vma(mm, address); if (!vma) @@ -147,11 +144,8 @@ do_page_fault(unsigned long address, unsigned long mmcsr, /* If for any reason at all we couldn't handle the fault, make sure we exit gracefully rather than endlessly redo the fault. */ - fault = handle_mm_fault(mm, vma, address, flags); - - if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) - return; - + fault = handle_mm_fault(mm, vma, address, cause > 0 ? FAULT_FLAG_WRITE : 0); + up_read(&mm->mmap_sem); if (unlikely(fault & VM_FAULT_ERROR)) { if (fault & VM_FAULT_OOM) goto out_of_memory; @@ -159,26 +153,10 @@ do_page_fault(unsigned long address, unsigned long mmcsr, goto do_sigbus; BUG(); } - - if (flags & FAULT_FLAG_ALLOW_RETRY) { - if (fault & VM_FAULT_MAJOR) - current->maj_flt++; - else - current->min_flt++; - if (fault & VM_FAULT_RETRY) { - flags &= ~FAULT_FLAG_ALLOW_RETRY; - - /* No need to up_read(&mm->mmap_sem) as we would - * have already released it in __lock_page_or_retry - * in mm/filemap.c. - */ - - goto retry; - } - } - - up_read(&mm->mmap_sem); - + if (fault & VM_FAULT_MAJOR) + current->maj_flt++; + else + current->min_flt++; return; /* Something tried to access memory that isn't in our memory map. @@ -208,14 +186,12 @@ do_page_fault(unsigned long address, unsigned long mmcsr, /* We ran out of memory, or some other thing happened to us that made us unable to handle the page fault gracefully. */ out_of_memory: - up_read(&mm->mmap_sem); if (!user_mode(regs)) goto no_context; pagefault_out_of_memory(); return; do_sigbus: - up_read(&mm->mmap_sem); /* Send a sigbus, regardless of whether we were in kernel or user mode. */ info.si_signo = SIGBUS; diff --git a/trunk/arch/alpha/oprofile/common.c b/trunk/arch/alpha/oprofile/common.c index b8ce18f485d3..a0a5d27aa215 100644 --- a/trunk/arch/alpha/oprofile/common.c +++ b/trunk/arch/alpha/oprofile/common.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "op_impl.h" diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index 884768cb5332..e91c7cdc6fe5 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -6,7 +6,7 @@ config ARM select HAVE_DMA_API_DEBUG select HAVE_IDE if PCI || ISA || PCMCIA select HAVE_DMA_ATTRS - select HAVE_DMA_CONTIGUOUS if MMU + select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7) select HAVE_MEMBLOCK select RTC_LIB select SYS_SUPPORTS_APM_EMULATION @@ -38,6 +38,7 @@ config ARM select HARDIRQS_SW_RESEND select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW + select GENERIC_IRQ_PROBE select ARCH_WANT_IPC_PARSE_VERSION select HARDIRQS_SW_RESEND select CPU_PM if (SUSPEND || CPU_IDLE) @@ -125,6 +126,11 @@ config TRACE_IRQFLAGS_SUPPORT bool default y +config GENERIC_LOCKBREAK + bool + default y + depends on SMP && PREEMPT + config RWSEM_GENERIC_SPINLOCK bool default y @@ -273,12 +279,13 @@ config ARCH_INTEGRATOR select ARM_AMBA select ARCH_HAS_CPUFREQ select COMMON_CLK - select COMMON_CLK_VERSATILE + select CLK_VERSATILE select HAVE_TCM select ICST select GENERIC_CLOCKEVENTS select PLAT_VERSATILE select PLAT_VERSATILE_FPGA_IRQ + select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select SPARSE_IRQ select MULTI_IRQ_HANDLER @@ -288,12 +295,13 @@ config ARCH_INTEGRATOR config ARCH_REALVIEW bool "ARM Ltd. RealView family" select ARM_AMBA - select COMMON_CLK - select COMMON_CLK_VERSATILE + select CLKDEV_LOOKUP + select HAVE_MACH_CLKDEV select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB select PLAT_VERSATILE + select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD select ARM_TIMER_SP804 select GPIO_PL061 if GPIOLIB @@ -310,6 +318,7 @@ config ARCH_VERSATILE select ICST select GENERIC_CLOCKEVENTS select ARCH_WANT_OPTIONAL_GPIOLIB + select NEED_MACH_IO_H if PCI select PLAT_VERSATILE select PLAT_VERSATILE_CLOCK select PLAT_VERSATILE_CLCD @@ -404,19 +413,21 @@ config ARCH_GEMINI help Support for the Cortina Systems Gemini family SoCs -config ARCH_SIRF - bool "CSR SiRF" +config ARCH_PRIMA2 + bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" + select CPU_V7 select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS - select COMMON_CLK + select CLKDEV_LOOKUP select GENERIC_IRQ_CHIP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select PINCTRL_SIRF select USE_OF + select ZONE_DMA help - Support for CSR SiRFprimaII/Marco/Polo platforms + Support for CSR SiRFSoC ARM Cortex A9 Platform config ARCH_EBSA110 bool "EBSA-110" @@ -451,7 +462,7 @@ config ARCH_FOOTBRIDGE select FOOTBRIDGE select GENERIC_CLOCKEVENTS select HAVE_IDE - select NEED_MACH_IO_H if !MMU + select NEED_MACH_IO_H select NEED_MACH_MEMORY_H help Support for systems based on the DC21285 companion chip @@ -508,6 +519,7 @@ config ARCH_IOP13XX select PCI select ARCH_SUPPORTS_MSI select VMSPLIT_1G + select NEED_MACH_IO_H select NEED_MACH_MEMORY_H select NEED_RET_TO_USER help @@ -517,6 +529,7 @@ config ARCH_IOP32X bool "IOP32x-based" depends on MMU select CPU_XSCALE + select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -529,6 +542,7 @@ config ARCH_IOP33X bool "IOP33x-based" depends on MMU select CPU_XSCALE + select NEED_MACH_IO_H select NEED_RET_TO_USER select PLAT_IOP select PCI @@ -568,6 +582,7 @@ config ARCH_DOVE select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the Marvell Dove SoC 88AP510 @@ -578,6 +593,7 @@ config ARCH_KIRKWOOD select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Kirkwood series SoCs: @@ -604,6 +620,7 @@ config ARCH_MV78XX0 select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell MV78xx0 series SoCs: @@ -616,6 +633,7 @@ config ARCH_ORION5X select PCI select ARCH_REQUIRE_GPIOLIB select GENERIC_CLOCKEVENTS + select NEED_MACH_IO_H select PLAT_ORION help Support for the following Marvell Orion 5x series SoCs: @@ -640,9 +658,8 @@ config ARCH_KS8695 bool "Micrel/Kendin KS8695" select CPU_ARM922T select ARCH_REQUIRE_GPIOLIB + select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H - select CLKSRC_MMIO - select GENERIC_CLOCKEVENTS help Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based System-on-Chip devices. @@ -672,6 +689,7 @@ config ARCH_TEGRA select HAVE_CLK select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 + select NEED_MACH_IO_H if PCI select ARCH_HAS_CPUFREQ select USE_OF help @@ -697,6 +715,14 @@ config ARCH_PICOXCELL family of Femtocell devices. The picoxcell support requires device tree for all boards. +config ARCH_PNX4008 + bool "Philips Nexperia PNX4008 Mobile" + select CPU_ARM926T + select CLKDEV_LOOKUP + select ARCH_USES_GETTIMEOFFSET + help + This enables support for Philips PNX4008 mobile platform. + config ARCH_PXA bool "PXA2xx/PXA3xx-based" depends on MMU @@ -892,6 +918,7 @@ config ARCH_SHARK select PCI select ARCH_USES_GETTIMEOFFSET select NEED_MACH_MEMORY_H + select NEED_MACH_IO_H help Support for the StrongARM based Digital DNARD machine, also known as "Shark" (). @@ -910,7 +937,6 @@ config ARCH_U300 select COMMON_CLK select GENERIC_GPIO select ARCH_REQUIRE_GPIOLIB - select SPARSE_IRQ help Support for ST-Ericsson U300 series mobile platforms. @@ -1098,8 +1124,6 @@ source "arch/arm/mach-exynos/Kconfig" source "arch/arm/mach-shmobile/Kconfig" -source "arch/arm/mach-prima2/Kconfig" - source "arch/arm/mach-tegra/Kconfig" source "arch/arm/mach-u300/Kconfig" @@ -1161,6 +1185,12 @@ config XSCALE_PMU depends on CPU_XSCALE default y +config CPU_HAS_PMU + depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \ + (!ARCH_OMAP3 || OMAP3_EMU) + default y + bool + config MULTI_IRQ_HANDLER bool help @@ -1733,7 +1763,7 @@ config HIGHPTE config HW_PERF_EVENTS bool "Enable hardware performance counter support for perf events" - depends on PERF_EVENTS + depends on PERF_EVENTS && CPU_HAS_PMU default y help Enable hardware performance counter support for perf events. If @@ -2120,7 +2150,6 @@ source "drivers/cpufreq/Kconfig" config CPU_FREQ_IMX tristate "CPUfreq driver for i.MX CPUs" depends on ARCH_MXC && CPU_FREQ - select CPU_FREQ_TABLE help This enables the CPUfreq driver for i.MX CPUs. @@ -2289,7 +2318,7 @@ menu "Power management options" source "kernel/power/Kconfig" config ARCH_SUSPEND_POSSIBLE - depends on !ARCH_S5PC100 + depends on !ARCH_S5PC100 && !ARCH_TEGRA depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \ CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK def_bool y diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug index e968a52e4881..f15f82bf3a50 100644 --- a/trunk/arch/arm/Kconfig.debug +++ b/trunk/arch/arm/Kconfig.debug @@ -356,15 +356,15 @@ choice is nothing connected to read from the DCC. config DEBUG_SEMIHOSTING - bool "Kernel low-level debug output via semihosting I/O" + bool "Kernel low-level debug output via semihosting I" help Semihosting enables code running on an ARM target to use the I/O facilities on a host debugger/emulator through a - simple SVC call. The host debugger or emulator must have + simple SVC calls. The host debugger or emulator must have semihosting enabled for the special svc call to be trapped otherwise the kernel will crash. - This is known to work with OpenOCD, as well as + This is known to work with OpenOCD, as wellas ARM's Fast Models, or any other controlling environment that implements semihosting. diff --git a/trunk/arch/arm/Makefile b/trunk/arch/arm/Makefile index 74381a31ee42..30eae87ead6d 100644 --- a/trunk/arch/arm/Makefile +++ b/trunk/arch/arm/Makefile @@ -167,6 +167,7 @@ machine-$(CONFIG_ARCH_OMAP1) := omap1 machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2 machine-$(CONFIG_ARCH_ORION5X) := orion5x machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell +machine-$(CONFIG_ARCH_PNX4008) := pnx4008 machine-$(CONFIG_ARCH_PRIMA2) := prima2 machine-$(CONFIG_ARCH_PXA) := pxa machine-$(CONFIG_ARCH_REALVIEW) := realview @@ -283,10 +284,10 @@ zImage Image xipImage bootpImage uImage: vmlinux zinstall uinstall install: vmlinux $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@ -%.dtb: scripts +%.dtb: $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ -dtbs: scripts +dtbs: $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@ # We use MRPROPER_FILES and CLEAN_FILES now diff --git a/trunk/arch/arm/boot/compressed/head.S b/trunk/arch/arm/boot/compressed/head.S index bc67cbff3944..b8c64b80bafc 100644 --- a/trunk/arch/arm/boot/compressed/head.S +++ b/trunk/arch/arm/boot/compressed/head.S @@ -653,21 +653,16 @@ __armv7_mmu_cache_on: mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs #endif mrc p15, 0, r0, c1, c0, 0 @ read control reg - bic r0, r0, #1 << 28 @ clear SCTLR.TRE orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer #ifdef CONFIG_MMU #ifdef CONFIG_CPU_ENDIAN_BE8 orr r0, r0, #1 << 25 @ big-endian page tables #endif - mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client - bic r6, r6, #1 << 31 @ 32-bit translation system - bic r6, r6, #3 << 0 @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control - mcrne p15, 0, r6, c2, c0, 2 @ load ttb control #endif mcr p15, 0, r0, c7, c5, 4 @ ISB mcr p15, 0, r0, c1, c0, 0 @ load control register diff --git a/trunk/arch/arm/boot/dts/am33xx.dtsi b/trunk/arch/arm/boot/dts/am33xx.dtsi index bd0cff3f808c..59509c48d7e5 100644 --- a/trunk/arch/arm/boot/dts/am33xx.dtsi +++ b/trunk/arch/arm/boot/dts/am33xx.dtsi @@ -154,10 +154,5 @@ #size-cells = <0>; ti,hwmods = "i2c3"; }; - - wdt2: wdt@44e35000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer2"; - }; }; }; diff --git a/trunk/arch/arm/boot/dts/at91sam9260.dtsi b/trunk/arch/arm/boot/dts/at91sam9260.dtsi index 7c95f76398de..66389c1c6f62 100644 --- a/trunk/arch/arm/boot/dts/at91sam9260.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9260.dtsi @@ -104,7 +104,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioB: gpio@fffff600 { @@ -114,7 +113,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioC: gpio@fffff800 { @@ -124,7 +122,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; dbgu: serial@fffff200 { diff --git a/trunk/arch/arm/boot/dts/at91sam9263.dtsi b/trunk/arch/arm/boot/dts/at91sam9263.dtsi index 195019b7ca0e..b460d6ce9eb5 100644 --- a/trunk/arch/arm/boot/dts/at91sam9263.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9263.dtsi @@ -95,7 +95,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioB: gpio@fffff400 { @@ -105,7 +104,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioC: gpio@fffff600 { @@ -115,7 +113,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioD: gpio@fffff800 { @@ -125,7 +122,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioE: gpio@fffffa00 { @@ -135,7 +131,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; dbgu: serial@ffffee00 { diff --git a/trunk/arch/arm/boot/dts/at91sam9g25ek.dts b/trunk/arch/arm/boot/dts/at91sam9g25ek.dts index 96514c134e54..7829a4d0cb22 100644 --- a/trunk/arch/arm/boot/dts/at91sam9g25ek.dts +++ b/trunk/arch/arm/boot/dts/at91sam9g25ek.dts @@ -15,7 +15,7 @@ compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9"; chosen { - bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; + bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs"; }; ahb { diff --git a/trunk/arch/arm/boot/dts/at91sam9g45.dtsi b/trunk/arch/arm/boot/dts/at91sam9g45.dtsi index 63751b1e744b..bafa8806fc17 100644 --- a/trunk/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9g45.dtsi @@ -113,7 +113,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioB: gpio@fffff400 { @@ -123,7 +122,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioC: gpio@fffff600 { @@ -133,7 +131,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioD: gpio@fffff800 { @@ -143,7 +140,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioE: gpio@fffffa00 { @@ -153,7 +149,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; dbgu: serial@ffffee00 { diff --git a/trunk/arch/arm/boot/dts/at91sam9n12.dtsi b/trunk/arch/arm/boot/dts/at91sam9n12.dtsi index ef9336ae9614..bfac0dfc332c 100644 --- a/trunk/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9n12.dtsi @@ -107,7 +107,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioB: gpio@fffff600 { @@ -117,7 +116,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioC: gpio@fffff800 { @@ -127,7 +125,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioD: gpio@fffffa00 { @@ -137,7 +134,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; dbgu: serial@fffff200 { diff --git a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi index 8a387a8d61b7..4a18c393b136 100644 --- a/trunk/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/trunk/arch/arm/boot/dts/at91sam9x5.dtsi @@ -115,7 +115,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioB: gpio@fffff600 { @@ -125,7 +124,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioC: gpio@fffff800 { @@ -135,7 +133,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; pioD: gpio@fffffa00 { @@ -145,7 +142,6 @@ #gpio-cells = <2>; gpio-controller; interrupt-controller; - #interrupt-cells = <2>; }; dbgu: serial@fffff200 { diff --git a/trunk/arch/arm/boot/dts/imx23.dtsi b/trunk/arch/arm/boot/dts/imx23.dtsi index e6138310e5ce..a874dbfb5ae6 100644 --- a/trunk/arch/arm/boot/dts/imx23.dtsi +++ b/trunk/arch/arm/boot/dts/imx23.dtsi @@ -51,11 +51,11 @@ dma-apbh@80004000 { compatible = "fsl,imx23-dma-apbh"; - reg = <0x80004000 0x2000>; + reg = <0x80004000 2000>; }; ecc@80008000 { - reg = <0x80008000 0x2000>; + reg = <0x80008000 2000>; status = "disabled"; }; @@ -63,7 +63,7 @@ compatible = "fsl,imx23-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; + reg = <0x8000c000 2000>, <0x8000a000 2000>; reg-names = "gpmi-nand", "bch"; interrupts = <13>, <56>; interrupt-names = "gpmi-dma", "bch"; @@ -72,14 +72,14 @@ }; ssp0: ssp@80010000 { - reg = <0x80010000 0x2000>; + reg = <0x80010000 2000>; interrupts = <15 14>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; etm@80014000 { - reg = <0x80014000 0x2000>; + reg = <0x80014000 2000>; status = "disabled"; }; @@ -87,7 +87,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx23-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; + reg = <0x80018000 2000>; gpio0: gpio@0 { compatible = "fsl,imx23-gpio", "fsl,mxs-gpio"; @@ -273,32 +273,32 @@ }; emi@80020000 { - reg = <0x80020000 0x2000>; + reg = <0x80020000 2000>; status = "disabled"; }; dma-apbx@80024000 { compatible = "fsl,imx23-dma-apbx"; - reg = <0x80024000 0x2000>; + reg = <0x80024000 2000>; }; dcp@80028000 { - reg = <0x80028000 0x2000>; + reg = <0x80028000 2000>; status = "disabled"; }; pxp@8002a000 { - reg = <0x8002a000 0x2000>; + reg = <0x8002a000 2000>; status = "disabled"; }; ocotp@8002c000 { - reg = <0x8002c000 0x2000>; + reg = <0x8002c000 2000>; status = "disabled"; }; axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; + reg = <0x8002e000 2000>; status = "disabled"; }; @@ -310,14 +310,14 @@ }; ssp1: ssp@80034000 { - reg = <0x80034000 0x2000>; + reg = <0x80034000 2000>; interrupts = <2 20>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; tvenc@80038000 { - reg = <0x80038000 0x2000>; + reg = <0x80038000 2000>; status = "disabled"; }; }; @@ -330,37 +330,37 @@ ranges; clkctl@80040000 { - reg = <0x80040000 0x2000>; + reg = <0x80040000 2000>; status = "disabled"; }; saif0: saif@80042000 { - reg = <0x80042000 0x2000>; + reg = <0x80042000 2000>; status = "disabled"; }; power@80044000 { - reg = <0x80044000 0x2000>; + reg = <0x80044000 2000>; status = "disabled"; }; saif1: saif@80046000 { - reg = <0x80046000 0x2000>; + reg = <0x80046000 2000>; status = "disabled"; }; audio-out@80048000 { - reg = <0x80048000 0x2000>; + reg = <0x80048000 2000>; status = "disabled"; }; audio-in@8004c000 { - reg = <0x8004c000 0x2000>; + reg = <0x8004c000 2000>; status = "disabled"; }; lradc@80050000 { - reg = <0x80050000 0x2000>; + reg = <0x80050000 2000>; status = "disabled"; }; @@ -370,26 +370,26 @@ }; i2c@80058000 { - reg = <0x80058000 0x2000>; + reg = <0x80058000 2000>; status = "disabled"; }; rtc@8005c000 { compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x8005c000 0x2000>; + reg = <0x8005c000 2000>; interrupts = <22>; }; pwm: pwm@80064000 { compatible = "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; + reg = <0x80064000 2000>; #pwm-cells = <2>; fsl,pwm-number = <5>; status = "disabled"; }; timrot@80068000 { - reg = <0x80068000 0x2000>; + reg = <0x80068000 2000>; status = "disabled"; }; @@ -429,7 +429,7 @@ ranges; usbctrl@80080000 { - reg = <0x80080000 0x40000>; + reg = <0x80080000 0x10000>; status = "disabled"; }; }; diff --git a/trunk/arch/arm/boot/dts/imx27-3ds.dts b/trunk/arch/arm/boot/dts/imx27-3ds.dts index 0a8978a40ece..d3f8296e19e0 100644 --- a/trunk/arch/arm/boot/dts/imx27-3ds.dts +++ b/trunk/arch/arm/boot/dts/imx27-3ds.dts @@ -27,7 +27,7 @@ status = "okay"; }; - uart1: serial@1000a000 { + uart@1000a000 { fsl,uart-has-rtscts; status = "okay"; }; diff --git a/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts b/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts index 2acc86cfdd05..2b0ff60247a4 100644 --- a/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts +++ b/trunk/arch/arm/boot/dts/imx27-phytec-phycore.dts @@ -49,7 +49,7 @@ i2c@1001d000 { clock-frequency = <400000>; status = "okay"; - at24@52 { + at24@4c { compatible = "at,24c32"; pagesize = <32>; reg = <0x52>; diff --git a/trunk/arch/arm/boot/dts/imx27.dtsi b/trunk/arch/arm/boot/dts/imx27.dtsi index 5303ab680a34..00bae3aad5ab 100644 --- a/trunk/arch/arm/boot/dts/imx27.dtsi +++ b/trunk/arch/arm/boot/dts/imx27.dtsi @@ -19,12 +19,6 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; }; avic: avic-interrupt-controller@e0000000 { diff --git a/trunk/arch/arm/boot/dts/imx28.dtsi b/trunk/arch/arm/boot/dts/imx28.dtsi index 3fa6d190fab4..787efac68da8 100644 --- a/trunk/arch/arm/boot/dts/imx28.dtsi +++ b/trunk/arch/arm/boot/dts/imx28.dtsi @@ -57,18 +57,18 @@ }; hsadc@80002000 { - reg = <0x80002000 0x2000>; + reg = <0x80002000 2000>; interrupts = <13 87>; status = "disabled"; }; dma-apbh@80004000 { compatible = "fsl,imx28-dma-apbh"; - reg = <0x80004000 0x2000>; + reg = <0x80004000 2000>; }; perfmon@80006000 { - reg = <0x80006000 0x800>; + reg = <0x80006000 800>; interrupts = <27>; status = "disabled"; }; @@ -77,7 +77,7 @@ compatible = "fsl,imx28-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; - reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; + reg = <0x8000c000 2000>, <0x8000a000 2000>; reg-names = "gpmi-nand", "bch"; interrupts = <88>, <41>; interrupt-names = "gpmi-dma", "bch"; @@ -86,28 +86,28 @@ }; ssp0: ssp@80010000 { - reg = <0x80010000 0x2000>; + reg = <0x80010000 2000>; interrupts = <96 82>; fsl,ssp-dma-channel = <0>; status = "disabled"; }; ssp1: ssp@80012000 { - reg = <0x80012000 0x2000>; + reg = <0x80012000 2000>; interrupts = <97 83>; fsl,ssp-dma-channel = <1>; status = "disabled"; }; ssp2: ssp@80014000 { - reg = <0x80014000 0x2000>; + reg = <0x80014000 2000>; interrupts = <98 84>; fsl,ssp-dma-channel = <2>; status = "disabled"; }; ssp3: ssp@80016000 { - reg = <0x80016000 0x2000>; + reg = <0x80016000 2000>; interrupts = <99 85>; fsl,ssp-dma-channel = <3>; status = "disabled"; @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx28-pinctrl", "simple-bus"; - reg = <0x80018000 0x2000>; + reg = <0x80018000 2000>; gpio0: gpio@0 { compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; @@ -510,96 +510,96 @@ }; digctl@8001c000 { - reg = <0x8001c000 0x2000>; + reg = <0x8001c000 2000>; interrupts = <89>; status = "disabled"; }; etm@80022000 { - reg = <0x80022000 0x2000>; + reg = <0x80022000 2000>; status = "disabled"; }; dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; - reg = <0x80024000 0x2000>; + reg = <0x80024000 2000>; }; dcp@80028000 { - reg = <0x80028000 0x2000>; + reg = <0x80028000 2000>; interrupts = <52 53 54>; status = "disabled"; }; pxp@8002a000 { - reg = <0x8002a000 0x2000>; + reg = <0x8002a000 2000>; interrupts = <39>; status = "disabled"; }; ocotp@8002c000 { - reg = <0x8002c000 0x2000>; + reg = <0x8002c000 2000>; status = "disabled"; }; axi-ahb@8002e000 { - reg = <0x8002e000 0x2000>; + reg = <0x8002e000 2000>; status = "disabled"; }; lcdif@80030000 { compatible = "fsl,imx28-lcdif"; - reg = <0x80030000 0x2000>; + reg = <0x80030000 2000>; interrupts = <38 86>; status = "disabled"; }; can0: can@80032000 { compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; - reg = <0x80032000 0x2000>; + reg = <0x80032000 2000>; interrupts = <8>; status = "disabled"; }; can1: can@80034000 { compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; - reg = <0x80034000 0x2000>; + reg = <0x80034000 2000>; interrupts = <9>; status = "disabled"; }; simdbg@8003c000 { - reg = <0x8003c000 0x200>; + reg = <0x8003c000 200>; status = "disabled"; }; simgpmisel@8003c200 { - reg = <0x8003c200 0x100>; + reg = <0x8003c200 100>; status = "disabled"; }; simsspsel@8003c300 { - reg = <0x8003c300 0x100>; + reg = <0x8003c300 100>; status = "disabled"; }; simmemsel@8003c400 { - reg = <0x8003c400 0x100>; + reg = <0x8003c400 100>; status = "disabled"; }; gpiomon@8003c500 { - reg = <0x8003c500 0x100>; + reg = <0x8003c500 100>; status = "disabled"; }; simenet@8003c700 { - reg = <0x8003c700 0x100>; + reg = <0x8003c700 100>; status = "disabled"; }; armjtag@8003c800 { - reg = <0x8003c800 0x100>; + reg = <0x8003c800 100>; status = "disabled"; }; }; @@ -612,45 +612,45 @@ ranges; clkctl@80040000 { - reg = <0x80040000 0x2000>; + reg = <0x80040000 2000>; status = "disabled"; }; saif0: saif@80042000 { compatible = "fsl,imx28-saif"; - reg = <0x80042000 0x2000>; + reg = <0x80042000 2000>; interrupts = <59 80>; fsl,saif-dma-channel = <4>; status = "disabled"; }; power@80044000 { - reg = <0x80044000 0x2000>; + reg = <0x80044000 2000>; status = "disabled"; }; saif1: saif@80046000 { compatible = "fsl,imx28-saif"; - reg = <0x80046000 0x2000>; + reg = <0x80046000 2000>; interrupts = <58 81>; fsl,saif-dma-channel = <5>; status = "disabled"; }; lradc@80050000 { - reg = <0x80050000 0x2000>; + reg = <0x80050000 2000>; status = "disabled"; }; spdif@80054000 { - reg = <0x80054000 0x2000>; + reg = <0x80054000 2000>; interrupts = <45 66>; status = "disabled"; }; rtc@80056000 { compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; - reg = <0x80056000 0x2000>; + reg = <0x80056000 2000>; interrupts = <29>; }; @@ -658,7 +658,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx28-i2c"; - reg = <0x80058000 0x2000>; + reg = <0x80058000 2000>; interrupts = <111 68>; clock-frequency = <100000>; status = "disabled"; @@ -668,7 +668,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx28-i2c"; - reg = <0x8005a000 0x2000>; + reg = <0x8005a000 2000>; interrupts = <110 69>; clock-frequency = <100000>; status = "disabled"; @@ -676,14 +676,14 @@ pwm: pwm@80064000 { compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; - reg = <0x80064000 0x2000>; + reg = <0x80064000 2000>; #pwm-cells = <2>; fsl,pwm-number = <8>; status = "disabled"; }; timrot@80068000 { - reg = <0x80068000 0x2000>; + reg = <0x80068000 2000>; status = "disabled"; }; diff --git a/trunk/arch/arm/boot/dts/imx51-babbage.dts b/trunk/arch/arm/boot/dts/imx51-babbage.dts index 59d9789e5508..de065b5976e6 100644 --- a/trunk/arch/arm/boot/dts/imx51-babbage.dts +++ b/trunk/arch/arm/boot/dts/imx51-babbage.dts @@ -25,8 +25,8 @@ aips@70000000 { /* aips-1 */ spba@70000000 { esdhc@70004000 { /* ESDHC1 */ - fsl,cd-controller; - fsl,wp-controller; + fsl,cd-internal; + fsl,wp-internal; status = "okay"; }; @@ -53,7 +53,7 @@ spi-max-frequency = <6000000>; reg = <0>; interrupt-parent = <&gpio1>; - interrupts = <8 0x4>; + interrupts = <8>; regulators { sw1_reg: sw1 { diff --git a/trunk/arch/arm/boot/dts/imx51.dtsi b/trunk/arch/arm/boot/dts/imx51.dtsi index aba28dc87fc8..53cbaa3d4f90 100644 --- a/trunk/arch/arm/boot/dts/imx51.dtsi +++ b/trunk/arch/arm/boot/dts/imx51.dtsi @@ -17,10 +17,6 @@ serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; }; tzic: tz-interrupt-controller@e0000000 { diff --git a/trunk/arch/arm/boot/dts/imx53-ard.dts b/trunk/arch/arm/boot/dts/imx53-ard.dts index da895e93a999..5b8eafcdbeec 100644 --- a/trunk/arch/arm/boot/dts/imx53-ard.dts +++ b/trunk/arch/arm/boot/dts/imx53-ard.dts @@ -64,32 +64,12 @@ reg = <0xf4000000 0x2000000>; phy-mode = "mii"; interrupt-parent = <&gpio2>; - interrupts = <31 0x8>; + interrupts = <31>; reg-io-width = <4>; - /* - * VDD33A and VDDVARIO of LAN9220 are supplied by - * SW4_3V3 of LTC3589. Before the regulator driver - * for this PMIC is available, we use a fixed dummy - * 3V3 regulator to get LAN9220 driver probing work. - */ - vdd33a-supply = <®_3p3v>; - vddvario-supply = <®_3p3v>; smsc,irq-push-pull; }; }; - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - gpio-keys { compatible = "gpio-keys"; diff --git a/trunk/arch/arm/boot/dts/imx53.dtsi b/trunk/arch/arm/boot/dts/imx53.dtsi index cd37165edce5..fc79cdc4b4e6 100644 --- a/trunk/arch/arm/boot/dts/imx53.dtsi +++ b/trunk/arch/arm/boot/dts/imx53.dtsi @@ -19,13 +19,6 @@ serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; }; tzic: tz-interrupt-controller@0fffc000 { diff --git a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts index 72f30f3e6171..d42e851ceb97 100644 --- a/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts +++ b/trunk/arch/arm/boot/dts/imx6q-sabrelite.dts @@ -53,7 +53,6 @@ fsl,pins = < 144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */ 121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */ - 953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */ >; }; }; diff --git a/trunk/arch/arm/boot/dts/imx6q.dtsi b/trunk/arch/arm/boot/dts/imx6q.dtsi index fd57079f71a9..3d3c64b014e6 100644 --- a/trunk/arch/arm/boot/dts/imx6q.dtsi +++ b/trunk/arch/arm/boot/dts/imx6q.dtsi @@ -19,13 +19,6 @@ serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - gpio5 = &gpio6; - gpio6 = &gpio7; }; cpus { diff --git a/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts b/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts index f8ca6fa88192..52d947045106 100644 --- a/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/trunk/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -41,12 +41,8 @@ }; power-blue { label = "power:blue"; - gpios = <&gpio1 10 0>; - linux,default-trigger = "timer"; - }; - power-red { - label = "power:red"; gpios = <&gpio1 11 0>; + linux,default-trigger = "timer"; }; usb1 { label = "usb1:blue"; diff --git a/trunk/arch/arm/boot/dts/tegra20-harmony.dts b/trunk/arch/arm/boot/dts/tegra20-harmony.dts index c3ef1ad26b6a..f146dbf6f7f8 100644 --- a/trunk/arch/arm/boot/dts/tegra20-harmony.dts +++ b/trunk/arch/arm/boot/dts/tegra20-harmony.dts @@ -275,160 +275,6 @@ i2c@7000d000 { status = "okay"; clock-frequency = <400000>; - - pmic: tps6586x@34 { - compatible = "ti,tps6586x"; - reg = <0x34>; - interrupts = <0 86 0x4>; - - ti,system-power-controller; - - #gpio-cells = <2>; - gpio-controller; - - sys-supply = <&vdd_5v0_reg>; - vin-sm0-supply = <&sys_reg>; - vin-sm1-supply = <&sys_reg>; - vin-sm2-supply = <&sys_reg>; - vinldo01-supply = <&sm2_reg>; - vinldo23-supply = <&sm2_reg>; - vinldo4-supply = <&sm2_reg>; - vinldo678-supply = <&sm2_reg>; - vinldo9-supply = <&sm2_reg>; - - regulators { - #address-cells = <1>; - #size-cells = <0>; - - sys_reg: regulator@0 { - reg = <0>; - regulator-compatible = "sys"; - regulator-name = "vdd_sys"; - regulator-always-on; - }; - - regulator@1 { - reg = <1>; - regulator-compatible = "sm0"; - regulator-name = "vdd_sm0,vdd_core"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - regulator@2 { - reg = <2>; - regulator-compatible = "sm1"; - regulator-name = "vdd_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - sm2_reg: regulator@3 { - reg = <3>; - regulator-compatible = "sm2"; - regulator-name = "vdd_sm2,vin_ldo*"; - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - regulator-always-on; - }; - - regulator@4 { - reg = <4>; - regulator-compatible = "ldo0"; - regulator-name = "vdd_ldo0,vddio_pex_clk"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - regulator@5 { - reg = <5>; - regulator-compatible = "ldo1"; - regulator-name = "vdd_ldo1,avdd_pll*"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - regulator@6 { - reg = <6>; - regulator-compatible = "ldo2"; - regulator-name = "vdd_ldo2,vdd_rtc"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - }; - - regulator@7 { - reg = <7>; - regulator-compatible = "ldo3"; - regulator-name = "vdd_ldo3,avdd_usb*"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - regulator@8 { - reg = <8>; - regulator-compatible = "ldo4"; - regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - regulator@9 { - reg = <9>; - regulator-compatible = "ldo5"; - regulator-name = "vdd_ldo5,vcore_mmc"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - regulator@10 { - reg = <10>; - regulator-compatible = "ldo6"; - regulator-name = "vdd_ldo6,avdd_vdac"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - regulator@11 { - reg = <11>; - regulator-compatible = "ldo7"; - regulator-name = "vdd_ldo7,avdd_hdmi"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - regulator@12 { - reg = <12>; - regulator-compatible = "ldo8"; - regulator-name = "vdd_ldo8,avdd_hdmi_pll"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - regulator@13 { - reg = <13>; - regulator-compatible = "ldo9"; - regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - regulator-always-on; - }; - - regulator@14 { - reg = <14>; - regulator-compatible = "ldo_rtc"; - regulator-name = "vdd_rtc_out,vdd_cell"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; - }; }; pmc { @@ -464,72 +310,6 @@ bus-width = <8>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - vdd_5v0_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vdd_1v5"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - gpio = <&pmic 0 0>; - }; - - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vdd_1v2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - gpio = <&pmic 1 0>; - enable-active-high; - }; - - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vdd_1v05"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - gpio = <&pmic 2 0>; - enable-active-high; - /* Hack until board-harmony-pcie.c is removed */ - status = "disabled"; - }; - - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "vdd_pnl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio 22 0>; /* gpio PC6 */ - enable-active-high; - }; - - regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "vdd_bl"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - gpio = <&gpio 176 0>; /* gpio PW0 */ - enable-active-high; - }; - }; - sound { compatible = "nvidia,tegra-audio-wm8903-harmony", "nvidia,tegra-audio-wm8903"; diff --git a/trunk/arch/arm/boot/dts/twl6030.dtsi b/trunk/arch/arm/boot/dts/twl6030.dtsi index d351b27d7213..3b2f3510d7eb 100644 --- a/trunk/arch/arm/boot/dts/twl6030.dtsi +++ b/trunk/arch/arm/boot/dts/twl6030.dtsi @@ -66,7 +66,6 @@ vcxio: regulator@8 { compatible = "ti,twl6030-vcxio"; - regulator-always-on; }; vusb: regulator@9 { @@ -75,12 +74,10 @@ v1v8: regulator@10 { compatible = "ti,twl6030-v1v8"; - regulator-always-on; }; v2v1: regulator@11 { compatible = "ti,twl6030-v2v1"; - regulator-always-on; }; clk32kg: regulator@12 { diff --git a/trunk/arch/arm/configs/armadillo800eva_defconfig b/trunk/arch/arm/configs/armadillo800eva_defconfig index 90610c7030f7..7d8718468e0d 100644 --- a/trunk/arch/arm/configs/armadillo800eva_defconfig +++ b/trunk/arch/arm/configs/armadillo800eva_defconfig @@ -33,7 +33,7 @@ CONFIG_AEABI=y CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw" +CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096" CONFIG_CMDLINE_FORCE=y CONFIG_KEXEC=y CONFIG_VFP=y diff --git a/trunk/arch/arm/configs/imx_v6_v7_defconfig b/trunk/arch/arm/configs/imx_v6_v7_defconfig index 3c9f32f9b6b4..f725b9637b33 100644 --- a/trunk/arch/arm/configs/imx_v6_v7_defconfig +++ b/trunk/arch/arm/configs/imx_v6_v7_defconfig @@ -192,7 +192,6 @@ CONFIG_RTC_DRV_MC13XXX=y CONFIG_RTC_DRV_MXC=y CONFIG_DMADEVICES=y CONFIG_IMX_SDMA=y -CONFIG_MXS_DMA=y CONFIG_COMMON_CLK_DEBUG=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXT2_FS=y diff --git a/trunk/arch/arm/configs/mxs_defconfig b/trunk/arch/arm/configs/mxs_defconfig index 4edcfb4e4dee..ccdb6357fb74 100644 --- a/trunk/arch/arm/configs/mxs_defconfig +++ b/trunk/arch/arm/configs/mxs_defconfig @@ -34,6 +34,7 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT_VOLUNTARY=y CONFIG_AEABI=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 CONFIG_AUTO_ZRELADDR=y CONFIG_FPE_NWFPE=y CONFIG_NET=y diff --git a/trunk/arch/arm/configs/pnx4008_defconfig b/trunk/arch/arm/configs/pnx4008_defconfig new file mode 100644 index 000000000000..35a31ccacc32 --- /dev/null +++ b/trunk/arch/arm/configs/pnx4008_defconfig @@ -0,0 +1,472 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_AUDIT=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_ARCH_PNX4008=y +CONFIG_PREEMPT=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="mem=64M console=ttyS0,115200" +CONFIG_FPE_NWFPE=y +CONFIG_BINFMT_AOUT=m +CONFIG_BINFMT_MISC=m +CONFIG_PM=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_IPV6_PRIVACY=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_TUNNEL=m +CONFIG_NETFILTER=y +CONFIG_IP_VS=m +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_WRR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP6_NF_QUEUE=m +CONFIG_DECNET_NF_GRABULATOR=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_IP_SCTP=m +CONFIG_ATM=y +CONFIG_ATM_CLIP=y +CONFIG_ATM_LANE=m +CONFIG_ATM_MPOA=m +CONFIG_ATM_BR2684=m +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=m +CONFIG_DECNET=m +CONFIG_LLC2=m +CONFIG_IPX=m +CONFIG_ATALK=m +CONFIG_DEV_APPLETALK=m +CONFIG_IPDDP=m +CONFIG_IPDDP_ENCAP=y +CONFIG_IPDDP_DECAP=y +CONFIG_X25=m +CONFIG_LAPB=m +CONFIG_ECONET=m +CONFIG_ECONET_AUNUDP=y +CONFIG_ECONET_NATIVE=y +CONFIG_WAN_ROUTER=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_PKTGEN=m +CONFIG_MTD=y +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +CONFIG_MTD_REDBOOT_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_SLRAM=m +CONFIG_MTD_PHRAM=m +CONFIG_MTD_MTDRAM=m +CONFIG_MTD_DOC2000=m +CONFIG_MTD_DOC2001=m +CONFIG_MTD_DOC2001PLUS=m +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_NANDSIM=m +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_CDROM_PKTCDVD=m +CONFIG_EEPROM_LEGACY=m +CONFIG_SCSI=m +CONFIG_BLK_DEV_SD=m +CONFIG_CHR_DEV_ST=m +CONFIG_CHR_DEV_OSST=m +CONFIG_BLK_DEV_SR=m +CONFIG_CHR_DEV_SG=m +CONFIG_CHR_DEV_SCH=m +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_DEBUG=m +CONFIG_NETDEVICES=y +CONFIG_DUMMY=m +CONFIG_BONDING=m +CONFIG_EQUALIZER=m +CONFIG_TUN=m +CONFIG_NET_ETHERNET=y +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_CDC_SUBSET is not set +CONFIG_WAN=y +CONFIG_HDLC=m +CONFIG_HDLC_RAW=m +CONFIG_HDLC_RAW_ETH=m +CONFIG_HDLC_CISCO=m +CONFIG_HDLC_FR=m +CONFIG_HDLC_PPP=m +CONFIG_HDLC_X25=m +CONFIG_DLCI=m +CONFIG_WAN_ROUTER_DRIVERS=m +CONFIG_LAPBETHER=m +CONFIG_X25_ASY=m +CONFIG_ATM_TCP=m +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOATM=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_NETCONSOLE=m +# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=m +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_LKKBD=m +CONFIG_KEYBOARD_NEWTON=m +CONFIG_KEYBOARD_SUNKBD=m +CONFIG_KEYBOARD_XTKBD=m +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_SERIAL=m +CONFIG_MOUSE_VSXXXAA=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_JOYSTICK_ANALOG=m +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_SIDEWINDER=m +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=y +CONFIG_JOYSTICK_IFORCE_232=y +CONFIG_JOYSTICK_WARRIOR=m +CONFIG_JOYSTICK_MAGELLAN=m +CONFIG_JOYSTICK_SPACEORB=m +CONFIG_JOYSTICK_SPACEBALL=m +CONFIG_JOYSTICK_STINGER=m +CONFIG_JOYSTICK_JOYDUMP=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_GUNZE=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=m +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT_NS558=m +CONFIG_GAMEPORT_L4=m +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_SPI=y +CONFIG_SPI_BITBANG=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_USBPCWATCHDOG=m +# CONFIG_VGA_CONSOLE is not set +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_SEQUENCER_OSS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_VIRMIDI=m +CONFIG_SND_MTPAV=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_MPU401=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SOUND_PRIME=m +CONFIG_USB_HID=m +CONFIG_USB_HIDDEV=y +CONFIG_USB_KBD=m +CONFIG_USB_MOUSE=m +CONFIG_USB=y +CONFIG_USB_DEVICEFS=y +CONFIG_USB_MON=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_ACM=m +CONFIG_USB_PRINTER=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_WHITEHEAT=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_RIO500=m +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_LED=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_TEST=m +CONFIG_USB_ATM=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_GADGET=m +CONFIG_USB_GADGET_DUMMY_HCD=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=m +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=m +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_STATISTICS=y +CONFIG_XFS_FS=m +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +CONFIG_INOTIFY=y +CONFIG_QUOTA=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m +CONFIG_AUTOFS_FS=m +CONFIG_AUTOFS4_FS=m +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_TMPFS=y +CONFIG_ADFS_FS=m +CONFIG_AFFS_FS=m +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_BEFS_FS=m +CONFIG_BFS_FS=m +CONFIG_EFS_FS=m +CONFIG_JFFS2_FS=m +CONFIG_CRAMFS=y +CONFIG_VXFS_FS=m +CONFIG_MINIX_FS=m +CONFIG_HPFS_FS=m +CONFIG_QNX4FS_FS=m +CONFIG_ROMFS_FS=m +CONFIG_SYSV_FS=m +CONFIG_UFS_FS=m +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=m +CONFIG_NFSD_V4=y +CONFIG_RPCSEC_GSS_SPKM3=m +CONFIG_SMB_FS=m +CONFIG_CIFS=m +CONFIG_NCP_FS=m +CONFIG_NCPFS_PACKET_SIGNING=y +CONFIG_NCPFS_IOCTL_LOCKING=y +CONFIG_NCPFS_STRONG=y +CONFIG_NCPFS_NFS_NS=y +CONFIG_NCPFS_OS2_NS=y +CONFIG_NCPFS_NLS=y +CONFIG_NCPFS_EXTRAS=y +CONFIG_CODA_FS=m +CONFIG_AFS_FS=m +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +CONFIG_ACORN_PARTITION_ICS=y +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=m +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_ASCII=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_SECURITY=y +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRC16=m diff --git a/trunk/arch/arm/configs/prima2_defconfig b/trunk/arch/arm/configs/prima2_defconfig index 807d4e2acb17..c328ac65479a 100644 --- a/trunk/arch/arm/configs/prima2_defconfig +++ b/trunk/arch/arm/configs/prima2_defconfig @@ -1,6 +1,4 @@ CONFIG_EXPERIMENTAL=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_KALLSYMS_ALL=y @@ -10,7 +8,9 @@ CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_BSD_DISKLABEL=y CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_ARCH_SIRF=y +CONFIG_ARCH_PRIMA2=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_KEXEC=y @@ -36,6 +36,7 @@ CONFIG_SPI=y CONFIG_SPI_SIRF=y CONFIG_SPI_SPIDEV=y # CONFIG_HWMON is not set +# CONFIG_HID_SUPPORT is not set CONFIG_USB_GADGET=y CONFIG_USB_FILE_STORAGE=m CONFIG_USB_MASS_STORAGE=m diff --git a/trunk/arch/arm/configs/tct_hammer_defconfig b/trunk/arch/arm/configs/tct_hammer_defconfig index 71277a1591ba..1d24f8458bef 100644 --- a/trunk/arch/arm/configs/tct_hammer_defconfig +++ b/trunk/arch/arm/configs/tct_hammer_defconfig @@ -7,7 +7,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set -# CONFIG_BUGVERBOSE is not set +# CONFIG_BUG is not set # CONFIG_ELF_CORE is not set # CONFIG_SHMEM is not set CONFIG_SLOB=y diff --git a/trunk/arch/arm/configs/tegra_defconfig b/trunk/arch/arm/configs/tegra_defconfig index 0d6bb738c6de..db2245353f0f 100644 --- a/trunk/arch/arm/configs/tegra_defconfig +++ b/trunk/arch/arm/configs/tegra_defconfig @@ -145,8 +145,6 @@ CONFIG_MMC_SDHCI_TEGRA=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_EM3027=y CONFIG_RTC_DRV_TEGRA=y -CONFIG_DMADEVICES=y -CONFIG_TEGRA20_APB_DMA=y CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y diff --git a/trunk/arch/arm/configs/u8500_defconfig b/trunk/arch/arm/configs/u8500_defconfig index da6845493caa..2d4f661d1cf6 100644 --- a/trunk/arch/arm/configs/u8500_defconfig +++ b/trunk/arch/arm/configs/u8500_defconfig @@ -86,7 +86,6 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_LM3530=y CONFIG_LEDS_LP5521=y -CONFIG_LEDS_GPIO=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_AB8500=y CONFIG_RTC_DRV_PL031=y diff --git a/trunk/arch/arm/include/asm/assembler.h b/trunk/arch/arm/include/asm/assembler.h index 5c8b3bf4d825..03fb93621d0d 100644 --- a/trunk/arch/arm/include/asm/assembler.h +++ b/trunk/arch/arm/include/asm/assembler.h @@ -320,12 +320,4 @@ .size \name , . - \name .endm - .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req -#ifndef CONFIG_CPU_USE_DOMAINS - adds \tmp, \addr, #\size - 1 - sbcccs \tmp, \tmp, \limit - bcs \bad -#endif - .endm - #endif /* __ASM_ASSEMBLER_H__ */ diff --git a/trunk/arch/arm/include/asm/dma-mapping.h b/trunk/arch/arm/include/asm/dma-mapping.h index 5c44dcb0987b..2ae842df4551 100644 --- a/trunk/arch/arm/include/asm/dma-mapping.h +++ b/trunk/arch/arm/include/asm/dma-mapping.h @@ -202,13 +202,6 @@ static inline void dma_free_writecombine(struct device *dev, size_t size, return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs); } -/* - * This can be called during early boot to increase the size of the atomic - * coherent DMA pool above the default value of 256KiB. It must be called - * before postcore_initcall. - */ -extern void __init init_dma_coherent_pool_size(unsigned long size); - /* * This can be called during boot to increase the size of the consistent * DMA region above it's default value of 2MB. It must be called before the diff --git a/trunk/arch/arm/include/asm/hardware/iop3xx.h b/trunk/arch/arm/include/asm/hardware/iop3xx.h index 02fe2fbe2477..2ff2c75a4639 100644 --- a/trunk/arch/arm/include/asm/hardware/iop3xx.h +++ b/trunk/arch/arm/include/asm/hardware/iop3xx.h @@ -217,8 +217,18 @@ extern int iop3xx_get_init_atu(void); #define IOP3XX_PCI_LOWER_MEM_PA 0x80000000 #define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000 +#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 #define IOP3XX_PCI_LOWER_IO_PA 0x90000000 -#define IOP3XX_PCI_LOWER_IO_BA 0x00000000 +#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 +#define IOP3XX_PCI_LOWER_IO_BA 0x90000000 +#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ + IOP3XX_PCI_IO_WINDOW_SIZE - 1) +#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ + IOP3XX_PCI_IO_WINDOW_SIZE - 1) +#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\ + IOP3XX_PCI_LOWER_IO_PA) +\ + IOP3XX_PCI_LOWER_IO_VA) + #ifndef __ASSEMBLY__ diff --git a/trunk/arch/arm/include/asm/io.h b/trunk/arch/arm/include/asm/io.h index 8f4db67533e5..815c669fec0a 100644 --- a/trunk/arch/arm/include/asm/io.h +++ b/trunk/arch/arm/include/asm/io.h @@ -113,19 +113,11 @@ static inline void __iomem *__typesafe_io(unsigned long addr) #define __iowmb() do { } while (0) #endif -/* PCI fixed i/o mapping */ -#define PCI_IO_VIRT_BASE 0xfee00000 - -extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); - /* * Now, pick up the machine-defined IO definitions */ #ifdef CONFIG_NEED_MACH_IO_H #include -#elif defined(CONFIG_PCI) -#define IO_SPACE_LIMIT ((resource_size_t)0xfffff) -#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT)) #else #define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT) #endif diff --git a/trunk/arch/arm/include/asm/mach/map.h b/trunk/arch/arm/include/asm/mach/map.h index 195ac2f9d3d3..a6efcdd6fd25 100644 --- a/trunk/arch/arm/include/asm/mach/map.h +++ b/trunk/arch/arm/include/asm/mach/map.h @@ -9,9 +9,6 @@ * * Page table mapping constructs and function prototypes */ -#ifndef __ASM_MACH_MAP_H -#define __ASM_MACH_MAP_H - #include struct map_desc { @@ -37,8 +34,6 @@ struct map_desc { #ifdef CONFIG_MMU extern void iotable_init(struct map_desc *, int); -extern void vm_reserve_area_early(unsigned long addr, unsigned long size, - void *caller); struct mem_type; extern const struct mem_type *get_mem_type(unsigned int type); @@ -49,7 +44,4 @@ extern int ioremap_page(unsigned long virt, unsigned long phys, const struct mem_type *mtype); #else #define iotable_init(map,num) do { } while (0) -#define vm_reserve_area_early(a,s,c) do { } while (0) -#endif - #endif diff --git a/trunk/arch/arm/include/asm/mach/pci.h b/trunk/arch/arm/include/asm/mach/pci.h index db9fedb57f2c..26c511fddf8f 100644 --- a/trunk/arch/arm/include/asm/mach/pci.h +++ b/trunk/arch/arm/include/asm/mach/pci.h @@ -11,8 +11,6 @@ #ifndef __ASM_MACH_PCI_H #define __ASM_MACH_PCI_H -#include - struct pci_sys_data; struct pci_ops; struct pci_bus; @@ -44,8 +42,6 @@ struct pci_sys_data { unsigned long io_offset; /* bus->cpu IO mapping offset */ struct pci_bus *bus; /* PCI bus */ struct list_head resources; /* root bus resources (apertures) */ - struct resource io_res; - char io_res_name[12]; /* Bridge swizzling */ u8 (*swizzle)(struct pci_dev *, u8 *); /* IRQ mapping */ @@ -58,15 +54,6 @@ struct pci_sys_data { */ void pci_common_init(struct hw_pci *); -/* - * Setup early fixed I/O mapping. - */ -#if defined(CONFIG_PCI) -extern void pci_map_io_early(unsigned long pfn); -#else -static inline void pci_map_io_early(unsigned long pfn) {} -#endif - /* * PCI controllers */ diff --git a/trunk/arch/arm/include/asm/memory.h b/trunk/arch/arm/include/asm/memory.h index 5f6ddcc56452..e965f1b560f1 100644 --- a/trunk/arch/arm/include/asm/memory.h +++ b/trunk/arch/arm/include/asm/memory.h @@ -187,7 +187,6 @@ static inline unsigned long __phys_to_virt(unsigned long x) #define __phys_to_virt(x) ((x) - PHYS_OFFSET + PAGE_OFFSET) #endif #endif -#endif /* __ASSEMBLY__ */ #ifndef PHYS_OFFSET #ifdef PLAT_PHYS_OFFSET @@ -197,8 +196,6 @@ static inline unsigned long __phys_to_virt(unsigned long x) #endif #endif -#ifndef __ASSEMBLY__ - /* * PFNs are used to describe any physical page; this means * PFN 0 == physical address 0. diff --git a/trunk/arch/arm/include/asm/perf_event.h b/trunk/arch/arm/include/asm/perf_event.h index 625cd621a436..e074948d8143 100644 --- a/trunk/arch/arm/include/asm/perf_event.h +++ b/trunk/arch/arm/include/asm/perf_event.h @@ -12,13 +12,6 @@ #ifndef __ARM_PERF_EVENT_H__ #define __ARM_PERF_EVENT_H__ -/* - * The ARMv7 CPU PMU supports up to 32 event counters. - */ -#define ARMPMU_MAX_HWEVENTS 32 - -#define HW_OP_UNSUPPORTED 0xFFFF -#define C(_x) PERF_COUNT_HW_CACHE_##_x -#define CACHE_OP_UNSUPPORTED 0xFFFF +/* Nothing to see here... */ #endif /* __ARM_PERF_EVENT_H__ */ diff --git a/trunk/arch/arm/include/asm/pgtable.h b/trunk/arch/arm/include/asm/pgtable.h index 41dc31f834c3..f66626d71e7d 100644 --- a/trunk/arch/arm/include/asm/pgtable.h +++ b/trunk/arch/arm/include/asm/pgtable.h @@ -195,18 +195,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) -#define pte_none(pte) (!pte_val(pte)) -#define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) -#define pte_write(pte) (!(pte_val(pte) & L_PTE_RDONLY)) -#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) -#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) -#define pte_exec(pte) (!(pte_val(pte) & L_PTE_XN)) -#define pte_special(pte) (0) - -#define pte_present_user(pte) \ - ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \ - (L_PTE_PRESENT | L_PTE_USER)) - #if __LINUX_ARM_ARCH__ < 6 static inline void __sync_icache_dcache(pte_t pteval) { @@ -218,16 +206,26 @@ extern void __sync_icache_dcache(pte_t pteval); static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) { - unsigned long ext = 0; - - if (addr < TASK_SIZE && pte_present_user(pteval)) { + if (addr >= TASK_SIZE) + set_pte_ext(ptep, pteval, 0); + else { __sync_icache_dcache(pteval); - ext |= PTE_EXT_NG; + set_pte_ext(ptep, pteval, PTE_EXT_NG); } - - set_pte_ext(ptep, pteval, ext); } +#define pte_none(pte) (!pte_val(pte)) +#define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) +#define pte_write(pte) (!(pte_val(pte) & L_PTE_RDONLY)) +#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) +#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) +#define pte_exec(pte) (!(pte_val(pte) & L_PTE_XN)) +#define pte_special(pte) (0) + +#define pte_present_user(pte) \ + ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \ + (L_PTE_PRESENT | L_PTE_USER)) + #define PTE_BIT_FUNC(fn,op) \ static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } @@ -253,13 +251,13 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) * * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * <--------------- offset ----------------------> < type -> 0 0 0 + * <--------------- offset --------------------> <- type --> 0 0 0 * - * This gives us up to 31 swap files and 64GB per swap file. Note that + * This gives us up to 63 swap files and 32GB per swap file. Note that * the offset field is always non-zero. */ #define __SWP_TYPE_SHIFT 3 -#define __SWP_TYPE_BITS 5 +#define __SWP_TYPE_BITS 6 #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) diff --git a/trunk/arch/arm/include/asm/pmu.h b/trunk/arch/arm/include/asm/pmu.h index a26170dce02e..4432305f4a2a 100644 --- a/trunk/arch/arm/include/asm/pmu.h +++ b/trunk/arch/arm/include/asm/pmu.h @@ -15,6 +15,15 @@ #include #include +/* + * Types of PMUs that can be accessed directly and require mutual + * exclusion between profiling tools. + */ +enum arm_pmu_type { + ARM_PMU_DEVICE_CPU = 0, + ARM_NUM_PMU_DEVICES, +}; + /* * struct arm_pmu_platdata - ARM PMU platform data * @@ -22,24 +31,54 @@ * interrupt and passed the address of the low level handler, * and can be used to implement any platform specific handling * before or after calling it. - * @runtime_resume: an optional handler which will be called by the - * runtime PM framework following a call to pm_runtime_get(). - * Note that if pm_runtime_get() is called more than once in - * succession this handler will only be called once. - * @runtime_suspend: an optional handler which will be called by the - * runtime PM framework following a call to pm_runtime_put(). - * Note that if pm_runtime_get() is called more than once in - * succession this handler will only be called following the - * final call to pm_runtime_put() that actually disables the - * hardware. + * @enable_irq: an optional handler which will be called after + * request_irq and be used to handle some platform specific + * irq enablement + * @disable_irq: an optional handler which will be called before + * free_irq and be used to handle some platform specific + * irq disablement */ struct arm_pmu_platdata { irqreturn_t (*handle_irq)(int irq, void *dev, irq_handler_t pmu_handler); - int (*runtime_resume)(struct device *dev); - int (*runtime_suspend)(struct device *dev); + void (*enable_irq)(int irq); + void (*disable_irq)(int irq); }; +#ifdef CONFIG_CPU_HAS_PMU + +/** + * reserve_pmu() - reserve the hardware performance counters + * + * Reserve the hardware performance counters in the system for exclusive use. + * Returns 0 on success or -EBUSY if the lock is already held. + */ +extern int +reserve_pmu(enum arm_pmu_type type); + +/** + * release_pmu() - Relinquish control of the performance counters + * + * Release the performance counters and allow someone else to use them. + */ +extern void +release_pmu(enum arm_pmu_type type); + +#else /* CONFIG_CPU_HAS_PMU */ + +#include + +static inline int +reserve_pmu(enum arm_pmu_type type) +{ + return -ENODEV; +} + +static inline void +release_pmu(enum arm_pmu_type type) { } + +#endif /* CONFIG_CPU_HAS_PMU */ + #ifdef CONFIG_HW_PERF_EVENTS /* The events for a given PMU register set. */ @@ -64,6 +103,7 @@ struct pmu_hw_events { struct arm_pmu { struct pmu pmu; + enum arm_pmu_type type; cpumask_t active_irqs; char *name; irqreturn_t (*handle_irq)(int irq_num, void *dev); @@ -78,8 +118,6 @@ struct arm_pmu { void (*start)(void); void (*stop)(void); void (*reset)(void *); - int (*request_irq)(irq_handler_t handler); - void (*free_irq)(void); int (*map_event)(struct perf_event *event); int num_events; atomic_t active_events; @@ -91,9 +129,7 @@ struct arm_pmu { #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) -extern const struct dev_pm_ops armpmu_dev_pm_ops; - -int armpmu_register(struct arm_pmu *armpmu, char *name, int type); +int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type); u64 armpmu_event_update(struct perf_event *event, struct hw_perf_event *hwc, @@ -103,13 +139,6 @@ int armpmu_event_set_period(struct perf_event *event, struct hw_perf_event *hwc, int idx); -int armpmu_map_event(struct perf_event *event, - const unsigned (*event_map)[PERF_COUNT_HW_MAX], - const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], - u32 raw_event_mask); - #endif /* CONFIG_HW_PERF_EVENTS */ #endif /* __ARM_PMU_H__ */ diff --git a/trunk/arch/arm/include/asm/sched_clock.h b/trunk/arch/arm/include/asm/sched_clock.h index 05b8e82ec9f5..e3f757263438 100644 --- a/trunk/arch/arm/include/asm/sched_clock.h +++ b/trunk/arch/arm/include/asm/sched_clock.h @@ -10,7 +10,5 @@ extern void sched_clock_postinit(void); extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate); -extern void setup_sched_clock_needs_suspend(u32 (*read)(void), int bits, - unsigned long rate); #endif diff --git a/trunk/arch/arm/include/asm/tlb.h b/trunk/arch/arm/include/asm/tlb.h index 99a19512ee26..314d4664eae7 100644 --- a/trunk/arch/arm/include/asm/tlb.h +++ b/trunk/arch/arm/include/asm/tlb.h @@ -199,9 +199,6 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, { pgtable_page_dtor(pte); -#ifdef CONFIG_ARM_LPAE - tlb_add_flush(tlb, addr); -#else /* * With the classic ARM MMU, a pte page has two corresponding pmd * entries, each covering 1MB. @@ -209,7 +206,6 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte, addr &= PMD_MASK; tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE); tlb_add_flush(tlb, addr + SZ_1M); -#endif tlb_remove_page(tlb, pte); } diff --git a/trunk/arch/arm/include/asm/uaccess.h b/trunk/arch/arm/include/asm/uaccess.h index 77bd79f2ffdb..479a6352e0b5 100644 --- a/trunk/arch/arm/include/asm/uaccess.h +++ b/trunk/arch/arm/include/asm/uaccess.h @@ -101,39 +101,28 @@ extern int __get_user_1(void *); extern int __get_user_2(void *); extern int __get_user_4(void *); -#define __GUP_CLOBBER_1 "lr", "cc" -#ifdef CONFIG_CPU_USE_DOMAINS -#define __GUP_CLOBBER_2 "ip", "lr", "cc" -#else -#define __GUP_CLOBBER_2 "lr", "cc" -#endif -#define __GUP_CLOBBER_4 "lr", "cc" - -#define __get_user_x(__r2,__p,__e,__l,__s) \ +#define __get_user_x(__r2,__p,__e,__s,__i...) \ __asm__ __volatile__ ( \ __asmeq("%0", "r0") __asmeq("%1", "r2") \ - __asmeq("%3", "r1") \ "bl __get_user_" #__s \ : "=&r" (__e), "=r" (__r2) \ - : "0" (__p), "r" (__l) \ - : __GUP_CLOBBER_##__s) + : "0" (__p) \ + : __i, "cc") -#define __get_user_check(x,p) \ +#define get_user(x,p) \ ({ \ - unsigned long __limit = current_thread_info()->addr_limit - 1; \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ register unsigned long __r2 asm("r2"); \ - register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ switch (sizeof(*(__p))) { \ case 1: \ - __get_user_x(__r2, __p, __e, __l, 1); \ - break; \ + __get_user_x(__r2, __p, __e, 1, "lr"); \ + break; \ case 2: \ - __get_user_x(__r2, __p, __e, __l, 2); \ + __get_user_x(__r2, __p, __e, 2, "r3", "lr"); \ break; \ case 4: \ - __get_user_x(__r2, __p, __e, __l, 4); \ + __get_user_x(__r2, __p, __e, 4, "lr"); \ break; \ default: __e = __get_user_bad(); break; \ } \ @@ -141,57 +130,42 @@ extern int __get_user_4(void *); __e; \ }) -#define get_user(x,p) \ - ({ \ - might_fault(); \ - __get_user_check(x,p); \ - }) - extern int __put_user_1(void *, unsigned int); extern int __put_user_2(void *, unsigned int); extern int __put_user_4(void *, unsigned int); extern int __put_user_8(void *, unsigned long long); -#define __put_user_x(__r2,__p,__e,__l,__s) \ +#define __put_user_x(__r2,__p,__e,__s) \ __asm__ __volatile__ ( \ __asmeq("%0", "r0") __asmeq("%2", "r2") \ - __asmeq("%3", "r1") \ "bl __put_user_" #__s \ : "=&r" (__e) \ - : "0" (__p), "r" (__r2), "r" (__l) \ + : "0" (__p), "r" (__r2) \ : "ip", "lr", "cc") -#define __put_user_check(x,p) \ +#define put_user(x,p) \ ({ \ - unsigned long __limit = current_thread_info()->addr_limit - 1; \ register const typeof(*(p)) __r2 asm("r2") = (x); \ register const typeof(*(p)) __user *__p asm("r0") = (p);\ - register unsigned long __l asm("r1") = __limit; \ register int __e asm("r0"); \ switch (sizeof(*(__p))) { \ case 1: \ - __put_user_x(__r2, __p, __e, __l, 1); \ + __put_user_x(__r2, __p, __e, 1); \ break; \ case 2: \ - __put_user_x(__r2, __p, __e, __l, 2); \ + __put_user_x(__r2, __p, __e, 2); \ break; \ case 4: \ - __put_user_x(__r2, __p, __e, __l, 4); \ + __put_user_x(__r2, __p, __e, 4); \ break; \ case 8: \ - __put_user_x(__r2, __p, __e, __l, 8); \ + __put_user_x(__r2, __p, __e, 8); \ break; \ default: __e = __put_user_bad(); break; \ } \ __e; \ }) -#define put_user(x,p) \ - ({ \ - might_fault(); \ - __put_user_check(x,p); \ - }) - #else /* CONFIG_MMU */ /* @@ -245,7 +219,6 @@ do { \ unsigned long __gu_addr = (unsigned long)(ptr); \ unsigned long __gu_val; \ __chk_user_ptr(ptr); \ - might_fault(); \ switch (sizeof(*(ptr))) { \ case 1: __get_user_asm_byte(__gu_val,__gu_addr,err); break; \ case 2: __get_user_asm_half(__gu_val,__gu_addr,err); break; \ @@ -327,7 +300,6 @@ do { \ unsigned long __pu_addr = (unsigned long)(ptr); \ __typeof__(*(ptr)) __pu_val = (x); \ __chk_user_ptr(ptr); \ - might_fault(); \ switch (sizeof(*(ptr))) { \ case 1: __put_user_asm_byte(__pu_val,__pu_addr,err); break; \ case 2: __put_user_asm_half(__pu_val,__pu_addr,err); break; \ diff --git a/trunk/arch/arm/include/asm/unistd.h b/trunk/arch/arm/include/asm/unistd.h index 2fde5fd1acce..0cab47d4a83f 100644 --- a/trunk/arch/arm/include/asm/unistd.h +++ b/trunk/arch/arm/include/asm/unistd.h @@ -404,7 +404,6 @@ #define __NR_setns (__NR_SYSCALL_BASE+375) #define __NR_process_vm_readv (__NR_SYSCALL_BASE+376) #define __NR_process_vm_writev (__NR_SYSCALL_BASE+377) - /* 378 for kcmp */ /* * The following SWIs are ARM private. @@ -484,7 +483,6 @@ */ #define __IGNORE_fadvise64_64 #define __IGNORE_migrate_pages -#define __IGNORE_kcmp #endif /* __KERNEL__ */ #endif /* __ASM_ARM_UNISTD_H */ diff --git a/trunk/arch/arm/kernel/Makefile b/trunk/arch/arm/kernel/Makefile index 1c4321430737..7ad2d5cf7008 100644 --- a/trunk/arch/arm/kernel/Makefile +++ b/trunk/arch/arm/kernel/Makefile @@ -69,7 +69,8 @@ obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o -obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o +obj-$(CONFIG_CPU_HAS_PMU) += pmu.o +obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o diff --git a/trunk/arch/arm/kernel/bios32.c b/trunk/arch/arm/kernel/bios32.c index 9b722612553d..2b2f25e7fef5 100644 --- a/trunk/arch/arm/kernel/bios32.c +++ b/trunk/arch/arm/kernel/bios32.c @@ -13,7 +13,6 @@ #include #include -#include #include static int debug_pci; @@ -271,6 +270,15 @@ static void __devinit pci_fixup_it8152(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152); + + +void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) +{ + if (debug_pci) + printk("PCI: Assigning IRQ %02d to %s\n", irq, pci_name(dev)); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); +} + /* * If the bus contains any of these devices, then we must not turn on * parity checking of any kind. Currently this is CyberPro 20x0 only. @@ -415,38 +423,6 @@ static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) return irq; } -static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys) -{ - int ret; - struct pci_host_bridge_window *window; - - if (list_empty(&sys->resources)) { - pci_add_resource_offset(&sys->resources, - &iomem_resource, sys->mem_offset); - } - - list_for_each_entry(window, &sys->resources, list) { - if (resource_type(window->res) == IORESOURCE_IO) - return 0; - } - - sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io; - sys->io_res.end = (busnr + 1) * SZ_64K - 1; - sys->io_res.flags = IORESOURCE_IO; - sys->io_res.name = sys->io_res_name; - sprintf(sys->io_res_name, "PCI%d I/O", busnr); - - ret = request_resource(&ioport_resource, &sys->io_res); - if (ret) { - pr_err("PCI: unable to allocate I/O port region (%d)\n", ret); - return ret; - } - pci_add_resource_offset(&sys->resources, &sys->io_res, - sys->io_offset); - - return 0; -} - static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) { struct pci_sys_data *sys = NULL; @@ -469,10 +445,11 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head) ret = hw->setup(nr, sys); if (ret > 0) { - ret = pcibios_init_resources(nr, sys); - if (ret) { - kfree(sys); - break; + if (list_empty(&sys->resources)) { + pci_add_resource_offset(&sys->resources, + &ioport_resource, sys->io_offset); + pci_add_resource_offset(&sys->resources, + &iomem_resource, sys->mem_offset); } if (hw->scan) @@ -650,15 +627,3 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, return 0; } - -void __init pci_map_io_early(unsigned long pfn) -{ - struct map_desc pci_io_desc = { - .virtual = PCI_IO_VIRT_BASE, - .type = MT_DEVICE, - .length = SZ_64K, - }; - - pci_io_desc.pfn = pfn; - iotable_init(&pci_io_desc, 1); -} diff --git a/trunk/arch/arm/kernel/calls.S b/trunk/arch/arm/kernel/calls.S index e337879595e5..463ff4a0ec8a 100644 --- a/trunk/arch/arm/kernel/calls.S +++ b/trunk/arch/arm/kernel/calls.S @@ -387,7 +387,6 @@ /* 375 */ CALL(sys_setns) CALL(sys_process_vm_readv) CALL(sys_process_vm_writev) - CALL(sys_ni_syscall) /* reserved for sys_kcmp */ #ifndef syscalls_counted .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls #define syscalls_counted diff --git a/trunk/arch/arm/kernel/hw_breakpoint.c b/trunk/arch/arm/kernel/hw_breakpoint.c index 281bf3301241..ba386bd94107 100644 --- a/trunk/arch/arm/kernel/hw_breakpoint.c +++ b/trunk/arch/arm/kernel/hw_breakpoint.c @@ -159,12 +159,6 @@ static int debug_arch_supported(void) arch >= ARM_DEBUG_ARCH_V7_1; } -/* Can we determine the watchpoint access type from the fsr? */ -static int debug_exception_updates_fsr(void) -{ - return 0; -} - /* Determine number of WRP registers available. */ static int get_num_wrp_resources(void) { @@ -610,14 +604,13 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) /* Aligned */ break; case 1: + /* Allow single byte watchpoint. */ + if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) + break; case 2: /* Allow halfword watchpoints and breakpoints. */ if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) break; - case 3: - /* Allow single byte watchpoint. */ - if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) - break; default: ret = -EINVAL; goto out; @@ -626,35 +619,18 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp) info->address &= ~alignment_mask; info->ctrl.len <<= offset; - if (!bp->overflow_handler) { - /* - * Mismatch breakpoints are required for single-stepping - * breakpoints. - */ - if (!core_has_mismatch_brps()) - return -EINVAL; - - /* We don't allow mismatch breakpoints in kernel space. */ - if (arch_check_bp_in_kernelspace(bp)) - return -EPERM; - - /* - * Per-cpu breakpoints are not supported by our stepping - * mechanism. - */ - if (!bp->hw.bp_target) - return -EINVAL; - - /* - * We only support specific access types if the fsr - * reports them. - */ - if (!debug_exception_updates_fsr() && - (info->ctrl.type == ARM_BREAKPOINT_LOAD || - info->ctrl.type == ARM_BREAKPOINT_STORE)) - return -EINVAL; + /* + * Currently we rely on an overflow handler to take + * care of single-stepping the breakpoint when it fires. + * In the case of userspace breakpoints on a core with V7 debug, + * we can use the mismatch feature as a poor-man's hardware + * single-step, but this only works for per-task breakpoints. + */ + if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) || + !core_has_mismatch_brps() || !bp->hw.bp_target)) { + pr_warning("overflow handler required but none found\n"); + ret = -EINVAL; } - out: return ret; } @@ -730,12 +706,10 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, goto unlock; /* Check that the access type matches. */ - if (debug_exception_updates_fsr()) { - access = (fsr & ARM_FSR_ACCESS_MASK) ? - HW_BREAKPOINT_W : HW_BREAKPOINT_R; - if (!(access & hw_breakpoint_type(wp))) - goto unlock; - } + access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W : + HW_BREAKPOINT_R; + if (!(access & hw_breakpoint_type(wp))) + goto unlock; /* We have a winner. */ info->trigger = addr; diff --git a/trunk/arch/arm/kernel/perf_event.c b/trunk/arch/arm/kernel/perf_event.c index 93971b1a4f0b..ab243b87118d 100644 --- a/trunk/arch/arm/kernel/perf_event.c +++ b/trunk/arch/arm/kernel/perf_event.c @@ -12,15 +12,68 @@ */ #define pr_fmt(fmt) "hw perfevents: " fmt +#include +#include #include +#include +#include #include -#include +#include #include +#include +#include #include #include #include +/* + * ARMv6 supports a maximum of 3 events, starting from index 0. If we add + * another platform that supports more, we need to increase this to be the + * largest of all platforms. + * + * ARMv7 supports up to 32 events: + * cycle counter CCNT + 31 events counters CNT0..30. + * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. + */ +#define ARMPMU_MAX_HWEVENTS 32 + +static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); +static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); +static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); + +#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu)) + +/* Set at runtime when we know what CPU type we are. */ +static struct arm_pmu *cpu_pmu; + +const char *perf_pmu_name(void) +{ + if (!cpu_pmu) + return NULL; + + return cpu_pmu->pmu.name; +} +EXPORT_SYMBOL_GPL(perf_pmu_name); + +int perf_num_counters(void) +{ + int max_events = 0; + + if (cpu_pmu != NULL) + max_events = cpu_pmu->num_events; + + return max_events; +} +EXPORT_SYMBOL_GPL(perf_num_counters); + +#define HW_OP_UNSUPPORTED 0xFFFF + +#define C(_x) \ + PERF_COUNT_HW_CACHE_##_x + +#define CACHE_OP_UNSUPPORTED 0xFFFF + static int armpmu_map_cache_event(const unsigned (*cache_map) [PERF_COUNT_HW_CACHE_MAX] @@ -51,7 +104,7 @@ armpmu_map_cache_event(const unsigned (*cache_map) } static int -armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) +armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config) { int mapping = (*event_map)[config]; return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping; @@ -63,20 +116,19 @@ armpmu_map_raw_event(u32 raw_event_mask, u64 config) return (int)(config & raw_event_mask); } -int -armpmu_map_event(struct perf_event *event, - const unsigned (*event_map)[PERF_COUNT_HW_MAX], - const unsigned (*cache_map) - [PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX], - u32 raw_event_mask) +static int map_cpu_event(struct perf_event *event, + const unsigned (*event_map)[PERF_COUNT_HW_MAX], + const unsigned (*cache_map) + [PERF_COUNT_HW_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX], + u32 raw_event_mask) { u64 config = event->attr.config; switch (event->attr.type) { case PERF_TYPE_HARDWARE: - return armpmu_map_hw_event(event_map, config); + return armpmu_map_event(event_map, config); case PERF_TYPE_HW_CACHE: return armpmu_map_cache_event(cache_map, config); case PERF_TYPE_RAW: @@ -170,6 +222,7 @@ armpmu_stop(struct perf_event *event, int flags) */ if (!(hwc->state & PERF_HES_STOPPED)) { armpmu->disable(hwc, hwc->idx); + barrier(); /* why? */ armpmu_event_update(event, hwc, hwc->idx); hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; } @@ -297,41 +350,99 @@ validate_group(struct perf_event *event) return 0; } -static irqreturn_t armpmu_dispatch_irq(int irq, void *dev) +static irqreturn_t armpmu_platform_irq(int irq, void *dev) { struct arm_pmu *armpmu = (struct arm_pmu *) dev; struct platform_device *plat_device = armpmu->plat_device; struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev); - if (plat && plat->handle_irq) - return plat->handle_irq(irq, dev, armpmu->handle_irq); - else - return armpmu->handle_irq(irq, dev); + return plat->handle_irq(irq, dev, armpmu->handle_irq); } static void armpmu_release_hardware(struct arm_pmu *armpmu) { - armpmu->free_irq(); - pm_runtime_put_sync(&armpmu->plat_device->dev); + int i, irq, irqs; + struct platform_device *pmu_device = armpmu->plat_device; + struct arm_pmu_platdata *plat = + dev_get_platdata(&pmu_device->dev); + + irqs = min(pmu_device->num_resources, num_possible_cpus()); + + for (i = 0; i < irqs; ++i) { + if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs)) + continue; + irq = platform_get_irq(pmu_device, i); + if (irq >= 0) { + if (plat && plat->disable_irq) + plat->disable_irq(irq); + free_irq(irq, armpmu); + } + } + + release_pmu(armpmu->type); } static int armpmu_reserve_hardware(struct arm_pmu *armpmu) { - int err; + struct arm_pmu_platdata *plat; + irq_handler_t handle_irq; + int i, err, irq, irqs; struct platform_device *pmu_device = armpmu->plat_device; if (!pmu_device) return -ENODEV; - pm_runtime_get_sync(&pmu_device->dev); - err = armpmu->request_irq(armpmu_dispatch_irq); + err = reserve_pmu(armpmu->type); if (err) { - armpmu_release_hardware(armpmu); + pr_warning("unable to reserve pmu\n"); return err; } + plat = dev_get_platdata(&pmu_device->dev); + if (plat && plat->handle_irq) + handle_irq = armpmu_platform_irq; + else + handle_irq = armpmu->handle_irq; + + irqs = min(pmu_device->num_resources, num_possible_cpus()); + if (irqs < 1) { + pr_err("no irqs for PMUs defined\n"); + return -ENODEV; + } + + for (i = 0; i < irqs; ++i) { + err = 0; + irq = platform_get_irq(pmu_device, i); + if (irq < 0) + continue; + + /* + * If we have a single PMU interrupt that we can't shift, + * assume that we're running on a uniprocessor machine and + * continue. Otherwise, continue without this interrupt. + */ + if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { + pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", + irq, i); + continue; + } + + err = request_irq(irq, handle_irq, + IRQF_DISABLED | IRQF_NOBALANCING, + "arm-pmu", armpmu); + if (err) { + pr_err("unable to request IRQ%d for ARM PMU counters\n", + irq); + armpmu_release_hardware(armpmu); + return err; + } else if (plat && plat->enable_irq) + plat->enable_irq(irq); + + cpumask_set_cpu(i, &armpmu->active_irqs); + } + return 0; } @@ -470,32 +581,6 @@ static void armpmu_disable(struct pmu *pmu) armpmu->stop(); } -#ifdef CONFIG_PM_RUNTIME -static int armpmu_runtime_resume(struct device *dev) -{ - struct arm_pmu_platdata *plat = dev_get_platdata(dev); - - if (plat && plat->runtime_resume) - return plat->runtime_resume(dev); - - return 0; -} - -static int armpmu_runtime_suspend(struct device *dev) -{ - struct arm_pmu_platdata *plat = dev_get_platdata(dev); - - if (plat && plat->runtime_suspend) - return plat->runtime_suspend(dev); - - return 0; -} -#endif - -const struct dev_pm_ops armpmu_dev_pm_ops = { - SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL) -}; - static void __init armpmu_init(struct arm_pmu *armpmu) { atomic_set(&armpmu->active_events, 0); @@ -513,14 +598,174 @@ static void __init armpmu_init(struct arm_pmu *armpmu) }; } -int armpmu_register(struct arm_pmu *armpmu, char *name, int type) +int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type) { armpmu_init(armpmu); - pr_info("enabled with %s PMU driver, %d counters available\n", - armpmu->name, armpmu->num_events); return perf_pmu_register(&armpmu->pmu, name, type); } +/* Include the PMU-specific implementations. */ +#include "perf_event_xscale.c" +#include "perf_event_v6.c" +#include "perf_event_v7.c" + +/* + * Ensure the PMU has sane values out of reset. + * This requires SMP to be available, so exists as a separate initcall. + */ +static int __init +cpu_pmu_reset(void) +{ + if (cpu_pmu && cpu_pmu->reset) + return on_each_cpu(cpu_pmu->reset, NULL, 1); + return 0; +} +arch_initcall(cpu_pmu_reset); + +/* + * PMU platform driver and devicetree bindings. + */ +static struct of_device_id armpmu_of_device_ids[] = { + {.compatible = "arm,cortex-a9-pmu"}, + {.compatible = "arm,cortex-a8-pmu"}, + {.compatible = "arm,arm1136-pmu"}, + {.compatible = "arm,arm1176-pmu"}, + {}, +}; + +static struct platform_device_id armpmu_plat_device_ids[] = { + {.name = "arm-pmu"}, + {}, +}; + +static int __devinit armpmu_device_probe(struct platform_device *pdev) +{ + if (!cpu_pmu) + return -ENODEV; + + cpu_pmu->plat_device = pdev; + return 0; +} + +static struct platform_driver armpmu_driver = { + .driver = { + .name = "arm-pmu", + .of_match_table = armpmu_of_device_ids, + }, + .probe = armpmu_device_probe, + .id_table = armpmu_plat_device_ids, +}; + +static int __init register_pmu_driver(void) +{ + return platform_driver_register(&armpmu_driver); +} +device_initcall(register_pmu_driver); + +static struct pmu_hw_events *armpmu_get_cpu_events(void) +{ + return &__get_cpu_var(cpu_hw_events); +} + +static void __init cpu_pmu_init(struct arm_pmu *armpmu) +{ + int cpu; + for_each_possible_cpu(cpu) { + struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); + events->events = per_cpu(hw_events, cpu); + events->used_mask = per_cpu(used_mask, cpu); + raw_spin_lock_init(&events->pmu_lock); + } + armpmu->get_hw_events = armpmu_get_cpu_events; + armpmu->type = ARM_PMU_DEVICE_CPU; +} + +/* + * PMU hardware loses all context when a CPU goes offline. + * When a CPU is hotplugged back in, since some hardware registers are + * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading + * junk values out of them. + */ +static int __cpuinit pmu_cpu_notify(struct notifier_block *b, + unsigned long action, void *hcpu) +{ + if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) + return NOTIFY_DONE; + + if (cpu_pmu && cpu_pmu->reset) + cpu_pmu->reset(NULL); + + return NOTIFY_OK; +} + +static struct notifier_block __cpuinitdata pmu_cpu_notifier = { + .notifier_call = pmu_cpu_notify, +}; + +/* + * CPU PMU identification and registration. + */ +static int __init +init_hw_perf_events(void) +{ + unsigned long cpuid = read_cpuid_id(); + unsigned long implementor = (cpuid & 0xFF000000) >> 24; + unsigned long part_number = (cpuid & 0xFFF0); + + /* ARM Ltd CPUs. */ + if (0x41 == implementor) { + switch (part_number) { + case 0xB360: /* ARM1136 */ + case 0xB560: /* ARM1156 */ + case 0xB760: /* ARM1176 */ + cpu_pmu = armv6pmu_init(); + break; + case 0xB020: /* ARM11mpcore */ + cpu_pmu = armv6mpcore_pmu_init(); + break; + case 0xC080: /* Cortex-A8 */ + cpu_pmu = armv7_a8_pmu_init(); + break; + case 0xC090: /* Cortex-A9 */ + cpu_pmu = armv7_a9_pmu_init(); + break; + case 0xC050: /* Cortex-A5 */ + cpu_pmu = armv7_a5_pmu_init(); + break; + case 0xC0F0: /* Cortex-A15 */ + cpu_pmu = armv7_a15_pmu_init(); + break; + case 0xC070: /* Cortex-A7 */ + cpu_pmu = armv7_a7_pmu_init(); + break; + } + /* Intel CPUs [xscale]. */ + } else if (0x69 == implementor) { + part_number = (cpuid >> 13) & 0x7; + switch (part_number) { + case 1: + cpu_pmu = xscale1pmu_init(); + break; + case 2: + cpu_pmu = xscale2pmu_init(); + break; + } + } + + if (cpu_pmu) { + pr_info("enabled with %s PMU driver, %d counters available\n", + cpu_pmu->name, cpu_pmu->num_events); + cpu_pmu_init(cpu_pmu); + register_cpu_notifier(&pmu_cpu_notifier); + armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); + } else { + pr_info("no hardware support available\n"); + } + + return 0; +} +early_initcall(init_hw_perf_events); + /* * Callchain handling code. */ diff --git a/trunk/arch/arm/kernel/perf_event_cpu.c b/trunk/arch/arm/kernel/perf_event_cpu.c deleted file mode 100644 index 8d7d8d4de9d6..000000000000 --- a/trunk/arch/arm/kernel/perf_event_cpu.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2012 ARM Limited - * - * Author: Will Deacon - */ -#define pr_fmt(fmt) "CPU PMU: " fmt - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -/* Set at runtime when we know what CPU type we are. */ -static struct arm_pmu *cpu_pmu; - -static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events); -static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask); -static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events); - -/* - * Despite the names, these two functions are CPU-specific and are used - * by the OProfile/perf code. - */ -const char *perf_pmu_name(void) -{ - if (!cpu_pmu) - return NULL; - - return cpu_pmu->pmu.name; -} -EXPORT_SYMBOL_GPL(perf_pmu_name); - -int perf_num_counters(void) -{ - int max_events = 0; - - if (cpu_pmu != NULL) - max_events = cpu_pmu->num_events; - - return max_events; -} -EXPORT_SYMBOL_GPL(perf_num_counters); - -/* Include the PMU-specific implementations. */ -#include "perf_event_xscale.c" -#include "perf_event_v6.c" -#include "perf_event_v7.c" - -static struct pmu_hw_events *cpu_pmu_get_cpu_events(void) -{ - return &__get_cpu_var(cpu_hw_events); -} - -static void cpu_pmu_free_irq(void) -{ - int i, irq, irqs; - struct platform_device *pmu_device = cpu_pmu->plat_device; - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - - for (i = 0; i < irqs; ++i) { - if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs)) - continue; - irq = platform_get_irq(pmu_device, i); - if (irq >= 0) - free_irq(irq, cpu_pmu); - } -} - -static int cpu_pmu_request_irq(irq_handler_t handler) -{ - int i, err, irq, irqs; - struct platform_device *pmu_device = cpu_pmu->plat_device; - - if (!pmu_device) - return -ENODEV; - - irqs = min(pmu_device->num_resources, num_possible_cpus()); - if (irqs < 1) { - pr_err("no irqs for PMUs defined\n"); - return -ENODEV; - } - - for (i = 0; i < irqs; ++i) { - err = 0; - irq = platform_get_irq(pmu_device, i); - if (irq < 0) - continue; - - /* - * If we have a single PMU interrupt that we can't shift, - * assume that we're running on a uniprocessor machine and - * continue. Otherwise, continue without this interrupt. - */ - if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) { - pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n", - irq, i); - continue; - } - - err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu", - cpu_pmu); - if (err) { - pr_err("unable to request IRQ%d for ARM PMU counters\n", - irq); - return err; - } - - cpumask_set_cpu(i, &cpu_pmu->active_irqs); - } - - return 0; -} - -static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu) -{ - int cpu; - for_each_possible_cpu(cpu) { - struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu); - events->events = per_cpu(hw_events, cpu); - events->used_mask = per_cpu(used_mask, cpu); - raw_spin_lock_init(&events->pmu_lock); - } - - cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events; - cpu_pmu->request_irq = cpu_pmu_request_irq; - cpu_pmu->free_irq = cpu_pmu_free_irq; - - /* Ensure the PMU has sane values out of reset. */ - if (cpu_pmu && cpu_pmu->reset) - on_each_cpu(cpu_pmu->reset, NULL, 1); -} - -/* - * PMU hardware loses all context when a CPU goes offline. - * When a CPU is hotplugged back in, since some hardware registers are - * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading - * junk values out of them. - */ -static int __cpuinit cpu_pmu_notify(struct notifier_block *b, - unsigned long action, void *hcpu) -{ - if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING) - return NOTIFY_DONE; - - if (cpu_pmu && cpu_pmu->reset) - cpu_pmu->reset(NULL); - - return NOTIFY_OK; -} - -static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = { - .notifier_call = cpu_pmu_notify, -}; - -/* - * PMU platform driver and devicetree bindings. - */ -static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = { - {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, - {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, - {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, - {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, - {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, - {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init}, - {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init}, - {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init}, - {}, -}; - -static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = { - {.name = "arm-pmu"}, - {}, -}; - -/* - * CPU PMU identification and probing. - */ -static struct arm_pmu *__devinit probe_current_pmu(void) -{ - struct arm_pmu *pmu = NULL; - int cpu = get_cpu(); - unsigned long cpuid = read_cpuid_id(); - unsigned long implementor = (cpuid & 0xFF000000) >> 24; - unsigned long part_number = (cpuid & 0xFFF0); - - pr_info("probing PMU on CPU %d\n", cpu); - - /* ARM Ltd CPUs. */ - if (0x41 == implementor) { - switch (part_number) { - case 0xB360: /* ARM1136 */ - case 0xB560: /* ARM1156 */ - case 0xB760: /* ARM1176 */ - pmu = armv6pmu_init(); - break; - case 0xB020: /* ARM11mpcore */ - pmu = armv6mpcore_pmu_init(); - break; - case 0xC080: /* Cortex-A8 */ - pmu = armv7_a8_pmu_init(); - break; - case 0xC090: /* Cortex-A9 */ - pmu = armv7_a9_pmu_init(); - break; - case 0xC050: /* Cortex-A5 */ - pmu = armv7_a5_pmu_init(); - break; - case 0xC0F0: /* Cortex-A15 */ - pmu = armv7_a15_pmu_init(); - break; - case 0xC070: /* Cortex-A7 */ - pmu = armv7_a7_pmu_init(); - break; - } - /* Intel CPUs [xscale]. */ - } else if (0x69 == implementor) { - part_number = (cpuid >> 13) & 0x7; - switch (part_number) { - case 1: - pmu = xscale1pmu_init(); - break; - case 2: - pmu = xscale2pmu_init(); - break; - } - } - - put_cpu(); - return pmu; -} - -static int __devinit cpu_pmu_device_probe(struct platform_device *pdev) -{ - const struct of_device_id *of_id; - struct arm_pmu *(*init_fn)(void); - struct device_node *node = pdev->dev.of_node; - - if (cpu_pmu) { - pr_info("attempt to register multiple PMU devices!"); - return -ENOSPC; - } - - if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) { - init_fn = of_id->data; - cpu_pmu = init_fn(); - } else { - cpu_pmu = probe_current_pmu(); - } - - if (!cpu_pmu) - return -ENODEV; - - cpu_pmu->plat_device = pdev; - cpu_pmu_init(cpu_pmu); - register_cpu_notifier(&cpu_pmu_hotplug_notifier); - armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW); - - return 0; -} - -static struct platform_driver cpu_pmu_driver = { - .driver = { - .name = "arm-pmu", - .pm = &armpmu_dev_pm_ops, - .of_match_table = cpu_pmu_of_device_ids, - }, - .probe = cpu_pmu_device_probe, - .id_table = cpu_pmu_plat_device_ids, -}; - -static int __init register_pmu_driver(void) -{ - return platform_driver_register(&cpu_pmu_driver); -} -device_initcall(register_pmu_driver); diff --git a/trunk/arch/arm/kernel/perf_event_v6.c b/trunk/arch/arm/kernel/perf_event_v6.c index 6ccc07971745..c90fcb2b6967 100644 --- a/trunk/arch/arm/kernel/perf_event_v6.c +++ b/trunk/arch/arm/kernel/perf_event_v6.c @@ -645,7 +645,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc, static int armv6_map_event(struct perf_event *event) { - return armpmu_map_event(event, &armv6_perf_map, + return map_cpu_event(event, &armv6_perf_map, &armv6_perf_cache_map, 0xFF); } @@ -664,7 +664,7 @@ static struct arm_pmu armv6pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__devinit armv6pmu_init(void) +static struct arm_pmu *__init armv6pmu_init(void) { return &armv6pmu; } @@ -679,7 +679,7 @@ static struct arm_pmu *__devinit armv6pmu_init(void) static int armv6mpcore_map_event(struct perf_event *event) { - return armpmu_map_event(event, &armv6mpcore_perf_map, + return map_cpu_event(event, &armv6mpcore_perf_map, &armv6mpcore_perf_cache_map, 0xFF); } @@ -698,17 +698,17 @@ static struct arm_pmu armv6mpcore_pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__devinit armv6mpcore_pmu_init(void) +static struct arm_pmu *__init armv6mpcore_pmu_init(void) { return &armv6mpcore_pmu; } #else -static struct arm_pmu *__devinit armv6pmu_init(void) +static struct arm_pmu *__init armv6pmu_init(void) { return NULL; } -static struct arm_pmu *__devinit armv6mpcore_pmu_init(void) +static struct arm_pmu *__init armv6mpcore_pmu_init(void) { return NULL; } diff --git a/trunk/arch/arm/kernel/perf_event_v7.c b/trunk/arch/arm/kernel/perf_event_v7.c index bd4b090ebcfd..f04070bd2183 100644 --- a/trunk/arch/arm/kernel/perf_event_v7.c +++ b/trunk/arch/arm/kernel/perf_event_v7.c @@ -1204,31 +1204,31 @@ static void armv7pmu_reset(void *info) static int armv7_a8_map_event(struct perf_event *event) { - return armpmu_map_event(event, &armv7_a8_perf_map, + return map_cpu_event(event, &armv7_a8_perf_map, &armv7_a8_perf_cache_map, 0xFF); } static int armv7_a9_map_event(struct perf_event *event) { - return armpmu_map_event(event, &armv7_a9_perf_map, + return map_cpu_event(event, &armv7_a9_perf_map, &armv7_a9_perf_cache_map, 0xFF); } static int armv7_a5_map_event(struct perf_event *event) { - return armpmu_map_event(event, &armv7_a5_perf_map, + return map_cpu_event(event, &armv7_a5_perf_map, &armv7_a5_perf_cache_map, 0xFF); } static int armv7_a15_map_event(struct perf_event *event) { - return armpmu_map_event(event, &armv7_a15_perf_map, + return map_cpu_event(event, &armv7_a15_perf_map, &armv7_a15_perf_cache_map, 0xFF); } static int armv7_a7_map_event(struct perf_event *event) { - return armpmu_map_event(event, &armv7_a7_perf_map, + return map_cpu_event(event, &armv7_a7_perf_map, &armv7_a7_perf_cache_map, 0xFF); } @@ -1245,7 +1245,7 @@ static struct arm_pmu armv7pmu = { .max_period = (1LLU << 32) - 1, }; -static u32 __devinit armv7_read_num_pmnc_events(void) +static u32 __init armv7_read_num_pmnc_events(void) { u32 nb_cnt; @@ -1256,7 +1256,7 @@ static u32 __devinit armv7_read_num_pmnc_events(void) return nb_cnt + 1; } -static struct arm_pmu *__devinit armv7_a8_pmu_init(void) +static struct arm_pmu *__init armv7_a8_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A8"; armv7pmu.map_event = armv7_a8_map_event; @@ -1264,7 +1264,7 @@ static struct arm_pmu *__devinit armv7_a8_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__devinit armv7_a9_pmu_init(void) +static struct arm_pmu *__init armv7_a9_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A9"; armv7pmu.map_event = armv7_a9_map_event; @@ -1272,7 +1272,7 @@ static struct arm_pmu *__devinit armv7_a9_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__devinit armv7_a5_pmu_init(void) +static struct arm_pmu *__init armv7_a5_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A5"; armv7pmu.map_event = armv7_a5_map_event; @@ -1280,7 +1280,7 @@ static struct arm_pmu *__devinit armv7_a5_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__devinit armv7_a15_pmu_init(void) +static struct arm_pmu *__init armv7_a15_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A15"; armv7pmu.map_event = armv7_a15_map_event; @@ -1289,7 +1289,7 @@ static struct arm_pmu *__devinit armv7_a15_pmu_init(void) return &armv7pmu; } -static struct arm_pmu *__devinit armv7_a7_pmu_init(void) +static struct arm_pmu *__init armv7_a7_pmu_init(void) { armv7pmu.name = "ARMv7 Cortex-A7"; armv7pmu.map_event = armv7_a7_map_event; @@ -1298,27 +1298,27 @@ static struct arm_pmu *__devinit armv7_a7_pmu_init(void) return &armv7pmu; } #else -static struct arm_pmu *__devinit armv7_a8_pmu_init(void) +static struct arm_pmu *__init armv7_a8_pmu_init(void) { return NULL; } -static struct arm_pmu *__devinit armv7_a9_pmu_init(void) +static struct arm_pmu *__init armv7_a9_pmu_init(void) { return NULL; } -static struct arm_pmu *__devinit armv7_a5_pmu_init(void) +static struct arm_pmu *__init armv7_a5_pmu_init(void) { return NULL; } -static struct arm_pmu *__devinit armv7_a15_pmu_init(void) +static struct arm_pmu *__init armv7_a15_pmu_init(void) { return NULL; } -static struct arm_pmu *__devinit armv7_a7_pmu_init(void) +static struct arm_pmu *__init armv7_a7_pmu_init(void) { return NULL; } diff --git a/trunk/arch/arm/kernel/perf_event_xscale.c b/trunk/arch/arm/kernel/perf_event_xscale.c index 426e19f380a2..f759fe0bab63 100644 --- a/trunk/arch/arm/kernel/perf_event_xscale.c +++ b/trunk/arch/arm/kernel/perf_event_xscale.c @@ -430,7 +430,7 @@ xscale1pmu_write_counter(int counter, u32 val) static int xscale_map_event(struct perf_event *event) { - return armpmu_map_event(event, &xscale_perf_map, + return map_cpu_event(event, &xscale_perf_map, &xscale_perf_cache_map, 0xFF); } @@ -449,7 +449,7 @@ static struct arm_pmu xscale1pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__devinit xscale1pmu_init(void) +static struct arm_pmu *__init xscale1pmu_init(void) { return &xscale1pmu; } @@ -816,17 +816,17 @@ static struct arm_pmu xscale2pmu = { .max_period = (1LLU << 32) - 1, }; -static struct arm_pmu *__devinit xscale2pmu_init(void) +static struct arm_pmu *__init xscale2pmu_init(void) { return &xscale2pmu; } #else -static struct arm_pmu *__devinit xscale1pmu_init(void) +static struct arm_pmu *__init xscale1pmu_init(void) { return NULL; } -static struct arm_pmu *__devinit xscale2pmu_init(void) +static struct arm_pmu *__init xscale2pmu_init(void) { return NULL; } diff --git a/trunk/arch/arm/kernel/pmu.c b/trunk/arch/arm/kernel/pmu.c new file mode 100644 index 000000000000..2334bf8a650a --- /dev/null +++ b/trunk/arch/arm/kernel/pmu.c @@ -0,0 +1,36 @@ +/* + * linux/arch/arm/kernel/pmu.c + * + * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles + * Copyright (C) 2010 ARM Ltd, Will Deacon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include +#include + +#include + +/* + * PMU locking to ensure mutual exclusion between different subsystems. + */ +static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)]; + +int +reserve_pmu(enum arm_pmu_type type) +{ + return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0; +} +EXPORT_SYMBOL_GPL(reserve_pmu); + +void +release_pmu(enum arm_pmu_type type) +{ + clear_bit_unlock(type, pmu_lock); +} +EXPORT_SYMBOL_GPL(release_pmu); diff --git a/trunk/arch/arm/kernel/sched_clock.c b/trunk/arch/arm/kernel/sched_clock.c index f4515393248d..27d186abbc06 100644 --- a/trunk/arch/arm/kernel/sched_clock.c +++ b/trunk/arch/arm/kernel/sched_clock.c @@ -21,8 +21,6 @@ struct clock_data { u32 epoch_cyc_copy; u32 mult; u32 shift; - bool suspended; - bool needs_suspend; }; static void sched_clock_poll(unsigned long wrap_ticks); @@ -51,9 +49,6 @@ static unsigned long long cyc_to_sched_clock(u32 cyc, u32 mask) u64 epoch_ns; u32 epoch_cyc; - if (cd.suspended) - return cd.epoch_ns; - /* * Load the epoch_cyc and epoch_ns atomically. We do this by * ensuring that we always write epoch_cyc, epoch_ns and @@ -103,13 +98,6 @@ static void sched_clock_poll(unsigned long wrap_ticks) update_sched_clock(); } -void __init setup_sched_clock_needs_suspend(u32 (*read)(void), int bits, - unsigned long rate) -{ - setup_sched_clock(read, bits, rate); - cd.needs_suspend = true; -} - void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate) { unsigned long r, w; @@ -181,23 +169,11 @@ void __init sched_clock_postinit(void) static int sched_clock_suspend(void) { sched_clock_poll(sched_clock_timer.data); - if (cd.needs_suspend) - cd.suspended = true; return 0; } -static void sched_clock_resume(void) -{ - if (cd.needs_suspend) { - cd.epoch_cyc = read_sched_clock(); - cd.epoch_cyc_copy = cd.epoch_cyc; - cd.suspended = false; - } -} - static struct syscore_ops sched_clock_ops = { .suspend = sched_clock_suspend, - .resume = sched_clock_resume, }; static int __init sched_clock_syscore_init(void) diff --git a/trunk/arch/arm/kernel/smp_twd.c b/trunk/arch/arm/kernel/smp_twd.c index e1f906989bb8..fef42b21cecb 100644 --- a/trunk/arch/arm/kernel/smp_twd.c +++ b/trunk/arch/arm/kernel/smp_twd.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -95,52 +96,7 @@ static void twd_timer_stop(struct clock_event_device *clk) disable_percpu_irq(clk->irq); } -#ifdef CONFIG_COMMON_CLK - -/* - * Updates clockevent frequency when the cpu frequency changes. - * Called on the cpu that is changing frequency with interrupts disabled. - */ -static void twd_update_frequency(void *new_rate) -{ - twd_timer_rate = *((unsigned long *) new_rate); - - clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate); -} - -static int twd_rate_change(struct notifier_block *nb, - unsigned long flags, void *data) -{ - struct clk_notifier_data *cnd = data; - - /* - * The twd clock events must be reprogrammed to account for the new - * frequency. The timer is local to a cpu, so cross-call to the - * changing cpu. - */ - if (flags == POST_RATE_CHANGE) - smp_call_function(twd_update_frequency, - (void *)&cnd->new_rate, 1); - - return NOTIFY_OK; -} - -static struct notifier_block twd_clk_nb = { - .notifier_call = twd_rate_change, -}; - -static int twd_clk_init(void) -{ - if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) - return clk_notifier_register(twd_clk, &twd_clk_nb); - - return 0; -} -core_initcall(twd_clk_init); - -#elif defined (CONFIG_CPU_FREQ) - -#include +#ifdef CONFIG_CPU_FREQ /* * Updates clockevent frequency when the cpu frequency changes. diff --git a/trunk/arch/arm/kernel/topology.c b/trunk/arch/arm/kernel/topology.c index 26c12c6440fc..198b08456e90 100644 --- a/trunk/arch/arm/kernel/topology.c +++ b/trunk/arch/arm/kernel/topology.c @@ -321,7 +321,7 @@ void store_cpu_topology(unsigned int cpuid) * init_cpu_topology is called at boot when only one cpu is running * which prevent simultaneous write access to cpu_topology array */ -void __init init_cpu_topology(void) +void init_cpu_topology(void) { unsigned int cpu; diff --git a/trunk/arch/arm/kernel/traps.c b/trunk/arch/arm/kernel/traps.c index b0179b89a04c..f7945218b8c6 100644 --- a/trunk/arch/arm/kernel/traps.c +++ b/trunk/arch/arm/kernel/traps.c @@ -420,23 +420,20 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs) #endif instr = *(u32 *) pc; } else if (thumb_mode(regs)) { - if (get_user(instr, (u16 __user *)pc)) - goto die_sig; + get_user(instr, (u16 __user *)pc); if (is_wide_instruction(instr)) { unsigned int instr2; - if (get_user(instr2, (u16 __user *)pc+1)) - goto die_sig; + get_user(instr2, (u16 __user *)pc+1); instr <<= 16; instr |= instr2; } - } else if (get_user(instr, (u32 __user *)pc)) { - goto die_sig; + } else { + get_user(instr, (u32 __user *)pc); } if (call_undef_hook(regs, instr) == 0) return; -die_sig: #ifdef CONFIG_DEBUG_USER if (user_debug & UDBG_UNDEFINED) { printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n", diff --git a/trunk/arch/arm/lib/Makefile b/trunk/arch/arm/lib/Makefile index af72969820b4..2473fd1fd51c 100644 --- a/trunk/arch/arm/lib/Makefile +++ b/trunk/arch/arm/lib/Makefile @@ -16,30 +16,13 @@ lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ call_with_stack.o mmu-y := clear_user.o copy_page.o getuser.o putuser.o - -# the code in uaccess.S is not preemption safe and -# probably faster on ARMv3 only -ifeq ($(CONFIG_PREEMPT),y) - mmu-y += copy_from_user.o copy_to_user.o -else -ifneq ($(CONFIG_CPU_32v3),y) - mmu-y += copy_from_user.o copy_to_user.o -else - mmu-y += uaccess.o -endif -endif +mmu-y += copy_from_user.o copy_to_user.o # using lib_ here won't override already available weak symbols obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o -lib-$(CONFIG_MMU) += $(mmu-y) - -ifeq ($(CONFIG_CPU_32v3),y) - lib-y += io-readsw-armv3.o io-writesw-armv3.o -else - lib-y += io-readsw-armv4.o io-writesw-armv4.o -endif - +lib-$(CONFIG_MMU) += $(mmu-y) +lib-y += io-readsw-armv4.o io-writesw-armv4.o lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o lib-$(CONFIG_ARCH_SHARK) += io-shark.o diff --git a/trunk/arch/arm/lib/delay.c b/trunk/arch/arm/lib/delay.c index 395d5fbb8fa2..d6dacc69254e 100644 --- a/trunk/arch/arm/lib/delay.c +++ b/trunk/arch/arm/lib/delay.c @@ -59,7 +59,6 @@ void __init init_current_timer_delay(unsigned long freq) { pr_info("Switching to timer-based delay loop\n"); lpj_fine = freq / HZ; - loops_per_jiffy = lpj_fine; arm_delay_ops.delay = __timer_delay; arm_delay_ops.const_udelay = __timer_const_udelay; arm_delay_ops.udelay = __timer_udelay; diff --git a/trunk/arch/arm/lib/getuser.S b/trunk/arch/arm/lib/getuser.S index 9b06bb41fca6..11093a7c3e32 100644 --- a/trunk/arch/arm/lib/getuser.S +++ b/trunk/arch/arm/lib/getuser.S @@ -16,9 +16,8 @@ * __get_user_X * * Inputs: r0 contains the address - * r1 contains the address limit, which must be preserved * Outputs: r0 is the error code - * r2 contains the zero-extended value + * r2, r3 contains the zero-extended value * lr corrupted * * No other registers must be altered. (see @@ -28,39 +27,33 @@ * Note also that it is intended that __get_user_bad is not global. */ #include -#include #include #include ENTRY(__get_user_1) - check_uaccess r0, 1, r1, r2, __get_user_bad 1: TUSER(ldrb) r2, [r0] mov r0, #0 mov pc, lr ENDPROC(__get_user_1) ENTRY(__get_user_2) - check_uaccess r0, 2, r1, r2, __get_user_bad -#ifdef CONFIG_CPU_USE_DOMAINS -rb .req ip -2: ldrbt r2, [r0], #1 -3: ldrbt rb, [r0], #0 +#ifdef CONFIG_THUMB2_KERNEL +2: TUSER(ldrb) r2, [r0] +3: TUSER(ldrb) r3, [r0, #1] #else -rb .req r0 -2: ldrb r2, [r0] -3: ldrb rb, [r0, #1] +2: TUSER(ldrb) r2, [r0], #1 +3: TUSER(ldrb) r3, [r0] #endif #ifndef __ARMEB__ - orr r2, r2, rb, lsl #8 + orr r2, r2, r3, lsl #8 #else - orr r2, rb, r2, lsl #8 + orr r2, r3, r2, lsl #8 #endif mov r0, #0 mov pc, lr ENDPROC(__get_user_2) ENTRY(__get_user_4) - check_uaccess r0, 4, r1, r2, __get_user_bad 4: TUSER(ldr) r2, [r0] mov r0, #0 mov pc, lr diff --git a/trunk/arch/arm/lib/io-readsw-armv3.S b/trunk/arch/arm/lib/io-readsw-armv3.S deleted file mode 100644 index 88487c8c4f23..000000000000 --- a/trunk/arch/arm/lib/io-readsw-armv3.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * linux/arch/arm/lib/io-readsw-armv3.S - * - * Copyright (C) 1995-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - -.Linsw_bad_alignment: - adr r0, .Linsw_bad_align_msg - mov r2, lr - b panic -.Linsw_bad_align_msg: - .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n" - .align - -.Linsw_align: tst r1, #1 - bne .Linsw_bad_alignment - - ldr r3, [r0] - strb r3, [r1], #1 - mov r3, r3, lsr #8 - strb r3, [r1], #1 - - subs r2, r2, #1 - moveq pc, lr - -ENTRY(__raw_readsw) - teq r2, #0 @ do we have to check for the zero len? - moveq pc, lr - tst r1, #3 - bne .Linsw_align - -.Linsw_aligned: mov ip, #0xff - orr ip, ip, ip, lsl #8 - stmfd sp!, {r4, r5, r6, lr} - - subs r2, r2, #8 - bmi .Lno_insw_8 - -.Linsw_8_lp: ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - ldr r4, [r0] - and r4, r4, ip - ldr r5, [r0] - orr r4, r4, r5, lsl #16 - - ldr r5, [r0] - and r5, r5, ip - ldr r6, [r0] - orr r5, r5, r6, lsl #16 - - ldr r6, [r0] - and r6, r6, ip - ldr lr, [r0] - orr r6, r6, lr, lsl #16 - - stmia r1!, {r3 - r6} - - subs r2, r2, #8 - bpl .Linsw_8_lp - - tst r2, #7 - ldmeqfd sp!, {r4, r5, r6, pc} - -.Lno_insw_8: tst r2, #4 - beq .Lno_insw_4 - - ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - ldr r4, [r0] - and r4, r4, ip - ldr r5, [r0] - orr r4, r4, r5, lsl #16 - - stmia r1!, {r3, r4} - -.Lno_insw_4: tst r2, #2 - beq .Lno_insw_2 - - ldr r3, [r0] - and r3, r3, ip - ldr r4, [r0] - orr r3, r3, r4, lsl #16 - - str r3, [r1], #4 - -.Lno_insw_2: tst r2, #1 - ldrne r3, [r0] - strneb r3, [r1], #1 - movne r3, r3, lsr #8 - strneb r3, [r1] - - ldmfd sp!, {r4, r5, r6, pc} - - diff --git a/trunk/arch/arm/lib/io-writesw-armv3.S b/trunk/arch/arm/lib/io-writesw-armv3.S deleted file mode 100644 index 49b800419e32..000000000000 --- a/trunk/arch/arm/lib/io-writesw-armv3.S +++ /dev/null @@ -1,126 +0,0 @@ -/* - * linux/arch/arm/lib/io-writesw-armv3.S - * - * Copyright (C) 1995-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include - -.Loutsw_bad_alignment: - adr r0, .Loutsw_bad_align_msg - mov r2, lr - b panic -.Loutsw_bad_align_msg: - .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n" - .align - -.Loutsw_align: tst r1, #1 - bne .Loutsw_bad_alignment - - add r1, r1, #2 - - ldr r3, [r1, #-4] - mov r3, r3, lsr #16 - orr r3, r3, r3, lsl #16 - str r3, [r0] - subs r2, r2, #1 - moveq pc, lr - -ENTRY(__raw_writesw) - teq r2, #0 @ do we have to check for the zero len? - moveq pc, lr - tst r1, #3 - bne .Loutsw_align - - stmfd sp!, {r4, r5, r6, lr} - - subs r2, r2, #8 - bmi .Lno_outsw_8 - -.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6} - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r4, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r4, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r5, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r5, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r6, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r6, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - subs r2, r2, #8 - bpl .Loutsw_8_lp - - tst r2, #7 - ldmeqfd sp!, {r4, r5, r6, pc} - -.Lno_outsw_8: tst r2, #4 - beq .Lno_outsw_4 - - ldmia r1!, {r3, r4} - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - - mov ip, r4, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r4, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - -.Lno_outsw_4: tst r2, #2 - beq .Lno_outsw_2 - - ldr r3, [r1], #4 - - mov ip, r3, lsl #16 - orr ip, ip, ip, lsr #16 - str ip, [r0] - - mov ip, r3, lsr #16 - orr ip, ip, ip, lsl #16 - str ip, [r0] - -.Lno_outsw_2: tst r2, #1 - - ldrne r3, [r1] - - movne ip, r3, lsl #16 - orrne ip, ip, ip, lsr #16 - strne ip, [r0] - - ldmfd sp!, {r4, r5, r6, pc} diff --git a/trunk/arch/arm/lib/putuser.S b/trunk/arch/arm/lib/putuser.S index 3d73dcb959b0..7db25990c589 100644 --- a/trunk/arch/arm/lib/putuser.S +++ b/trunk/arch/arm/lib/putuser.S @@ -16,7 +16,6 @@ * __put_user_X * * Inputs: r0 contains the address - * r1 contains the address limit, which must be preserved * r2, r3 contains the value * Outputs: r0 is the error code * lr corrupted @@ -28,19 +27,16 @@ * Note also that it is intended that __put_user_bad is not global. */ #include -#include #include #include ENTRY(__put_user_1) - check_uaccess r0, 1, r1, ip, __put_user_bad 1: TUSER(strb) r2, [r0] mov r0, #0 mov pc, lr ENDPROC(__put_user_1) ENTRY(__put_user_2) - check_uaccess r0, 2, r1, ip, __put_user_bad mov ip, r2, lsr #8 #ifdef CONFIG_THUMB2_KERNEL #ifndef __ARMEB__ @@ -64,14 +60,12 @@ ENTRY(__put_user_2) ENDPROC(__put_user_2) ENTRY(__put_user_4) - check_uaccess r0, 4, r1, ip, __put_user_bad 4: TUSER(str) r2, [r0] mov r0, #0 mov pc, lr ENDPROC(__put_user_4) ENTRY(__put_user_8) - check_uaccess r0, 8, r1, ip, __put_user_bad #ifdef CONFIG_THUMB2_KERNEL 5: TUSER(str) r2, [r0] 6: TUSER(str) r3, [r0, #4] diff --git a/trunk/arch/arm/lib/uaccess.S b/trunk/arch/arm/lib/uaccess.S deleted file mode 100644 index 5c908b1cb8ed..000000000000 --- a/trunk/arch/arm/lib/uaccess.S +++ /dev/null @@ -1,564 +0,0 @@ -/* - * linux/arch/arm/lib/uaccess.S - * - * Copyright (C) 1995, 1996,1997,1998 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Routines to block copy data to/from user memory - * These are highly optimised both for the 4k page size - * and for various alignments. - */ -#include -#include -#include -#include - - .text - -#define PAGE_SHIFT 12 - -/* Prototype: int __copy_to_user(void *to, const char *from, size_t n) - * Purpose : copy a block to user memory from kernel memory - * Params : to - user memory - * : from - kernel memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ - -.Lc2u_dest_not_aligned: - rsb ip, ip, #4 - cmp ip, #2 - ldrb r3, [r1], #1 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #1 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - sub r2, r2, ip - b .Lc2u_dest_aligned - -ENTRY(__copy_to_user) - stmfd sp!, {r2, r4 - r7, lr} - cmp r2, #4 - blt .Lc2u_not_enough - ands ip, r0, #3 - bne .Lc2u_dest_not_aligned -.Lc2u_dest_aligned: - - ands ip, r1, #3 - bne .Lc2u_src_not_aligned -/* - * Seeing as there has to be at least 8 bytes to copy, we can - * copy one word, and force a user-mode page fault... - */ - -.Lc2u_0fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_0nowords - ldr r3, [r1], #4 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_0fupi -/* - * ip = max no. of bytes to copy before needing another "strt" insn - */ - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #32 - blt .Lc2u_0rem8lp - -.Lc2u_0cpy8lp: ldmia r1!, {r3 - r6} - stmia r0!, {r3 - r6} @ Shouldnt fault - ldmia r1!, {r3 - r6} - subs ip, ip, #32 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_0cpy8lp - -.Lc2u_0rem8lp: cmn ip, #16 - ldmgeia r1!, {r3 - r6} - stmgeia r0!, {r3 - r6} @ Shouldnt fault - tst ip, #8 - ldmneia r1!, {r3 - r4} - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - ldrne r3, [r1], #4 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_0fupi -.Lc2u_0nowords: teq ip, #0 - beq .Lc2u_finished -.Lc2u_nowords: cmp ip, #2 - ldrb r3, [r1], #1 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #1 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_not_enough: - movs ip, r2 - bne .Lc2u_nowords -.Lc2u_finished: mov r0, #0 - ldmfd sp!, {r2, r4 - r7, pc} - -.Lc2u_src_not_aligned: - bic r1, r1, #3 - ldr r7, [r1], #4 - cmp ip, #2 - bgt .Lc2u_3fupi - beq .Lc2u_2fupi -.Lc2u_1fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_1nowords - mov r3, r7, pull #8 - ldr r7, [r1], #4 - orr r3, r3, r7, push #24 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_1fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_1rem8lp - -.Lc2u_1cpy8lp: mov r3, r7, pull #8 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_1cpy8lp - -.Lc2u_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #8 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #24 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_1fupi -.Lc2u_1nowords: mov r3, r7, get_byte_1 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - movge r3, r7, get_byte_2 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - movgt r3, r7, get_byte_3 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_2fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_2nowords - mov r3, r7, pull #16 - ldr r7, [r1], #4 - orr r3, r3, r7, push #16 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_2fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_2rem8lp - -.Lc2u_2cpy8lp: mov r3, r7, pull #16 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_2cpy8lp - -.Lc2u_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #16 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #16 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_2fupi -.Lc2u_2nowords: mov r3, r7, get_byte_2 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - movge r3, r7, get_byte_3 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #0 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished - -.Lc2u_3fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lc2u_3nowords - mov r3, r7, pull #24 - ldr r7, [r1], #4 - orr r3, r3, r7, push #8 -USER( TUSER( str) r3, [r0], #4) @ May fault - mov ip, r0, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lc2u_3fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lc2u_3rem8lp - -.Lc2u_3cpy8lp: mov r3, r7, pull #24 - ldmia r1!, {r4 - r7} - subs ip, ip, #16 - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 - stmia r0!, {r3 - r6} @ Shouldnt fault - bpl .Lc2u_3cpy8lp - -.Lc2u_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 - ldmneia r1!, {r4, r7} - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 - stmneia r0!, {r3 - r4} @ Shouldnt fault - tst ip, #4 - movne r3, r7, pull #24 - ldrne r7, [r1], #4 - orrne r3, r3, r7, push #8 - TUSER( strne) r3, [r0], #4 @ Shouldnt fault - ands ip, ip, #3 - beq .Lc2u_3fupi -.Lc2u_3nowords: mov r3, r7, get_byte_3 - teq ip, #0 - beq .Lc2u_finished - cmp ip, #2 -USER( TUSER( strb) r3, [r0], #1) @ May fault - ldrgeb r3, [r1], #1 -USER( TUSER( strgeb) r3, [r0], #1) @ May fault - ldrgtb r3, [r1], #0 -USER( TUSER( strgtb) r3, [r0], #1) @ May fault - b .Lc2u_finished -ENDPROC(__copy_to_user) - - .pushsection .fixup,"ax" - .align 0 -9001: ldmfd sp!, {r0, r4 - r7, pc} - .popsection - -/* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n); - * Purpose : copy a block from user memory to kernel memory - * Params : to - kernel memory - * : from - user memory - * : n - number of bytes to copy - * Returns : Number of bytes NOT copied. - */ -.Lcfu_dest_not_aligned: - rsb ip, ip, #4 - cmp ip, #2 -USER( TUSER( ldrb) r3, [r1], #1) @ May fault - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - sub r2, r2, ip - b .Lcfu_dest_aligned - -ENTRY(__copy_from_user) - stmfd sp!, {r0, r2, r4 - r7, lr} - cmp r2, #4 - blt .Lcfu_not_enough - ands ip, r0, #3 - bne .Lcfu_dest_not_aligned -.Lcfu_dest_aligned: - ands ip, r1, #3 - bne .Lcfu_src_not_aligned - -/* - * Seeing as there has to be at least 8 bytes to copy, we can - * copy one word, and force a user-mode page fault... - */ - -.Lcfu_0fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_0nowords -USER( TUSER( ldr) r3, [r1], #4) - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_0fupi -/* - * ip = max no. of bytes to copy before needing another "strt" insn - */ - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #32 - blt .Lcfu_0rem8lp - -.Lcfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault - stmia r0!, {r3 - r6} - ldmia r1!, {r3 - r6} @ Shouldnt fault - subs ip, ip, #32 - stmia r0!, {r3 - r6} - bpl .Lcfu_0cpy8lp - -.Lcfu_0rem8lp: cmn ip, #16 - ldmgeia r1!, {r3 - r6} @ Shouldnt fault - stmgeia r0!, {r3 - r6} - tst ip, #8 - ldmneia r1!, {r3 - r4} @ Shouldnt fault - stmneia r0!, {r3 - r4} - tst ip, #4 - TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_0fupi -.Lcfu_0nowords: teq ip, #0 - beq .Lcfu_finished -.Lcfu_nowords: cmp ip, #2 -USER( TUSER( ldrb) r3, [r1], #1) @ May fault - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_not_enough: - movs ip, r2 - bne .Lcfu_nowords -.Lcfu_finished: mov r0, #0 - add sp, sp, #8 - ldmfd sp!, {r4 - r7, pc} - -.Lcfu_src_not_aligned: - bic r1, r1, #3 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - cmp ip, #2 - bgt .Lcfu_3fupi - beq .Lcfu_2fupi -.Lcfu_1fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_1nowords - mov r3, r7, pull #8 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #24 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_1fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_1rem8lp - -.Lcfu_1cpy8lp: mov r3, r7, pull #8 - ldmia r1!, {r4 - r7} @ Shouldnt fault - subs ip, ip, #16 - orr r3, r3, r4, push #24 - mov r4, r4, pull #8 - orr r4, r4, r5, push #24 - mov r5, r5, pull #8 - orr r5, r5, r6, push #24 - mov r6, r6, pull #8 - orr r6, r6, r7, push #24 - stmia r0!, {r3 - r6} - bpl .Lcfu_1cpy8lp - -.Lcfu_1rem8lp: tst ip, #8 - movne r3, r7, pull #8 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #24 - movne r4, r4, pull #8 - orrne r4, r4, r7, push #24 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #8 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #24 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_1fupi -.Lcfu_1nowords: mov r3, r7, get_byte_1 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 - movge r3, r7, get_byte_2 - strgeb r3, [r0], #1 - movgt r3, r7, get_byte_3 - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_2fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_2nowords - mov r3, r7, pull #16 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #16 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_2fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_2rem8lp - - -.Lcfu_2cpy8lp: mov r3, r7, pull #16 - ldmia r1!, {r4 - r7} @ Shouldnt fault - subs ip, ip, #16 - orr r3, r3, r4, push #16 - mov r4, r4, pull #16 - orr r4, r4, r5, push #16 - mov r5, r5, pull #16 - orr r5, r5, r6, push #16 - mov r6, r6, pull #16 - orr r6, r6, r7, push #16 - stmia r0!, {r3 - r6} - bpl .Lcfu_2cpy8lp - -.Lcfu_2rem8lp: tst ip, #8 - movne r3, r7, pull #16 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #16 - movne r4, r4, pull #16 - orrne r4, r4, r7, push #16 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #16 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #16 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_2fupi -.Lcfu_2nowords: mov r3, r7, get_byte_2 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 - movge r3, r7, get_byte_3 - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished - -.Lcfu_3fupi: subs r2, r2, #4 - addmi ip, r2, #4 - bmi .Lcfu_3nowords - mov r3, r7, pull #24 -USER( TUSER( ldr) r7, [r1], #4) @ May fault - orr r3, r3, r7, push #8 - str r3, [r0], #4 - mov ip, r1, lsl #32 - PAGE_SHIFT - rsb ip, ip, #0 - movs ip, ip, lsr #32 - PAGE_SHIFT - beq .Lcfu_3fupi - cmp r2, ip - movlt ip, r2 - sub r2, r2, ip - subs ip, ip, #16 - blt .Lcfu_3rem8lp - -.Lcfu_3cpy8lp: mov r3, r7, pull #24 - ldmia r1!, {r4 - r7} @ Shouldnt fault - orr r3, r3, r4, push #8 - mov r4, r4, pull #24 - orr r4, r4, r5, push #8 - mov r5, r5, pull #24 - orr r5, r5, r6, push #8 - mov r6, r6, pull #24 - orr r6, r6, r7, push #8 - stmia r0!, {r3 - r6} - subs ip, ip, #16 - bpl .Lcfu_3cpy8lp - -.Lcfu_3rem8lp: tst ip, #8 - movne r3, r7, pull #24 - ldmneia r1!, {r4, r7} @ Shouldnt fault - orrne r3, r3, r4, push #8 - movne r4, r4, pull #24 - orrne r4, r4, r7, push #8 - stmneia r0!, {r3 - r4} - tst ip, #4 - movne r3, r7, pull #24 -USER( TUSER( ldrne) r7, [r1], #4) @ May fault - orrne r3, r3, r7, push #8 - strne r3, [r0], #4 - ands ip, ip, #3 - beq .Lcfu_3fupi -.Lcfu_3nowords: mov r3, r7, get_byte_3 - teq ip, #0 - beq .Lcfu_finished - cmp ip, #2 - strb r3, [r0], #1 -USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault - strgeb r3, [r0], #1 -USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault - strgtb r3, [r0], #1 - b .Lcfu_finished -ENDPROC(__copy_from_user) - - .pushsection .fixup,"ax" - .align 0 - /* - * We took an exception. r0 contains a pointer to - * the byte not copied. - */ -9001: ldr r2, [sp], #4 @ void *to - sub r2, r0, r2 @ bytes copied - ldr r1, [sp], #4 @ unsigned long count - subs r4, r1, r2 @ bytes left to copy - movne r1, r4 - blne __memzero - mov r0, r4 - ldmfd sp!, {r4 - r7, pc} - .popsection - diff --git a/trunk/arch/arm/mach-at91/at91rm9200_time.c b/trunk/arch/arm/mach-at91/at91rm9200_time.c index aaa443b48c91..104ca40d8d18 100644 --- a/trunk/arch/arm/mach-at91/at91rm9200_time.c +++ b/trunk/arch/arm/mach-at91/at91rm9200_time.c @@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void) at91_st_read(AT91_ST_SR); /* Make IRQs happen for the system timer */ - setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq); + setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used * directly for the clocksource and all clockevents, after adjusting diff --git a/trunk/arch/arm/mach-at91/at91sam9260_devices.c b/trunk/arch/arm/mach-at91/at91sam9260_devices.c index bce572a530ef..7b9c2ba396ed 100644 --- a/trunk/arch/arm/mach-at91/at91sam9260_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9260_devices.c @@ -726,8 +726,6 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, }, }; @@ -746,12 +744,10 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9260_rtt_device.num_resources = 3; + at91sam9260_rtt_device.num_resources = 2; rtt_resources[1].start = AT91SAM9260_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; - rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; - rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/trunk/arch/arm/mach-at91/at91sam9261_devices.c b/trunk/arch/arm/mach-at91/at91sam9261_devices.c index bc2590d712d0..8df5c1bdff92 100644 --- a/trunk/arch/arm/mach-at91/at91sam9261_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9261_devices.c @@ -609,8 +609,6 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, } }; @@ -628,12 +626,10 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9261_rtt_device.num_resources = 3; + at91sam9261_rtt_device.num_resources = 2; rtt_resources[1].start = AT91SAM9261_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; - rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; - rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/trunk/arch/arm/mach-at91/at91sam9263_devices.c b/trunk/arch/arm/mach-at91/at91sam9263_devices.c index 9b6ca734f1a9..eb6bbf86fb9f 100644 --- a/trunk/arch/arm/mach-at91/at91sam9263_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9263_devices.c @@ -990,8 +990,6 @@ static struct resource rtt0_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, } }; @@ -1008,8 +1006,6 @@ static struct resource rtt1_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, } }; @@ -1031,14 +1027,14 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed only for the chosen RTT: * GPBR will serve as the storage for RTC time offset */ - at91sam9263_rtt0_device.num_resources = 3; + at91sam9263_rtt0_device.num_resources = 2; at91sam9263_rtt1_device.num_resources = 1; pdev = &at91sam9263_rtt0_device; r = rtt0_resources; break; case 1: at91sam9263_rtt0_device.num_resources = 1; - at91sam9263_rtt1_device.num_resources = 3; + at91sam9263_rtt1_device.num_resources = 2; pdev = &at91sam9263_rtt1_device; r = rtt1_resources; break; @@ -1051,8 +1047,6 @@ static void __init at91_add_device_rtt_rtc(void) pdev->name = "rtc-at91sam9"; r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; r[1].end = r[1].start + 3; - r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; - r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/trunk/arch/arm/mach-at91/at91sam9g45_devices.c b/trunk/arch/arm/mach-at91/at91sam9g45_devices.c index 1b47319ca00b..06073996a382 100644 --- a/trunk/arch/arm/mach-at91/at91sam9g45_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9g45_devices.c @@ -1293,8 +1293,6 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, } }; @@ -1312,12 +1310,10 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9g45_rtt_device.num_resources = 3; + at91sam9g45_rtt_device.num_resources = 2; rtt_resources[1].start = AT91SAM9G45_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; - rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; - rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/trunk/arch/arm/mach-at91/at91sam9rl_devices.c b/trunk/arch/arm/mach-at91/at91sam9rl_devices.c index b3d365dadef5..f09fff932172 100644 --- a/trunk/arch/arm/mach-at91/at91sam9rl_devices.c +++ b/trunk/arch/arm/mach-at91/at91sam9rl_devices.c @@ -688,8 +688,6 @@ static struct resource rtt_resources[] = { .flags = IORESOURCE_MEM, }, { .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ, } }; @@ -707,12 +705,10 @@ static void __init at91_add_device_rtt_rtc(void) * The second resource is needed: * GPBR will serve as the storage for RTC time offset */ - at91sam9rl_rtt_device.num_resources = 3; + at91sam9rl_rtt_device.num_resources = 2; rtt_resources[1].start = AT91SAM9RL_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; rtt_resources[1].end = rtt_resources[1].start + 3; - rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS; - rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS; } #else static void __init at91_add_device_rtt_rtc(void) diff --git a/trunk/arch/arm/mach-at91/at91x40.c b/trunk/arch/arm/mach-at91/at91x40.c index 6bd7300a2bc5..46090e642d8e 100644 --- a/trunk/arch/arm/mach-at91/at91x40.c +++ b/trunk/arch/arm/mach-at91/at91x40.c @@ -47,7 +47,7 @@ static void at91x40_idle(void) * Disable the processor clock. The processor will be automatically * re-enabled by an interrupt or by a reset. */ - __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR)); + __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR); cpu_do_idle(); } diff --git a/trunk/arch/arm/mach-at91/at91x40_time.c b/trunk/arch/arm/mach-at91/at91x40_time.c index ee06d7bcdf76..6ca680a1d5d1 100644 --- a/trunk/arch/arm/mach-at91/at91x40_time.c +++ b/trunk/arch/arm/mach-at91/at91x40_time.c @@ -29,10 +29,10 @@ #include #define at91_tc_read(field) \ - __raw_readl(AT91_IO_P2V(AT91_TC) + field) + __raw_readl(AT91_TC + field) #define at91_tc_write(field, value) \ - __raw_writel(value, AT91_IO_P2V(AT91_TC) + field); + __raw_writel(value, AT91_TC + field); /* * 3 counter/timer units present. diff --git a/trunk/arch/arm/mach-at91/clock.c b/trunk/arch/arm/mach-at91/clock.c index 188c82971ebd..de2ec6b8fea7 100644 --- a/trunk/arch/arm/mach-at91/clock.c +++ b/trunk/arch/arm/mach-at91/clock.c @@ -63,12 +63,6 @@ EXPORT_SYMBOL_GPL(at91_pmc_base); #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) -#define cpu_has_240M_plla() (cpu_is_at91sam9261() \ - || cpu_is_at91sam9263() \ - || cpu_is_at91sam9rl()) - -#define cpu_has_210M_plla() (cpu_is_at91sam9260()) - #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5() \ @@ -712,12 +706,6 @@ static int __init at91_pmc_init(unsigned long main_clock) } else if (cpu_has_800M_plla()) { if (plla.rate_hz > 800000000) pll_overclock = true; - } else if (cpu_has_240M_plla()) { - if (plla.rate_hz > 240000000) - pll_overclock = true; - } else if (cpu_has_210M_plla()) { - if (plla.rate_hz > 210000000) - pll_overclock = true; } else { if (plla.rate_hz > 209000000) pll_overclock = true; diff --git a/trunk/arch/arm/mach-at91/include/mach/hardware.h b/trunk/arch/arm/mach-at91/include/mach/hardware.h index 711a7892d331..09242b67d277 100644 --- a/trunk/arch/arm/mach-at91/include/mach/hardware.h +++ b/trunk/arch/arm/mach-at91/include/mach/hardware.h @@ -67,13 +67,13 @@ * to 0xFEF78000 .. 0xFF000000. (544Kb) */ #define AT91_IO_PHYS_BASE 0xFFF78000 -#define AT91_IO_VIRT_BASE IOMEM(0xFF000000 - AT91_IO_SIZE) +#define AT91_IO_VIRT_BASE (0xFF000000 - AT91_IO_SIZE) #else /* * Identity mapping for the non MMU case. */ #define AT91_IO_PHYS_BASE AT91_BASE_SYS -#define AT91_IO_VIRT_BASE IOMEM(AT91_IO_PHYS_BASE) +#define AT91_IO_VIRT_BASE AT91_IO_PHYS_BASE #endif #define AT91_IO_SIZE (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1) diff --git a/trunk/arch/arm/mach-at91/include/mach/uncompress.h b/trunk/arch/arm/mach-at91/include/mach/uncompress.h index 97ad68a826f8..6f6118d1576a 100644 --- a/trunk/arch/arm/mach-at91/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-at91/include/mach/uncompress.h @@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = { 0, }; -static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) +static inline const u32* decomp_soc_detect(u32 dbgu_base) { u32 cidr, socid; @@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void) int i = 0; const u32* usarts; - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0); + usarts = decomp_soc_detect(AT91_BASE_DBGU0); if (!usarts) - usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1); + usarts = decomp_soc_detect(AT91_BASE_DBGU1); if (!usarts) { at91_uart = NULL; return; diff --git a/trunk/arch/arm/mach-at91/setup.c b/trunk/arch/arm/mach-at91/setup.c index e6f52de1062f..944bffb08991 100644 --- a/trunk/arch/arm/mach-at91/setup.c +++ b/trunk/arch/arm/mach-at91/setup.c @@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) { struct map_desc *desc = &sram_desc[bank]; - desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length; + desc->virtual = AT91_IO_VIRT_BASE - length; if (bank > 0) desc->virtual -= sram_desc[bank - 1].length; @@ -88,7 +88,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length) } static struct map_desc at91_io_desc __initdata = { - .virtual = (unsigned long)AT91_VA_BASE_SYS, + .virtual = AT91_VA_BASE_SYS, .pfn = __phys_to_pfn(AT91_BASE_SYS), .length = SZ_16K, .type = MT_DEVICE, diff --git a/trunk/arch/arm/mach-bcmring/arch.c b/trunk/arch/arm/mach-bcmring/arch.c index c18a5048b6c5..45c97b1ee9b1 100644 --- a/trunk/arch/arm/mach-bcmring/arch.c +++ b/trunk/arch/arm/mach-bcmring/arch.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -37,7 +38,7 @@ #include #include -#include +#include #include "core.h" @@ -115,7 +116,7 @@ static struct resource pmu_resource = { static struct platform_device pmu_device = { .name = "arm-pmu", - .id = -1, + .id = ARM_PMU_DEVICE_CPU, .resource = &pmu_resource, .num_resources = 1, }; diff --git a/trunk/arch/arm/mach-bcmring/core.c b/trunk/arch/arm/mach-bcmring/core.c index 4b50228a6771..adbfb1994582 100644 --- a/trunk/arch/arm/mach-bcmring/core.c +++ b/trunk/arch/arm/mach-bcmring/core.c @@ -43,10 +43,11 @@ #include #include -#include +#include #include "clock.h" +#include #include #include #include diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c index 5050833817b7..96273ff34956 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ @@ -61,21 +61,21 @@ static int chipcHw_divide(int num, int denom) /****************************************************************************/ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ ) { - uint32_t __iomem *pPLLReg = NULL; - uint32_t __iomem *pClockCtrl = NULL; - uint32_t __iomem *pDependentClock = NULL; + volatile uint32_t *pPLLReg = (uint32_t *) 0x0; + volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; + volatile uint32_t *pDependentClock = (uint32_t *) 0x0; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ uint32_t dependentClockType = 0; uint32_t vcoHz = 0; /* Get VCO frequencies */ - if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -86,13 +86,13 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur } else { vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -187,51 +187,51 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur if (pPLLReg) { /* Obtain PLL clock frequency */ - if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (clock == chipcHw_CLOCK_DDR) { /* DDR frequency is configured in PLLDivider register */ - return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); + return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { vcoHz >>= 1; } /* Obtain PLL clock frequency using VCO dividers */ - return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } } else if (pClockCtrl) { /* Obtain divider clock frequency */ uint32_t div; uint32_t freq = 0; - if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Return crystal clock frequency when bypassed */ return chipcHw_XTAL_FREQ_Hz; } else if (pDependentClock) { /* Identify the dependent clock frequency */ switch (dependentClockType) { case PLL_CLOCK: - if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { + if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent PLL clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain PLL clock frequency using VCO dividers */ - div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK; + div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; freq = div ? chipcHw_divide(vcoHz, div) : 0; } break; case NON_PLL_CLOCK: - if (pDependentClock == &pChipcHw->ACLKClock) { + if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { + if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { /* Use crystal clock frequency when dependent divider clock is bypassed */ freq = chipcHw_XTAL_FREQ_Hz; } else { /* Obtain divider clock frequency using XTAL dividers */ - div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); } } @@ -242,7 +242,7 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur freq = chipcHw_XTAL_FREQ_Hz; } - div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK; + div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; return chipcHw_divide(freq, (div ? div : 256)); } return 0; @@ -261,9 +261,9 @@ chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configur chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ uint32_t freq /* [ IN ] Clock frequency in Hz */ ) { - uint32_t __iomem *pPLLReg = NULL; - uint32_t __iomem *pClockCtrl = NULL; - uint32_t __iomem *pDependentClock = NULL; + volatile uint32_t *pPLLReg = (uint32_t *) 0x0; + volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; + volatile uint32_t *pDependentClock = (uint32_t *) 0x0; uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ @@ -272,12 +272,12 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu uint32_t desVcoHz = 0; /* Get VCO frequencies */ - if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { + if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { uint64_t adjustFreq = 0; vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ @@ -289,16 +289,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Desired VCO frequency */ desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); } else { vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); } vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * - ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> + ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); switch (clock) { @@ -307,7 +307,8 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu { REG_LOCAL_IRQ_SAVE; /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ - writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock); + pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) + << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->DDRClock; @@ -328,7 +329,8 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* Configure the VPM:BUS ratio settings */ { REG_LOCAL_IRQ_SAVE; - writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock); + pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) + << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); REG_LOCAL_IRQ_RESTORE; } pPLLReg = &pChipcHw->VPMClock; @@ -426,9 +428,9 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu /* For DDR settings use only the PLL divider clock */ if (pPLLReg == &pChipcHw->DDRClock) { /* Set M1DIV for PLL1, which controls the DDR clock */ - reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); + reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256)); + freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); } else { /* From chip revision number B0, LCD clock is internally divided by 2 */ if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { @@ -439,7 +441,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); /* Calculate expected frequency */ - freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); + freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); } /* Wait for for atleast 200ns as per the protocol to change frequency */ udelay(1); @@ -458,16 +460,16 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (pDependentClock) { switch (dependentClockType) { case PLL_CLOCK: - divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); + divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); break; case NON_PLL_CLOCK: { uint32_t sourceClock = 0; - if (pDependentClock == &pChipcHw->ACLKClock) { + if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); } else { - uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK; + uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); } divider = chipcHw_divide(sourceClock, freq); @@ -481,7 +483,7 @@ chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configu if (divider) { REG_LOCAL_IRQ_SAVE; /* Set the divider to obtain the required frequency */ - writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl); + *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); REG_LOCAL_IRQ_RESTORE; return freq; } @@ -513,26 +515,25 @@ static int vpmPhaseAlignA0(void) int count = 0; for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { - phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; + phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; phaseValue = 0; prevPhaseComp = 0; /* Step 1: Look for falling PH_COMP transition */ /* Read the contents of VPM Clock resgister */ - phaseValue = readl(&pChipcHw->VPMClock); + phaseValue = pChipcHw->VPMClock; do { /* Store previous value of phase comparator */ prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; /* Read the contents of VPM Clock resgister. */ - phaseValue = readl(&pChipcHw->VPMClock); + phaseValue = pChipcHw->VPMClock; if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -556,13 +557,12 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl + 1)); - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); - phaseValue = readl(&pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + phaseValue = pChipcHw->VPMClock; /* Count number of adjustment made */ adjustCount++; } @@ -581,13 +581,12 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); - phaseValue = readl(&pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + phaseValue = pChipcHw->VPMClock; /* Count number of adjustment made */ adjustCount++; } @@ -606,13 +605,12 @@ static int vpmPhaseAlignA0(void) for (count = 0; (count < 5); count++) { phaseControl = (0x3F & (phaseControl - 1)); - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); - phaseValue = readl(&pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; + phaseValue = pChipcHw->VPMClock; /* Count number of adjustment made */ adjustCount++; } @@ -633,14 +631,14 @@ static int vpmPhaseAlignA0(void) /* Store previous value of phase comparator */ prevPhaseComp = phaseValue; /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= + chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; /* Read the contents of VPM Clock resgister. */ - phaseValue = readl(&pChipcHw->VPMClock); + phaseValue = pChipcHw->VPMClock; if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { phaseControl = (0x3F & (phaseControl - 1)); @@ -663,13 +661,13 @@ static int vpmPhaseAlignA0(void) } /* For VPM Phase should be perfectly aligned. */ - phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); + phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); { REG_LOCAL_IRQ_SAVE; - writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock); + pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); /* Load new phase value */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -699,7 +697,7 @@ int chipcHw_vpmPhaseAlign(void) int adjustCount = 0; /* Disable VPM access */ - writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); + pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; /* Disable HW VPM phase alignment */ chipcHw_vpmHwPhaseAlignDisable(); /* Enable SW VPM phase alignment */ @@ -717,24 +715,23 @@ int chipcHw_vpmPhaseAlign(void) phaseControl--; } else { /* Enable VPM access */ - writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); + pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; /* Return adjust count */ return adjustCount; } /* Change the value of PH_CTRL. */ - reg32_write(&pChipcHw->VPMClock, - (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); + reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); /* Wait atleast 20 ns */ udelay(1); /* Toggle the LOAD_CH after phase control is written. */ - writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock); + pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; /* Count adjustment */ adjustCount++; } } /* Disable VPM access */ - writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1); + pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; return -1; } diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c index 8377d8054168..367df75d4bb3 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c @@ -26,15 +26,15 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* @@ -73,9 +73,9 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; - writel(chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET, - &pChipcHw->PLLConfig2); + pChipcHw->PLLConfig2 = + chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET; pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | @@ -87,30 +87,28 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); /* Enable CHIPC registers to control the PLL */ - writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); + pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; /* Set pre divider to get desired VCO frequency */ - writel(pllPreDivider2, &pChipcHw->PLLPreDivider2); + pChipcHw->PLLPreDivider2 = pllPreDivider2; /* Set NDIV Frac */ - writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2); + pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; /* This has to be removed once the default values are fixed for PLL2. */ - writel(0x38000700, &pChipcHw->PLLControl12); - writel(0x00000015, &pChipcHw->PLLControl22); + pChipcHw->PLLControl12 = 0x38000700; + pChipcHw->PLLControl22 = 0x00000015; /* Reset PLL2 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | + pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig2); + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } else { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | + pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | - chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig2); + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } REG_LOCAL_IRQ_RESTORE; } @@ -121,25 +119,22 @@ void chipcHw_pll2Enable(uint32_t vcoFreqHz) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - writel(readl(&pChipcHw->PLLConfig2) & + pChipcHw->PLLConfig2 &= ~(chipcHw_REG_PLL_CONFIG_A_RESET | - chipcHw_REG_PLL_CONFIG_POWER_DOWN), - &pChipcHw->PLLConfig2); + chipcHw_REG_PLL_CONFIG_POWER_DOWN); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) ; { REG_LOCAL_IRQ_SAVE; /* Remove digital reset */ - writel(readl(&pChipcHw->PLLConfig2) & - ~chipcHw_REG_PLL_CONFIG_D_RESET, - &pChipcHw->PLLConfig2); + pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; REG_LOCAL_IRQ_RESTORE; } @@ -162,9 +157,9 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; - writel(chipcHw_REG_PLL_CONFIG_D_RESET | - chipcHw_REG_PLL_CONFIG_A_RESET, - &pChipcHw->PLLConfig); + pChipcHw->PLLConfig = + chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET; /* Setting VCO frequency */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { pllPreDivider = @@ -187,22 +182,30 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) } /* Enable CHIPC registers to control the PLL */ - writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus); + pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; /* Set pre divider to get desired VCO frequency */ - writel(pllPreDivider, &pChipcHw->PLLPreDivider); + pChipcHw->PLLPreDivider = pllPreDivider; /* Set NDIV Frac */ if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { - writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider); + pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | + chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; } else { - writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider); + pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | + chipcHw_REG_PLL_DIVIDER_NDIV_f; } /* Reset PLL1 */ if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); + pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET | + chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } else { - writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig); + pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | + chipcHw_REG_PLL_CONFIG_A_RESET | + chipcHw_REG_PLL_CONFIG_VCO_800_1600 | + chipcHw_REG_PLL_CONFIG_POWER_DOWN; } REG_LOCAL_IRQ_RESTORE; @@ -213,19 +216,22 @@ void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) { REG_LOCAL_IRQ_SAVE; /* Remove analog reset and Power on the PLL */ - writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig); + pChipcHw->PLLConfig &= + ~(chipcHw_REG_PLL_CONFIG_A_RESET | + chipcHw_REG_PLL_CONFIG_POWER_DOWN); REG_LOCAL_IRQ_RESTORE; } /* Wait until PLL is locked */ - while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED) - || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED)) + while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) + || !(pChipcHw-> + PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) ; /* Remove digital reset */ { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig); + pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; REG_LOCAL_IRQ_RESTORE; } } @@ -261,7 +267,11 @@ void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initializ chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ - writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock); + pChipcHw->ACLKClock = + (pChipcHw-> + ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> + armBusRatio & + chipcHw_REG_ACLKClock_CLK_DIV_MASK); /* Set various core component frequencies. The order in which this is done is important for some. */ /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ diff --git a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c index f95ce913fa1e..2671d8896bbb 100644 --- a/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c +++ b/trunk/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c @@ -13,11 +13,11 @@ *****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #include -#include -#include +#include +#include /* ---- Private Constants and Types --------------------------------------- */ /* ---- Private Variables ------------------------------------------------- */ @@ -50,18 +50,17 @@ void chipcHw_reset(uint32_t mask) chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); } /* Bypass the PLL clocks before reboot */ - writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, - &pChipcHw->UARTClock); - writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT, - &pChipcHw->SPIClock); + pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; + pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ do { - writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i); + ((uint32_t *) MM_IO_BASE_ARAM)[i] = + ((uint32_t *) &chipcHw_reset_run_from_aram)[i]; i++; - } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ + } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ - flush_cache_all(); + CSP_CACHE_FLUSH_ALL; /* run the function from ARAM */ runFunc(); diff --git a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c index 547f746c7ff4..6b9be2e98e51 100644 --- a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw.c @@ -25,11 +25,11 @@ /****************************************************************************/ /* ---- Include Files ---------------------------------------------------- */ -#include -#include -#include +#include +#include +#include -#include +#include #include #include #include @@ -55,32 +55,33 @@ static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handl ) { uint32_t val = 0; dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); - dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module); + dmacHw_MISC_t *pMiscReg = + (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module); switch (pCblk->channel) { case 0: - val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; break; case 1: - val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; break; case 2: - val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; break; case 3: - val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; break; case 4: - val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; break; case 5: - val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; break; case 6: - val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28; + val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; break; case 7: - val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28; + val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; break; } diff --git a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c index fe438699d11e..a1f328357aa4 100644 --- a/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c +++ b/trunk/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c index dc4137ff75ca..16225e43f3c3 100644 --- a/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c +++ b/trunk/arch/arm/mach-bcmring/csp/tmr/tmrHw.c @@ -26,10 +26,10 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include -#include +#include #include #define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 diff --git a/trunk/arch/arm/mach-bcmring/include/cfg_global.h b/trunk/arch/arm/mach-bcmring/include/cfg_global.h new file mode 100644 index 000000000000..f01da877148e --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/cfg_global.h @@ -0,0 +1,13 @@ +#ifndef _CFG_GLOBAL_H_ +#define _CFG_GLOBAL_H_ + +#include + +#define CFG_GLOBAL_CHIP BCM11107 +#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING +#define CFG_GLOBAL_CHIP_REV 0xB0 +#define CFG_GLOBAL_RAM_SIZE 0x10000000 +#define CFG_GLOBAL_RAM_BASE 0x00000000 +#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 + +#endif /* _CFG_GLOBAL_H_ */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h b/trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h similarity index 74% rename from trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h rename to trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h index 449133eacdf5..b5beb0b30734 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/cfg_global.h +++ b/trunk/arch/arm/mach-bcmring/include/cfg_global_defines.h @@ -38,14 +38,3 @@ #define IMAGE_HEADER_SIZE_CHECKSUM 4 #endif -#ifndef _CFG_GLOBAL_H_ -#define _CFG_GLOBAL_H_ - -#define CFG_GLOBAL_CHIP BCM11107 -#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING -#define CFG_GLOBAL_CHIP_REV 0xB0 -#define CFG_GLOBAL_RAM_SIZE 0x10000000 -#define CFG_GLOBAL_RAM_BASE 0x00000000 -#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 - -#endif /* _CFG_GLOBAL_H_ */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/cache.h b/trunk/arch/arm/mach-bcmring/include/csp/cache.h new file mode 100644 index 000000000000..caa20e59db99 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/cache.h @@ -0,0 +1,35 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#ifndef CSP_CACHE_H +#define CSP_CACHE_H + +/* ---- Include Files ---------------------------------------------------- */ + +#include + +/* ---- Public Constants and Types --------------------------------------- */ + +#if defined(__KERNEL__) && !defined(STANDALONE) +#include + +#define CSP_CACHE_FLUSH_ALL flush_cache_all() + +#else + +#define CSP_CACHE_FLUSH_ALL + +#endif + +#endif /* CSP_CACHE_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/delay.h b/trunk/arch/arm/mach-bcmring/include/csp/delay.h new file mode 100644 index 000000000000..8b3d80367293 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/delay.h @@ -0,0 +1,36 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + +#ifndef CSP_DELAY_H +#define CSP_DELAY_H + +/* ---- Include Files ---------------------------------------------------- */ + +/* Some CSP routines require use of the following delay routines. Use the OS */ +/* version if available, otherwise use a CSP specific definition. */ +/* void udelay(unsigned long usecs); */ +/* void mdelay(unsigned long msecs); */ + +#if defined(__KERNEL__) && !defined(STANDALONE) + #include +#else + #include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + +#endif /* CSP_DELAY_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h b/trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h similarity index 99% rename from trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h rename to trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h index 9dc90f46a84d..e6a1dc484ca7 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h +++ b/trunk/arch/arm/mach-bcmring/include/csp/dmacHw.h @@ -23,9 +23,9 @@ #ifndef _DMACHW_H #define _DMACHW_H -#include +#include -#include +#include #include /* Define DMA Channel ID using DMA controller number (m) and channel number (c). diff --git a/trunk/arch/arm/mach-bcmring/include/csp/errno.h b/trunk/arch/arm/mach-bcmring/include/csp/errno.h new file mode 100644 index 000000000000..51357dd5b666 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/errno.h @@ -0,0 +1,32 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#ifndef CSP_ERRNO_H +#define CSP_ERRNO_H + +/* ---- Include Files ---------------------------------------------------- */ + +#if defined(__KERNEL__) +#include +#elif defined(CSP_SIMULATION) +#include +#else +#include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + +#endif /* CSP_ERRNO_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h b/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h new file mode 100644 index 000000000000..1c639c8ee08f --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/intcHw.h @@ -0,0 +1,40 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + +/****************************************************************************/ +/** +* @file intcHw.h +* +* @brief generic interrupt controller API +* +* @note +* None +*/ +/****************************************************************************/ + +#ifndef _INTCHW_H +#define _INTCHW_H + +/* ---- Include Files ---------------------------------------------------- */ +#include + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ +static inline void intcHw_irq_disable(void *basep, uint32_t mask); +static inline void intcHw_irq_enable(void *basep, uint32_t mask); + +#endif /* _INTCHW_H */ + diff --git a/trunk/arch/arm/mach-bcmring/include/csp/module.h b/trunk/arch/arm/mach-bcmring/include/csp/module.h new file mode 100644 index 000000000000..c30d2a5975a6 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/module.h @@ -0,0 +1,32 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + +#ifndef CSP_MODULE_H +#define CSP_MODULE_H + +/* ---- Include Files ---------------------------------------------------- */ + +#ifdef __KERNEL__ + #include +#else + #define EXPORT_SYMBOL(symbol) +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + + +#endif /* CSP_MODULE_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h b/trunk/arch/arm/mach-bcmring/include/csp/reg.h similarity index 81% rename from trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h rename to trunk/arch/arm/mach-bcmring/include/csp/reg.h index d9cbdca8cd25..56654d23c3d7 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/reg.h +++ b/trunk/arch/arm/mach-bcmring/include/csp/reg.h @@ -25,14 +25,13 @@ /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include /* ---- Public Constants and Types --------------------------------------- */ -#define __REG32(x) (*((volatile uint32_t __iomem *)(x))) -#define __REG16(x) (*((volatile uint16_t __iomem *)(x))) -#define __REG8(x) (*((volatile uint8_t __iomem *) (x))) +#define __REG32(x) (*((volatile uint32_t *)(x))) +#define __REG16(x) (*((volatile uint16_t *)(x))) +#define __REG8(x) (*((volatile uint8_t *) (x))) /* Macros used to define a sequence of reserved registers. The start / end */ /* are byte offsets in the particular register definition, with the "end" */ @@ -85,31 +84,31 @@ #endif -static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value) +static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - __raw_writel(__raw_readl(reg) & value, reg); + *reg &= value; REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value) +static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) { REG_LOCAL_IRQ_SAVE; - __raw_writel(__raw_readl(reg) | value, reg); + *reg |= value; REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask, +static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, uint32_t value) { REG_LOCAL_IRQ_SAVE; - __raw_writel((__raw_readl(reg) & mask) | value, reg); + *reg = (*reg & mask) | value; REG_LOCAL_IRQ_RESTORE; } -static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value) +static inline void reg32_write(volatile uint32_t *reg, uint32_t value) { - __raw_writel(value, reg); + *reg = value; } #endif /* CSP_REG_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/secHw.h b/trunk/arch/arm/mach-bcmring/include/csp/secHw.h new file mode 100644 index 000000000000..b9d7e0732dfc --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/secHw.h @@ -0,0 +1,65 @@ +/***************************************************************************** +* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +/****************************************************************************/ +/** +* @file secHw.h +* +* @brief Definitions for accessing low level security features +* +*/ +/****************************************************************************/ +#ifndef SECHW_H +#define SECHW_H + +typedef void (*secHw_FUNC_t) (void); + +typedef enum { + secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */ + secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */ +} secHw_MODE; + +/****************************************************************************/ +/** +* @brief Requesting to execute the function in secure mode +* +* This function requests the given function to run in secure mode +* +*/ +/****************************************************************************/ +void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */ + ); + +/****************************************************************************/ +/** +* @brief Sets the mode +* +* his function sets the processor mode (secure/non-secure) +* +*/ +/****************************************************************************/ +void secHw_SetMode(secHw_MODE /* Processor mode */ + ); + +/****************************************************************************/ +/** +* @brief Get the current mode +* +* This function retieves the processor mode (secure/non-secure) +* +*/ +/****************************************************************************/ +void secHw_GetMode(secHw_MODE *); + +#endif /* SECHW_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/stdint.h b/trunk/arch/arm/mach-bcmring/include/csp/stdint.h new file mode 100644 index 000000000000..3a8718bbf700 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/stdint.h @@ -0,0 +1,30 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + +#ifndef CSP_STDINT_H +#define CSP_STDINT_H + +/* ---- Include Files ---------------------------------------------------- */ + +#ifdef __KERNEL__ +#include +#else +#include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + +#endif /* CSP_STDINT_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/csp/string.h b/trunk/arch/arm/mach-bcmring/include/csp/string.h new file mode 100644 index 000000000000..ad9e4005f141 --- /dev/null +++ b/trunk/arch/arm/mach-bcmring/include/csp/string.h @@ -0,0 +1,34 @@ +/***************************************************************************** +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. +* +* Unless you and Broadcom execute a separate written software license +* agreement governing use of this software, this software is licensed to you +* under the terms of the GNU General Public License version 2, available at +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +* +* Notwithstanding the above, under no circumstances may you combine this +* software in any way with any other Broadcom software provided under a +* license other than the GPL, without Broadcom's express prior written +* consent. +*****************************************************************************/ + + + +#ifndef CSP_STRING_H +#define CSP_STRING_H + +/* ---- Include Files ---------------------------------------------------- */ + +#ifdef __KERNEL__ + #include +#else + #include +#endif + +/* ---- Public Constants and Types --------------------------------------- */ +/* ---- Public Variable Externs ------------------------------------------ */ +/* ---- Public Function Prototypes --------------------------------------- */ + + +#endif /* CSP_STRING_H */ + diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h b/trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h similarity index 99% rename from trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h rename to trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h index 1cc882ae60f5..2cbb530db8ea 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h +++ b/trunk/arch/arm/mach-bcmring/include/csp/tmrHw.h @@ -23,7 +23,7 @@ #ifndef _TMRHW_H #define _TMRHW_H -#include +#include typedef uint32_t tmrHw_ID_t; /* Timer ID */ typedef uint32_t tmrHw_COUNT_t; /* Timer count */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h index 0a89e0c63419..933ce68ed90b 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h @@ -17,7 +17,7 @@ /* ---- Include Files ---------------------------------------------------- */ #include -#include +#include /* ---- Public Constants and Types --------------------------------------- */ #define CAP_CONFIG0_VPM_DIS 0x00000001 diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h index 39f09cb89208..161973385faf 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h @@ -17,9 +17,9 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include -#include +#include +#include +#include #include /* ---- Public Constants and Types ---------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h index a66f3f7abb86..03238c299001 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h @@ -17,8 +17,8 @@ /* ---- Include Files ----------------------------------------------------- */ -#include -#include +#include +#include #include #include @@ -47,7 +47,7 @@ static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, /****************************************************************************/ static inline uint32_t chipcHw_getChipId(void) { - return readl(&pChipcHw->ChipId); + return pChipcHw->ChipId; } /****************************************************************************/ @@ -59,16 +59,15 @@ static inline uint32_t chipcHw_getChipId(void) /****************************************************************************/ static inline void chipcHw_enableSpreadSpectrum(void) { - if ((readl(&pChipcHw-> - PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != + if ((pChipcHw-> + PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { - writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | + ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = + (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << - ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT), - &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg); - writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) | - ddrcReg_PHY_ADDR_SS_CTRL_ENABLE, - &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl); + ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); + ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= + ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; } } @@ -94,8 +93,8 @@ static inline void chipcHw_disableSpreadSpectrum(void) /****************************************************************************/ static inline uint32_t chipcHw_getChipProductId(void) { - return (readl(&pChipcHw-> - ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >> + return (pChipcHw-> + ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> chipcHw_REG_CHIPID_BASE_SHIFT; } @@ -110,7 +109,7 @@ static inline uint32_t chipcHw_getChipProductId(void) /****************************************************************************/ static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) { - return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK; + return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; } /****************************************************************************/ @@ -157,7 +156,7 @@ static inline void chipcHw_busInterfaceClockDisable(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) { - return readl(&pChipcHw->BusIntfClock); + return pChipcHw->BusIntfClock; } /****************************************************************************/ @@ -216,9 +215,8 @@ static inline void chipcHw_softResetDisable(uint64_t mask) /* Deassert module soft reset */ REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1); - writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 & - (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); + pChipcHw->SoftReset1 ^= ctrl1; + pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); REG_LOCAL_IRQ_RESTORE; } @@ -229,10 +227,9 @@ static inline void chipcHw_softResetEnable(uint64_t mask) uint32_t unhold = 0; REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1); + pChipcHw->SoftReset1 |= ctrl1; /* Mask out unhold request bits */ - writel(readl(&pChipcHw->SoftReset2) | (ctrl2 & - (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2); + pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); /* Process unhold requests */ if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { @@ -249,7 +246,7 @@ static inline void chipcHw_softResetEnable(uint64_t mask) if (unhold) { /* Make sure unhold request is effective */ - writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1); + pChipcHw->SoftReset1 &= ~unhold; } REG_LOCAL_IRQ_RESTORE; } @@ -310,7 +307,7 @@ static inline void chipcHw_setOTPOption(uint64_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getStickyBits(void) { - return readl(&pChipcHw->Sticky); + return pChipcHw->Sticky; } /****************************************************************************/ @@ -331,7 +328,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_POR_BROM; } else { uint32_t sticky; - sticky = readl(pChipcHw->Sticky); + sticky = pChipcHw->Sticky; if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { @@ -358,7 +355,7 @@ static inline void chipcHw_setStickyBits(uint32_t mask) bits |= chipcHw_REG_STICKY_GENERAL_5; } } - writel(bits, pChipcHw->Sticky); + pChipcHw->Sticky = bits; REG_LOCAL_IRQ_RESTORE; } @@ -380,7 +377,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { - uint32_t sticky = readl(&pChipcHw->Sticky); + uint32_t sticky = pChipcHw->Sticky; if ((mask & chipcHw_REG_STICKY_BOOT_DONE) && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { @@ -413,7 +410,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) mask &= ~chipcHw_REG_STICKY_GENERAL_5; } } - writel(bits | mask, &pChipcHw->Sticky); + pChipcHw->Sticky = bits | mask; REG_LOCAL_IRQ_RESTORE; } @@ -429,7 +426,7 @@ static inline void chipcHw_clearStickyBits(uint32_t mask) /****************************************************************************/ static inline uint32_t chipcHw_getSoftStraps(void) { - return readl(&pChipcHw->SoftStraps); + return pChipcHw->SoftStraps; } /****************************************************************************/ @@ -459,7 +456,7 @@ static inline void chipcHw_setSoftStraps(uint32_t strapOptions) /****************************************************************************/ static inline uint32_t chipcHw_getPinStraps(void) { - return readl(&pChipcHw->PinStraps); + return pChipcHw->PinStraps; } /****************************************************************************/ @@ -674,9 +671,9 @@ static inline void chipcHw_selectGE3(void) /****************************************************************************/ static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) { - return (readl(chipcHw_REG_GPIO_MUX(pin))) & + return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & (chipcHw_REG_GPIO_MUX_MASK << - chipcHw_REG_GPIO_MUX_POSITION(pin)) >> + chipcHw_REG_GPIO_MUX_POSITION(pin))) >> chipcHw_REG_GPIO_MUX_POSITION(pin); } @@ -844,8 +841,8 @@ static inline void chipcHw_setUsbDevice(void) static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, chipcHw_OPTYPE_e type, int mode) { - uint32_t __iomem *pPLLReg = NULL; - uint32_t __iomem *pClockCtrl = NULL; + volatile uint32_t *pPLLReg = (uint32_t *) 0x0; + volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; switch (clock) { case chipcHw_CLOCK_DDR: @@ -1074,7 +1071,7 @@ static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock) /****************************************************************************/ static inline int chipcHw_isSoftwareStrapsEnable(void) { - return readl(&pChipcHw->SoftStraps) & 0x00000001; + return pChipcHw->SoftStraps & 0x00000001; } /****************************************************************************/ @@ -1141,7 +1138,7 @@ static inline void chipcHw_pll2TestDisable(void) /****************************************************************************/ static inline int chipcHw_isPllTestEnable(void) { - return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1150,7 +1147,7 @@ static inline int chipcHw_isPllTestEnable(void) /****************************************************************************/ static inline int chipcHw_isPll2TestEnable(void) { - return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; + return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; } /****************************************************************************/ @@ -1186,8 +1183,8 @@ static inline void chipcHw_pll2TestSelect(uint32_t val) /****************************************************************************/ static inline uint8_t chipcHw_getPllTestSelected(void) { - return (uint8_t) ((readl(&pChipcHw-> - PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((pChipcHw-> + PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1197,8 +1194,8 @@ static inline uint8_t chipcHw_getPllTestSelected(void) /****************************************************************************/ static inline uint8_t chipcHw_getPll2TestSelected(void) { - return (uint8_t) ((readl(&pChipcHw-> - PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) + return (uint8_t) ((pChipcHw-> + PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); } @@ -1211,8 +1208,7 @@ static inline uint8_t chipcHw_getPll2TestSelected(void) static inline void chipcHw_pll1Disable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig); + pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; REG_LOCAL_IRQ_RESTORE; } @@ -1225,8 +1221,7 @@ static inline void chipcHw_pll1Disable(void) static inline void chipcHw_pll2Disable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN, - &pChipcHw->PLLConfig2); + pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; REG_LOCAL_IRQ_RESTORE; } @@ -1238,8 +1233,7 @@ static inline void chipcHw_pll2Disable(void) static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, - &pChipcHw->Spare1); + pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1251,8 +1245,7 @@ static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE, - &pChipcHw->Spare1); + pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1340,8 +1333,7 @@ static inline void chipcHw_ddrHwPhaseAlignDisable(void) static inline void chipcHw_vpmSwPhaseAlignEnable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE, - &pChipcHw->VPMPhaseCtrl1); + pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1380,8 +1372,7 @@ static inline void chipcHw_vpmHwPhaseAlignEnable(void) static inline void chipcHw_vpmHwPhaseAlignDisable(void) { REG_LOCAL_IRQ_SAVE; - writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE, - &pChipcHw->VPMPhaseCtrl1); + pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; REG_LOCAL_IRQ_RESTORE; } @@ -1483,8 +1474,8 @@ chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin) /****************************************************************************/ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1497,8 +1488,8 @@ static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; } /****************************************************************************/ @@ -1509,8 +1500,8 @@ static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> chipcHw_REG_DDR_PHASE_STATUS_SHIFT; } @@ -1522,8 +1513,8 @@ static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> chipcHw_REG_VPM_PHASE_STATUS_SHIFT; } @@ -1535,8 +1526,8 @@ static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) /****************************************************************************/ static inline uint32_t chipcHw_getDdrPhaseControl(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> chipcHw_REG_DDR_PHASE_CTRL_SHIFT; } @@ -1548,8 +1539,8 @@ static inline uint32_t chipcHw_getDdrPhaseControl(void) /****************************************************************************/ static inline uint32_t chipcHw_getVpmPhaseControl(void) { - return (readl(&pChipcHw-> - PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> + return (pChipcHw-> + PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> chipcHw_REG_VPM_PHASE_CTRL_SHIFT; } diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h index 26f5d0e4e1dd..b162448f613c 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h @@ -24,7 +24,7 @@ #define CHIPCHW_REG_H #include -#include +#include #include #define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC @@ -131,8 +131,8 @@ typedef struct { uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ } chipcHw_REG_t; -#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS) -#define pChipcPhysical (MM_ADDR_IO_CHIPC) +#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) +#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) #define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 #define chipcHw_REG_CHIPID_BASE_SHIFT 12 diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h index 39da2c1fdafb..f1b68e26fa6d 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h @@ -30,8 +30,8 @@ extern "C" { /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include @@ -416,7 +416,7 @@ extern "C" { } ddrcReg_PHY_ADDR_CTL_REG_t; #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 -#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) +#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) /* @todo These SS definitions are duplicates of ones below */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h index 9d9455e0c391..d67e2f8c22de 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_PRIV_H #define _DMACHW_PRIV_H -#include +#include /* Data type for DMA Link List Item */ typedef struct { diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h index 7cd0aafa6f6e..f1ecf96f2da5 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h @@ -24,7 +24,7 @@ #ifndef _DMACHW_REG_H #define _DMACHW_REG_H -#include +#include #include /* Data type for 64 bit little endian register */ @@ -121,75 +121,75 @@ typedef struct { } dmacHw_MISC_t; /* Base registers */ -#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ -#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ +#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ +#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ extern uint32_t dmaChannelCount_0; extern uint32_t dmaChannelCount_1; /* Define channel specific registers */ -#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) +#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) /* Raw interrupt status registers */ -#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) -#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) -#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) -#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) -#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) -#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) +#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) +#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) +#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) +#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) +#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) +#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) -#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) -#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) -#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) -#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) -#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) +#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) +#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) +#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) +#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) +#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) +#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) /* Interrupt status registers */ -#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) -#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) -#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) -#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) -#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) -#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) +#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) +#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) +#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) +#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) +#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) +#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) /* Interrupt clear registers */ -#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) -#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) -#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) -#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) -#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) -#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) -#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) +#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) +#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) +#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) +#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) +#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) +#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) +#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) /* Software handshaking registers */ -#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) -#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) -#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) -#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) +#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) +#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) +#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) +#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) /* Miscellaneous registers */ -#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) -#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) -#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) -#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) -#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) -#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) -#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) -#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) -#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) -#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) -#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) -#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) -#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) -#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) -#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) -#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) +#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) +#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) +#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) +#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) +#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) +#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) +#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) +#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) +#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) +#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) +#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) +#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) +#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) +#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) +#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) +#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) /* Channel control registers */ #define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h index 27f59dd27792..cfa91bed9d34 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h @@ -18,7 +18,7 @@ /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include #if defined(__KERNEL__) diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h index f59db25b5632..0aeb6a6fe7f8 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h @@ -27,8 +27,8 @@ #define _INTCHW_REG_H /* ---- Include Files ---------------------------------------------------- */ -#include -#include +#include +#include #include /* ---- Public Constants and Types --------------------------------------- */ @@ -37,9 +37,9 @@ #define INTCHW_NUM_INTC 3 /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ -#define INTCHW_INTC0 (MM_IO_BASE_INTC0) -#define INTCHW_INTC1 (MM_IO_BASE_INTC1) -#define INTCHW_SINTC (MM_IO_BASE_SINTC) +#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) +#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) +#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) /* INTC0 - interrupt controller 0 */ #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ @@ -232,15 +232,15 @@ /* ---- Public Variable Externs ------------------------------------------ */ /* ---- Public Function Prototypes --------------------------------------- */ /* Clear one or more IRQ interrupts. */ -static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask) +static inline void intcHw_irq_disable(void *basep, uint32_t mask) { - writel(mask, basep + INTCHW_INTENCLEAR); + __REG32(basep + INTCHW_INTENCLEAR) = mask; } /* Enables one or more IRQ interrupts. */ -static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask) +static inline void intcHw_irq_enable(void *basep, uint32_t mask) { - writel(mask, basep + INTCHW_INTENABLE); + __REG32(basep + INTCHW_INTENABLE) = mask; } #endif /* _INTCHW_REG_H */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h index d571962f2904..ad58cf873377 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h @@ -29,7 +29,7 @@ /* ---- Include Files ---------------------------------------------------- */ #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h index 47450c23685a..de92ec6a01aa 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/mm_io.h @@ -30,7 +30,7 @@ #include #if !defined(CSP_SIMULATION) -#include +#include #endif /* ---- Public Constants and Types --------------------------------------- */ @@ -49,7 +49,7 @@ #ifdef __ASSEMBLY__ #define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) #else -#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ +#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) #endif #endif @@ -60,8 +60,8 @@ #ifdef __ASSEMBLY__ #define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) #else -#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ - ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF))) +#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ + ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) #endif #endif diff --git a/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h index 55d3cd4fd1e7..9cd6a032ab71 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h @@ -34,7 +34,7 @@ /****************************************************************************/ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; + secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; @@ -53,13 +53,13 @@ static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK /****************************************************************************/ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ ) { - secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; + secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; if (mask & 0x0000FFFF) { - writel(mask & 0x0000FFFF, ®p->reg[secHw_IDX_LS].setUnsecure); + regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; } if (mask & 0xFFFF0000) { - writel(mask >> 16, ®p->reg[secHw_IDX_MS].setUnsecure); + regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; } } @@ -71,7 +71,7 @@ static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MA /****************************************************************************/ static inline uint32_t secHw_getStatus(void) { - secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC; + secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; return (regp->reg[1].status << 16) + regp->reg[0].status; } diff --git a/trunk/arch/arm/mach-bcmring/include/mach/dma.h b/trunk/arch/arm/mach-bcmring/include/mach/dma.h index 13e01384d6fc..72543781207b 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/dma.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/dma.h @@ -27,7 +27,7 @@ #include #include -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/hardware.h b/trunk/arch/arm/mach-bcmring/include/mach/hardware.h index a0c92b4b8c60..6ae20a649a97 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/hardware.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/hardware.h @@ -22,7 +22,7 @@ #define __ASM_ARCH_HARDWARE_H #include -#include +#include #include /* Hardware addresses of major areas. diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h index f8d51a8b0b15..387376ffb56b 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/reg_nand.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_NAND_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ diff --git a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h index 56dd9de7d83f..0992842caa77 100644 --- a/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h +++ b/trunk/arch/arm/mach-bcmring/include/mach/reg_umi.h @@ -30,7 +30,7 @@ #define __ASM_ARCH_REG_UMI_H /* ---- Include Files ---------------------------------------------------- */ -#include +#include #include /* ---- Constants and Types ---------------------------------------------- */ @@ -233,5 +233,5 @@ #define REG_UMI_BCH_ERR_LOC_WORD 0x00000018 /* location within a page (512 byte) */ #define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0 -#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) +#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16)) #endif diff --git a/trunk/arch/arm/mach-bcmring/mm.c b/trunk/arch/arm/mach-bcmring/mm.c index 33824a81cac4..1adec78ec940 100644 --- a/trunk/arch/arm/mach-bcmring/mm.c +++ b/trunk/arch/arm/mach-bcmring/mm.c @@ -20,12 +20,12 @@ #include #include -#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \ +#define IO_DESC(va, sz) { .virtual = va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_DEVICE } -#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \ +#define MEM_DESC(va, sz) { .virtual = va, \ .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ .length = sz, \ .type = MT_MEMORY } diff --git a/trunk/arch/arm/mach-bcmring/timer.c b/trunk/arch/arm/mach-bcmring/timer.c index 59412903466e..af9c3d7e2a0c 100644 --- a/trunk/arch/arm/mach-bcmring/timer.c +++ b/trunk/arch/arm/mach-bcmring/timer.c @@ -14,7 +14,7 @@ #include #include -#include +#include #include /* The core.c file initializes timers 1 and 3 as a linux clocksource. */ diff --git a/trunk/arch/arm/mach-davinci/board-neuros-osd2.c b/trunk/arch/arm/mach-davinci/board-neuros-osd2.c index f6b9fc70161b..5de69f2fcca9 100644 --- a/trunk/arch/arm/mach-davinci/board-neuros-osd2.c +++ b/trunk/arch/arm/mach-davinci/board-neuros-osd2.c @@ -162,6 +162,38 @@ static void __init davinci_ntosd2_map_io(void) dm644x_init(); } +/* + I2C initialization +*/ +static struct davinci_i2c_platform_data ntosd2_i2c_pdata = { + .bus_freq = 20 /* kHz */, + .bus_delay = 100 /* usec */, +}; + +static struct i2c_board_info __initdata ntosd2_i2c_info[] = { +}; + +static int ntosd2_init_i2c(void) +{ + int status; + + davinci_init_i2c(&ntosd2_i2c_pdata); + status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type); + if (status == 0) { + status = gpio_direction_input(NTOSD2_MSP430_IRQ); + if (status == 0) { + status = gpio_to_irq(NTOSD2_MSP430_IRQ); + if (status > 0) { + ntosd2_i2c_info[0].irq = status; + i2c_register_board_info(1, + ntosd2_i2c_info, + ARRAY_SIZE(ntosd2_i2c_info)); + } + } + } + return status; +} + static struct davinci_mmc_config davinci_ntosd2_mmc_config = { .wires = 4, .version = MMC_CTLR_VERSION_1 @@ -186,6 +218,7 @@ static __init void davinci_ntosd2_init(void) { struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; + int status; aemif_clk = clk_get(NULL, "aemif"); clk_enable(aemif_clk); @@ -209,6 +242,12 @@ static __init void davinci_ntosd2_init(void) platform_add_devices(davinci_ntosd2_devices, ARRAY_SIZE(davinci_ntosd2_devices)); + /* Initialize I2C interface specific for this board */ + status = ntosd2_init_i2c(); + if (status < 0) + pr_warning("davinci_ntosd2_init: msp430 irq setup failed:" + " %d\n", status); + davinci_serial_init(&uart_config); dm644x_init_asp(&dm644x_ntosd2_snd_data); diff --git a/trunk/arch/arm/mach-dove/common.c b/trunk/arch/arm/mach-dove/common.c index cc4c6a5a357c..4db5de54b6a7 100644 --- a/trunk/arch/arm/mach-dove/common.c +++ b/trunk/arch/arm/mach-dove/common.c @@ -49,6 +49,16 @@ static struct map_desc dove_io_desc[] __initdata = { .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), .length = DOVE_NB_REGS_SIZE, .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE0_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE), + .length = DOVE_PCIE0_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = DOVE_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE), + .length = DOVE_PCIE1_IO_SIZE, + .type = MT_DEVICE, }, }; @@ -92,8 +102,7 @@ void __init dove_ehci1_init(void) void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE, - IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR, - 1600); + IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR); } /***************************************************************************** diff --git a/trunk/arch/arm/mach-dove/include/mach/dove.h b/trunk/arch/arm/mach-dove/include/mach/dove.h index c91e3004a47b..d52b0ef313b7 100644 --- a/trunk/arch/arm/mach-dove/include/mach/dove.h +++ b/trunk/arch/arm/mach-dove/include/mach/dove.h @@ -50,12 +50,14 @@ #define DOVE_NB_REGS_SIZE SZ_8M #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 +#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000 #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 -#define DOVE_PCIE0_IO_SIZE SZ_64K +#define DOVE_PCIE0_IO_SIZE SZ_1M #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 -#define DOVE_PCIE1_IO_BUS_BASE 0x00010000 -#define DOVE_PCIE1_IO_SIZE SZ_64K +#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000 +#define DOVE_PCIE1_IO_BUS_BASE 0x00100000 +#define DOVE_PCIE1_IO_SIZE SZ_1M /* * Dove Core Registers Map diff --git a/trunk/arch/arm/mach-dove/include/mach/io.h b/trunk/arch/arm/mach-dove/include/mach/io.h new file mode 100644 index 000000000000..29c8b85355a5 --- /dev/null +++ b/trunk/arch/arm/mach-dove/include/mach/io.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-dove/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "dove.h" + +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \ + DOVE_PCIE0_IO_VIRT_BASE)) + +#endif diff --git a/trunk/arch/arm/mach-dove/pcie.c b/trunk/arch/arm/mach-dove/pcie.c index 355332d502cb..47921b0cdc65 100644 --- a/trunk/arch/arm/mach-dove/pcie.c +++ b/trunk/arch/arm/mach-dove/pcie.c @@ -26,8 +26,9 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; + char io_space_name[16]; char mem_space_name[16]; - struct resource res; + struct resource res[2]; }; static struct pcie_port pcie_port[2]; @@ -52,10 +53,24 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_setup(pp->base); - if (pp->index == 0) - pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); - else - pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); + /* + * IORESOURCE_IO + */ + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d I/O", pp->index); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + if (pp->index == 0) { + pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1; + } else { + pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE; + pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1; + } + pp->res[0].flags = IORESOURCE_IO; + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe IO resource failed\n"); + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); /* * IORESOURCE_MEM @@ -63,18 +78,18 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d MEM", pp->index); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res.name = pp->mem_space_name; + pp->res[1].name = pp->mem_space_name; if (pp->index == 0) { - pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; - pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; + pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1; } else { - pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; - pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; + pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1; } - pp->res.flags = IORESOURCE_MEM; - if (request_resource(&iomem_resource, &pp->res)) + pp->res[1].flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe Memory resource failed\n"); - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); return 1; } @@ -195,7 +210,7 @@ static void __init add_pcie_port(int index, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(&pp->res, 0, sizeof(pp->res)); + memset(pp->res, 0, sizeof(pp->res)); } else { printk(KERN_INFO "link down, ignoring\n"); } diff --git a/trunk/arch/arm/mach-ebsa110/core.c b/trunk/arch/arm/mach-ebsa110/core.c index f0fe6b5350e2..6f8068692edf 100644 --- a/trunk/arch/arm/mach-ebsa110/core.c +++ b/trunk/arch/arm/mach-ebsa110/core.c @@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = { * sparse external-decode ISAIO space */ { /* IRQ_STAT/IRQ_MCLR */ - .virtual = (unsigned long)IRQ_STAT, + .virtual = IRQ_STAT, .pfn = __phys_to_pfn(TRICK4_PHYS), .length = TRICK4_SIZE, .type = MT_DEVICE }, { /* IRQ_MASK/IRQ_MSET */ - .virtual = (unsigned long)IRQ_MASK, + .virtual = IRQ_MASK, .pfn = __phys_to_pfn(TRICK3_PHYS), .length = TRICK3_SIZE, .type = MT_DEVICE }, { /* SOFT_BASE */ - .virtual = (unsigned long)SOFT_BASE, + .virtual = SOFT_BASE, .pfn = __phys_to_pfn(TRICK1_PHYS), .length = TRICK1_SIZE, .type = MT_DEVICE }, { /* PIT_BASE */ - .virtual = (unsigned long)PIT_BASE, + .virtual = PIT_BASE, .pfn = __phys_to_pfn(TRICK0_PHYS), .length = TRICK0_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-ebsa110/core.h b/trunk/arch/arm/mach-ebsa110/core.h index afe137ee172e..c93c9e43012d 100644 --- a/trunk/arch/arm/mach-ebsa110/core.h +++ b/trunk/arch/arm/mach-ebsa110/core.h @@ -31,11 +31,11 @@ #define TRICK7_PHYS 0xf3c00000 /* Virtual addresses */ -#define PIT_BASE IOMEM(0xfc000000) /* trick 0 */ -#define SOFT_BASE IOMEM(0xfd000000) /* trick 1 */ -#define IRQ_MASK IOMEM(0xfe000000) /* trick 3 - read */ -#define IRQ_MSET IOMEM(0xfe000000) /* trick 3 - write */ -#define IRQ_STAT IOMEM(0xff000000) /* trick 4 - read */ -#define IRQ_MCLR IOMEM(0xff000000) /* trick 4 - write */ +#define PIT_BASE 0xfc000000 /* trick 0 */ +#define SOFT_BASE 0xfd000000 /* trick 1 */ +#define IRQ_MASK 0xfe000000 /* trick 3 - read */ +#define IRQ_MSET 0xfe000000 /* trick 3 - write */ +#define IRQ_STAT 0xff000000 /* trick 4 - read */ +#define IRQ_MCLR 0xff000000 /* trick 4 - write */ #endif diff --git a/trunk/arch/arm/mach-ep93xx/adssphere.c b/trunk/arch/arm/mach-ep93xx/adssphere.c index 41383bf03d4b..a472777e9eba 100644 --- a/trunk/arch/arm/mach-ep93xx/adssphere.c +++ b/trunk/arch/arm/mach-ep93xx/adssphere.c @@ -13,7 +13,6 @@ #include #include #include -#include #include diff --git a/trunk/arch/arm/mach-ep93xx/gesbc9312.c b/trunk/arch/arm/mach-ep93xx/gesbc9312.c index 7fd705b5efe4..437c34111155 100644 --- a/trunk/arch/arm/mach-ep93xx/gesbc9312.c +++ b/trunk/arch/arm/mach-ep93xx/gesbc9312.c @@ -13,7 +13,6 @@ #include #include #include -#include #include diff --git a/trunk/arch/arm/mach-ep93xx/ts72xx.h b/trunk/arch/arm/mach-ep93xx/include/mach/ts72xx.h similarity index 89% rename from trunk/arch/arm/mach-ep93xx/ts72xx.h rename to trunk/arch/arm/mach-ep93xx/include/mach/ts72xx.h index 071feaa30adc..f1397a13e76b 100644 --- a/trunk/arch/arm/mach-ep93xx/ts72xx.h +++ b/trunk/arch/arm/mach-ep93xx/include/mach/ts72xx.h @@ -14,7 +14,7 @@ */ #define TS72XX_MODEL_PHYS_BASE 0x22000000 -#define TS72XX_MODEL_VIRT_BASE IOMEM(0xfebff000) +#define TS72XX_MODEL_VIRT_BASE 0xfebff000 #define TS72XX_MODEL_SIZE 0x00001000 #define TS72XX_MODEL_TS7200 0x00 @@ -26,7 +26,7 @@ #define TS72XX_OPTIONS_PHYS_BASE 0x22400000 -#define TS72XX_OPTIONS_VIRT_BASE IOMEM(0xfebfe000) +#define TS72XX_OPTIONS_VIRT_BASE 0xfebfe000 #define TS72XX_OPTIONS_SIZE 0x00001000 #define TS72XX_OPTIONS_COM2_RS485 0x02 @@ -34,18 +34,18 @@ #define TS72XX_OPTIONS2_PHYS_BASE 0x22800000 -#define TS72XX_OPTIONS2_VIRT_BASE IOMEM(0xfebfd000) +#define TS72XX_OPTIONS2_VIRT_BASE 0xfebfd000 #define TS72XX_OPTIONS2_SIZE 0x00001000 #define TS72XX_OPTIONS2_TS9420 0x04 #define TS72XX_OPTIONS2_TS9420_BOOT 0x02 -#define TS72XX_RTC_INDEX_VIRT_BASE IOMEM(0xfebf9000) +#define TS72XX_RTC_INDEX_VIRT_BASE 0xfebf9000 #define TS72XX_RTC_INDEX_PHYS_BASE 0x10800000 #define TS72XX_RTC_INDEX_SIZE 0x00001000 -#define TS72XX_RTC_DATA_VIRT_BASE IOMEM(0xfebf8000) +#define TS72XX_RTC_DATA_VIRT_BASE 0xfebf8000 #define TS72XX_RTC_DATA_PHYS_BASE 0x11700000 #define TS72XX_RTC_DATA_SIZE 0x00001000 diff --git a/trunk/arch/arm/mach-ep93xx/ts72xx.c b/trunk/arch/arm/mach-ep93xx/ts72xx.c index 3c4c233391dc..75cab2d7ec73 100644 --- a/trunk/arch/arm/mach-ep93xx/ts72xx.c +++ b/trunk/arch/arm/mach-ep93xx/ts72xx.c @@ -21,6 +21,7 @@ #include #include +#include #include #include @@ -28,31 +29,30 @@ #include #include "soc.h" -#include "ts72xx.h" static struct map_desc ts72xx_io_desc[] __initdata = { { - .virtual = (unsigned long)TS72XX_MODEL_VIRT_BASE, + .virtual = TS72XX_MODEL_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_MODEL_PHYS_BASE), .length = TS72XX_MODEL_SIZE, .type = MT_DEVICE, }, { - .virtual = (unsigned long)TS72XX_OPTIONS_VIRT_BASE, + .virtual = TS72XX_OPTIONS_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_OPTIONS_PHYS_BASE), .length = TS72XX_OPTIONS_SIZE, .type = MT_DEVICE, }, { - .virtual = (unsigned long)TS72XX_OPTIONS2_VIRT_BASE, + .virtual = TS72XX_OPTIONS2_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_OPTIONS2_PHYS_BASE), .length = TS72XX_OPTIONS2_SIZE, .type = MT_DEVICE, }, { - .virtual = (unsigned long)TS72XX_RTC_INDEX_VIRT_BASE, + .virtual = TS72XX_RTC_INDEX_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_RTC_INDEX_PHYS_BASE), .length = TS72XX_RTC_INDEX_SIZE, .type = MT_DEVICE, }, { - .virtual = (unsigned long)TS72XX_RTC_DATA_VIRT_BASE, + .virtual = TS72XX_RTC_DATA_VIRT_BASE, .pfn = __phys_to_pfn(TS72XX_RTC_DATA_PHYS_BASE), .length = TS72XX_RTC_DATA_SIZE, .type = MT_DEVICE, diff --git a/trunk/arch/arm/mach-exynos/clock-exynos5.c b/trunk/arch/arm/mach-exynos/clock-exynos5.c index 3b00e299b624..774533c67066 100644 --- a/trunk/arch/arm/mach-exynos/clock-exynos5.c +++ b/trunk/arch/arm/mach-exynos/clock-exynos5.c @@ -166,6 +166,11 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable) return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable); } +static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable) +{ + return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable); +} + static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable); @@ -666,6 +671,10 @@ static struct clk exynos5_init_clocks_off[] = { .name = "usbotg", .enable = exynos5_clk_ip_fsys_ctrl, .ctrlbit = (1 << 7), + }, { + .name = "gps", + .enable = exynos5_clk_ip_gps_ctrl, + .ctrlbit = ((1 << 3) | (1 << 2) | (1 << 0)), }, { .name = "nfcon", .enable = exynos5_clk_ip_fsys_ctrl, diff --git a/trunk/arch/arm/mach-exynos/include/mach/map.h b/trunk/arch/arm/mach-exynos/include/mach/map.h index 6d33f50c2e56..c72b675b3e4b 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/map.h +++ b/trunk/arch/arm/mach-exynos/include/mach/map.h @@ -89,7 +89,7 @@ #define EXYNOS4_PA_L2CC 0x10502000 #define EXYNOS4_PA_MDMA0 0x10810000 -#define EXYNOS4_PA_MDMA1 0x12850000 +#define EXYNOS4_PA_MDMA1 0x12840000 #define EXYNOS4_PA_PDMA0 0x12680000 #define EXYNOS4_PA_PDMA1 0x12690000 #define EXYNOS5_PA_MDMA0 0x10800000 @@ -131,6 +131,7 @@ #define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000 #define EXYNOS5_PA_SYSMMU_IOP 0x12360000 #define EXYNOS5_PA_SYSMMU_RTIC 0x12370000 +#define EXYNOS5_PA_SYSMMU_GPS 0x12630000 #define EXYNOS5_PA_SYSMMU_ISP 0x13260000 #define EXYNOS5_PA_SYSMMU_DRC 0x12370000 #define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000 diff --git a/trunk/arch/arm/mach-exynos/include/mach/sysmmu.h b/trunk/arch/arm/mach-exynos/include/mach/sysmmu.h index 88a4543b0001..998daf2add92 100644 --- a/trunk/arch/arm/mach-exynos/include/mach/sysmmu.h +++ b/trunk/arch/arm/mach-exynos/include/mach/sysmmu.h @@ -58,7 +58,7 @@ static inline void platform_set_sysmmu( #endif #else /* !CONFIG_EXYNOS_DEV_SYSMMU */ -#define platform_set_sysmmu(sysmmu, dev) do { } while (0) +#define platform_set_sysmmu(dev, sysmmu) do { } while (0) #endif #define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id) diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c index 4e574c24581c..5ca80307d6d7 100644 --- a/trunk/arch/arm/mach-exynos/mach-origen.c +++ b/trunk/arch/arm/mach-exynos/mach-origen.c @@ -42,7 +42,6 @@ #include #include #include -#include #include #include @@ -735,11 +734,6 @@ static void __init origen_bt_setup(void) s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE); } -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - static void s5p_tv_setup(void) { /* Direct HPD to HDMI chip */ @@ -787,7 +781,6 @@ static void __init origen_machine_init(void) s5p_tv_setup(); s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); #ifdef CONFIG_DRM_EXYNOS s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata; diff --git a/trunk/arch/arm/mach-exynos/mach-smdkv310.c b/trunk/arch/arm/mach-exynos/mach-smdkv310.c index 73f2bce097e1..3cfa688d274a 100644 --- a/trunk/arch/arm/mach-exynos/mach-smdkv310.c +++ b/trunk/arch/arm/mach-exynos/mach-smdkv310.c @@ -40,7 +40,6 @@ #include #include #include -#include #include #include @@ -355,11 +354,6 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = { .pwm_period_ns = 1000, }; -/* I2C module and id for HDMIPHY */ -static struct i2c_board_info hdmiphy_info = { - I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38), -}; - static void s5p_tv_setup(void) { /* direct HPD to HDMI chip */ @@ -394,7 +388,6 @@ static void __init smdkv310_machine_init(void) s5p_tv_setup(); s5p_i2c_hdmiphy_set_platdata(NULL); - s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0); samsung_keypad_set_platdata(&smdkv310_keypad_data); diff --git a/trunk/arch/arm/mach-exynos/pm_domains.c b/trunk/arch/arm/mach-exynos/pm_domains.c index c0bc83a7663e..373c3c00d24c 100644 --- a/trunk/arch/arm/mach-exynos/pm_domains.c +++ b/trunk/arch/arm/mach-exynos/pm_domains.c @@ -115,7 +115,7 @@ static __init int exynos_pm_dt_parse_domains(void) } #endif /* CONFIG_OF */ -static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, +static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev, struct exynos_pm_domain *pd) { if (pdev->dev.bus) { diff --git a/trunk/arch/arm/mach-footbridge/common.c b/trunk/arch/arm/mach-footbridge/common.c index a42b369bc439..3e6aaa6361da 100644 --- a/trunk/arch/arm/mach-footbridge/common.c +++ b/trunk/arch/arm/mach-footbridge/common.c @@ -15,7 +15,7 @@ #include #include #include - + #include #include #include @@ -26,7 +26,6 @@ #include #include -#include #include "common.h" @@ -176,6 +175,11 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = { .pfn = __phys_to_pfn(DC21285_PCI_IACK), .length = PCIIACK_SIZE, .type = MT_DEVICE, + }, { + .virtual = PCIO_BASE, + .pfn = __phys_to_pfn(DC21285_PCI_IO), + .length = PCIO_SIZE, + .type = MT_DEVICE, }, #endif }; @@ -192,10 +196,8 @@ void __init footbridge_map_io(void) * Now, work out what we've got to map in addition on this * platform. */ - if (footbridge_cfn_mode()) { + if (footbridge_cfn_mode()) iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); - pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO)); - } } void footbridge_restart(char mode, const char *cmd) diff --git a/trunk/arch/arm/mach-footbridge/dc21285.c b/trunk/arch/arm/mach-footbridge/dc21285.c index a7cd2cf5e08d..9d62e3381024 100644 --- a/trunk/arch/arm/mach-footbridge/dc21285.c +++ b/trunk/arch/arm/mach-footbridge/dc21285.c @@ -276,8 +276,8 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys) sys->mem_offset = DC21285_PCI_MEM; - pci_ioremap_io(0, DC21285_PCI_IO); - + pci_add_resource_offset(&sys->resources, + &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset); pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); @@ -298,7 +298,7 @@ void __init dc21285_preinit(void) mem_size = (unsigned int)high_memory - PAGE_OFFSET; for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1) if (mem_mask >= mem_size) - break; + break; /* * These registers need to be set up whether we're the @@ -350,6 +350,14 @@ void __init dc21285_preinit(void) "PCI data parity", NULL); if (cfn_mode) { + static struct resource csrio; + + csrio.flags = IORESOURCE_IO; + csrio.name = "Footbridge"; + + allocate_resource(&ioport_resource, &csrio, 128, + 0xff00, 0xffff, 128, NULL, NULL); + /* * Map our SDRAM at a known address in PCI space, just in case * the firmware had other ideas. Using a nonzero base is @@ -357,7 +365,7 @@ void __init dc21285_preinit(void) * in the range 0x000a0000 to 0x000c0000. (eg, S3 cards). */ *CSR_PCICSRBASE = 0xf4000000; - *CSR_PCICSRIOBASE = 0; + *CSR_PCICSRIOBASE = csrio.start; *CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET); *CSR_PCIROMBASE = 0; *CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | diff --git a/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S b/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S index c169f0c99b2a..e5acde25ffc5 100644 --- a/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S +++ b/trunk/arch/arm/mach-footbridge/include/mach/debug-macro.S @@ -17,8 +17,7 @@ /* For NetWinder debugging */ .macro addruart, rp, rv, tmp mov \rp, #0x000003f8 - orr \rv, \rp, #0xfe000000 @ virtual - orr \rv, \rv, #0x00e00000 @ virtual + orr \rv, \rp, #0xff000000 @ virtual orr \rp, \rp, #0x7c000000 @ physical .endm diff --git a/trunk/arch/arm/mach-footbridge/include/mach/io.h b/trunk/arch/arm/mach-footbridge/include/mach/io.h index aba46388cc0c..aba531eebbc6 100644 --- a/trunk/arch/arm/mach-footbridge/include/mach/io.h +++ b/trunk/arch/arm/mach-footbridge/include/mach/io.h @@ -14,10 +14,18 @@ #ifndef __ASM_ARM_ARCH_IO_H #define __ASM_ARM_ARCH_IO_H +#ifdef CONFIG_MMU +#define MMU_IO(a, b) (a) +#else +#define MMU_IO(a, b) (b) +#endif + +#define PCIO_SIZE 0x00100000 +#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) + /* - * Translation of various i/o addresses to host addresses for !CONFIG_MMU + * Translation of various region addresses to virtual addresses */ -#define PCIO_BASE 0x7c000000 #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) #endif diff --git a/trunk/arch/arm/mach-gemini/irq.c b/trunk/arch/arm/mach-gemini/irq.c index 020852d3bdd8..ca70e5fcc7ac 100644 --- a/trunk/arch/arm/mach-gemini/irq.c +++ b/trunk/arch/arm/mach-gemini/irq.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #define IRQ_SOURCE(base_addr) (base_addr + 0x00) diff --git a/trunk/arch/arm/mach-imx/Makefile b/trunk/arch/arm/mach-imx/Makefile index d1204198ca83..07f7c226e4cf 100644 --- a/trunk/arch/arm/mach-imx/Makefile +++ b/trunk/arch/arm/mach-imx/Makefile @@ -9,11 +9,10 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o -imx5-pm-$(CONFIG_PM) += pm-imx5.o -obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o +obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ - clk-pfd.o clk-busy.o clk.o + clk-pfd.o clk-busy.o # Support for CMOS sensor interface obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o @@ -71,13 +70,14 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o obj-$(CONFIG_HAVE_IMX_SRC) += src.o -AFLAGS_headsmp.o :=-Wa,-march=armv7-a -obj-$(CONFIG_SMP) += headsmp.o platsmp.o +obj-$(CONFIG_CPU_V7) += head-v7.o +AFLAGS_head-v7.o :=-Wa,-march=armv7-a +obj-$(CONFIG_SMP) += platsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o +obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o endif # i.MX5 based machines diff --git a/trunk/arch/arm/mach-imx/clk-imx21.c b/trunk/arch/arm/mach-imx/clk-imx21.c index cf65148bc519..ea13e61bd5f3 100644 --- a/trunk/arch/arm/mach-imx/clk-imx21.c +++ b/trunk/arch/arm/mach-imx/clk-imx21.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-imx/clk-imx25.c b/trunk/arch/arm/mach-imx/clk-imx25.c index d20d4795f4ea..fdd8cc87c9fe 100644 --- a/trunk/arch/arm/mach-imx/clk-imx25.c +++ b/trunk/arch/arm/mach-imx/clk-imx25.c @@ -222,8 +222,10 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0"); clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0"); clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0"); - clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1"); + clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0"); + clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0"); + clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1"); + clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1"); clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0"); clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0"); clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0"); @@ -241,6 +243,6 @@ int __init mx25_clocks_init(void) clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma"); clk_register_clkdev(clk[iim_ipg], "iim", NULL); - mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1); + mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54); return 0; } diff --git a/trunk/arch/arm/mach-imx/clk-imx27.c b/trunk/arch/arm/mach-imx/clk-imx27.c index f69ca4680049..7aa6313fb167 100644 --- a/trunk/arch/arm/mach-imx/clk-imx27.c +++ b/trunk/arch/arm/mach-imx/clk-imx27.c @@ -223,7 +223,7 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[per3_gate], "per", "imx-fb.0"); clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0"); clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx-fb.0"); - clk_register_clkdev(clk[csi_ahb_gate], "ahb", "mx2-camera.0"); + clk_register_clkdev(clk[csi_ahb_gate], NULL, "mx2-camera.0"); clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc"); clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc"); clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc"); @@ -250,10 +250,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx-i2c.1"); clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0"); clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad"); - clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "mx2-camera.0"); - clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "mx2-camera.0"); - clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0"); - clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0"); + clk_register_clkdev(clk[emma_ahb_gate], "ahb", "imx-emma"); + clk_register_clkdev(clk[emma_ipg_gate], "ipg", "imx-emma"); clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL); clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL); clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL); diff --git a/trunk/arch/arm/mach-imx/clk-imx31.c b/trunk/arch/arm/mach-imx/clk-imx31.c index 1253af2d9971..8e19e70f90f9 100644 --- a/trunk/arch/arm/mach-imx/clk-imx31.c +++ b/trunk/arch/arm/mach-imx/clk-imx31.c @@ -130,7 +130,7 @@ int __init mx31_clocks_init(unsigned long fref) clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0"); clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); - clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); + clk_register_clkdev(clk[kpp_gate], "kpp", NULL); clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); diff --git a/trunk/arch/arm/mach-imx/clk-imx35.c b/trunk/arch/arm/mach-imx/clk-imx35.c index 65fb8bcd86cb..c6422fb10bae 100644 --- a/trunk/arch/arm/mach-imx/clk-imx35.c +++ b/trunk/arch/arm/mach-imx/clk-imx35.c @@ -230,8 +230,10 @@ int __init mx35_clocks_init() clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); - clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); - clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); + clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0"); + clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0"); + clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1"); + clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1"); /* i.mx35 has the i.mx21 type uart */ clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); diff --git a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c index f89c4403a922..f6086693ebd2 100644 --- a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c @@ -39,10 +39,10 @@ static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", }; static const char *emi_slow_sel[] = { "main_bus", "ahb", }; static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", }; static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", }; -static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", }; +static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", }; static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", }; static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", }; -static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", }; +static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", }; static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", }; static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", }; static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", }; @@ -303,7 +303,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk_prepare_enable(clk[aips_tz2]); /* fec */ clk_prepare_enable(clk[spba]); clk_prepare_enable(clk[emi_fast_gate]); /* fec */ - clk_prepare_enable(clk[emi_slow_gate]); /* eim */ clk_prepare_enable(clk[tmax1]); clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */ diff --git a/trunk/arch/arm/mach-imx/clk-imx6q.c b/trunk/arch/arm/mach-imx/clk-imx6q.c index 4233d9e3531d..ea89520b6e22 100644 --- a/trunk/arch/arm/mach-imx/clk-imx6q.c +++ b/trunk/arch/arm/mach-imx/clk-imx6q.c @@ -152,7 +152,7 @@ enum mx6q_clks { ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3, usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg, pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg, - ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, clk_max }; @@ -288,10 +288,8 @@ int __init mx6q_clocks_init(void) clk[gpu3d_shader] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); clk[ipu1_podf] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); clk[ipu2_podf] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); - clk[ldb_di0_div_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); - clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1); - clk[ldb_di1_div_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); - clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1); + clk[ldb_di0_podf] = imx_clk_divider("ldb_di0_podf", "ldb_di0_sel", base + 0x20, 10, 1); + clk[ldb_di1_podf] = imx_clk_divider("ldb_di1_podf", "ldb_di1_sel", base + 0x20, 11, 1); clk[ipu1_di0_pre] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); clk[ipu1_di1_pre] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); clk[ipu2_di0_pre] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); diff --git a/trunk/arch/arm/mach-imx/clk-pllv1.c b/trunk/arch/arm/mach-imx/clk-pllv1.c index 02be73178912..2d856f9ccf59 100644 --- a/trunk/arch/arm/mach-imx/clk-pllv1.c +++ b/trunk/arch/arm/mach-imx/clk-pllv1.c @@ -6,7 +6,7 @@ #include #include #include - +#include #include "clk.h" /** @@ -29,53 +29,8 @@ static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_pllv1 *pll = to_clk_pllv1(hw); - long long ll; - int mfn_abs; - unsigned int mfi, mfn, mfd, pd; - u32 reg; - unsigned long rate; - - reg = readl(pll->base); - - /* - * Get the resulting clock rate from a PLL register value and the input - * frequency. PLLs with this register layout can be found on i.MX1, - * i.MX21, i.MX27 and i,MX31 - * - * mfi + mfn / (mfd + 1) - * f = 2 * f_ref * -------------------- - * pd + 1 - */ - - mfi = (reg >> 10) & 0xf; - mfn = reg & 0x3ff; - mfd = (reg >> 16) & 0x3ff; - pd = (reg >> 26) & 0xf; - - mfi = mfi <= 5 ? 5 : mfi; - - mfn_abs = mfn; - - /* - * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit - * 2's complements number - */ - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) - mfn_abs = 0x400 - mfn; - - rate = parent_rate * 2; - rate /= pd + 1; - - ll = (unsigned long long)rate * mfn_abs; - - do_div(ll, mfd + 1); - - if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200) - ll = -ll; - - ll = (rate * mfi) + ll; - return ll; + return mxc_decode_pll(readl(pll->base), parent_rate); } struct clk_ops clk_pllv1_ops = { diff --git a/trunk/arch/arm/mach-imx/clk.c b/trunk/arch/arm/mach-imx/clk.c deleted file mode 100644 index f5e8be8e7f11..000000000000 --- a/trunk/arch/arm/mach-imx/clk.c +++ /dev/null @@ -1,3 +0,0 @@ -#include - -DEFINE_SPINLOCK(imx_ccm_lock); diff --git a/trunk/arch/arm/mach-imx/clk.h b/trunk/arch/arm/mach-imx/clk.h index 5f2d8acca25f..1bf64fe2523c 100644 --- a/trunk/arch/arm/mach-imx/clk.h +++ b/trunk/arch/arm/mach-imx/clk.h @@ -3,8 +3,7 @@ #include #include - -extern spinlock_t imx_ccm_lock; +#include struct clk *imx_clk_pllv1(const char *name, const char *parent, void __iomem *base); diff --git a/trunk/arch/arm/mach-imx/headsmp.S b/trunk/arch/arm/mach-imx/head-v7.S similarity index 100% rename from trunk/arch/arm/mach-imx/headsmp.S rename to trunk/arch/arm/mach-imx/head-v7.S diff --git a/trunk/arch/arm/mach-imx/hotplug.c b/trunk/arch/arm/mach-imx/hotplug.c index f8f7437c83b8..20ed2d56c1af 100644 --- a/trunk/arch/arm/mach-imx/hotplug.c +++ b/trunk/arch/arm/mach-imx/hotplug.c @@ -42,6 +42,22 @@ static inline void cpu_enter_lowpower(void) : "cc"); } +static inline void cpu_leave_lowpower(void) +{ + unsigned int v; + + asm volatile( + "mrc p15, 0, %0, c1, c0, 0\n" + " orr %0, %0, %1\n" + " mcr p15, 0, %0, c1, c0, 0\n" + " mrc p15, 0, %0, c1, c0, 1\n" + " orr %0, %0, %2\n" + " mcr p15, 0, %0, c1, c0, 1\n" + : "=&r" (v) + : "Ir" (CR_C), "Ir" (0x40) + : "cc"); +} + /* * platform-specific code to shutdown a CPU * @@ -51,10 +67,11 @@ void platform_cpu_die(unsigned int cpu) { cpu_enter_lowpower(); imx_enable_cpu(cpu, false); + cpu_do_idle(); + cpu_leave_lowpower(); - /* spin here until hardware takes it down */ - while (1) - ; + /* We should never return from idle */ + panic("cpu %d unexpectedly exit from shutdown\n", cpu); } int platform_cpu_disable(unsigned int cpu) diff --git a/trunk/arch/arm/mach-imx/mach-armadillo5x0.c b/trunk/arch/arm/mach-imx/mach-armadillo5x0.c index 5985ed1b8c98..2c6ab3273f9e 100644 --- a/trunk/arch/arm/mach-imx/mach-armadillo5x0.c +++ b/trunk/arch/arm/mach-imx/mach-armadillo5x0.c @@ -526,8 +526,7 @@ static void __init armadillo5x0_init(void) imx31_add_mxc_nand(&armadillo5x0_nand_board_info); /* set NAND page size to 2k if not configured via boot mode pins */ - __raw_writel(__raw_readl(mx3_ccm_base + MXC_CCM_RCSR) | - (1 << 30), mx3_ccm_base + MXC_CCM_RCSR); + __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR); /* RTC */ /* Get RTC IRQ and register the chip */ diff --git a/trunk/arch/arm/mach-imx/mach-imx6q.c b/trunk/arch/arm/mach-imx/mach-imx6q.c index 045b3f6a387d..5ec0608f2a76 100644 --- a/trunk/arch/arm/mach-imx/mach-imx6q.c +++ b/trunk/arch/arm/mach-imx/mach-imx6q.c @@ -71,7 +71,7 @@ void imx6q_restart(char mode, const char *cmd) /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { - if (IS_BUILTIN(CONFIG_PHYLIB)) { + if (IS_ENABLED(CONFIG_PHYLIB)) { /* min rx data delay */ phy_write(phydev, 0x0b, 0x8105); phy_write(phydev, 0x0c, 0x0000); @@ -112,7 +112,7 @@ static void __init imx6q_sabrelite_cko1_setup(void) static void __init imx6q_sabrelite_init(void) { - if (IS_BUILTIN(CONFIG_PHYLIB)) + if (IS_ENABLED(CONFIG_PHYLIB)) phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, ksz9021rn_phy_fixup); imx6q_sabrelite_cko1_setup(); diff --git a/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c b/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c index 0330078ff788..5d08533ab2c7 100644 --- a/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c +++ b/trunk/arch/arm/mach-imx/mach-kzm_arm11_01.c @@ -36,6 +36,7 @@ #include #include +#include #include #include #include @@ -258,13 +259,13 @@ static void __init kzm_board_init(void) */ static struct map_desc kzm_io_desc[] __initdata = { { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, + .virtual = MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = MX31_CS4_SIZE, .type = MT_DEVICE }, { - .virtual = (unsigned long)MX31_CS5_BASE_ADDR_VIRT, + .virtual = MX31_CS5_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR), .length = MX31_CS5_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-imx/mach-mx31ads.c b/trunk/arch/arm/mach-imx/mach-mx31ads.c index e774b07f48d3..d37f4809c556 100644 --- a/trunk/arch/arm/mach-imx/mach-mx31ads.c +++ b/trunk/arch/arm/mach-imx/mach-mx31ads.c @@ -540,7 +540,7 @@ static void __init mxc_init_audio(void) */ static struct map_desc mx31ads_io_desc[] __initdata = { { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, + .virtual = MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = CS4_CS8900_MMIO_START, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-imx/mach-mx31lite.c b/trunk/arch/arm/mach-imx/mach-mx31lite.c index ef57cff5abfb..c8785b39eaed 100644 --- a/trunk/arch/arm/mach-imx/mach-mx31lite.c +++ b/trunk/arch/arm/mach-imx/mach-mx31lite.c @@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = { */ static struct map_desc mx31lite_io_desc[] __initdata = { { - .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT, + .virtual = MX31_CS4_BASE_ADDR_VIRT, .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR), .length = MX31_CS4_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-integrator/core.c b/trunk/arch/arm/mach-integrator/core.c index a432d4325f89..ebf680bebdf2 100644 --- a/trunk/arch/arm/mach-integrator/core.c +++ b/trunk/arch/arm/mach-integrator/core.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -95,8 +94,8 @@ arch_initcall(integrator_init); * UART0 7 6 * UART1 5 4 */ -#define SC_CTRLC __io_address(INTEGRATOR_SC_CTRLC) -#define SC_CTRLS __io_address(INTEGRATOR_SC_CTRLS) +#define SC_CTRLC IO_ADDRESS(INTEGRATOR_SC_CTRLC) +#define SC_CTRLS IO_ADDRESS(INTEGRATOR_SC_CTRLS) static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl) { diff --git a/trunk/arch/arm/mach-integrator/cpu.c b/trunk/arch/arm/mach-integrator/cpu.c index 590c192cdf4d..fbb457779895 100644 --- a/trunk/arch/arm/mach-integrator/cpu.c +++ b/trunk/arch/arm/mach-integrator/cpu.c @@ -25,10 +25,10 @@ static struct cpufreq_driver integrator_driver; -#define CM_ID __io_address(INTEGRATOR_HDR_ID) -#define CM_OSC __io_address(INTEGRATOR_HDR_OSC) -#define CM_STAT __io_address(INTEGRATOR_HDR_STAT) -#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK) +#define CM_ID IO_ADDRESS(INTEGRATOR_HDR_ID) +#define CM_OSC IO_ADDRESS(INTEGRATOR_HDR_OSC) +#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT) +#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK) static const struct icst_params lclk_params = { .ref = 24000000, diff --git a/trunk/arch/arm/mach-integrator/include/mach/io.h b/trunk/arch/arm/mach-integrator/include/mach/io.h new file mode 100644 index 000000000000..8de70de3dd0a --- /dev/null +++ b/trunk/arch/arm/mach-integrator/include/mach/io.h @@ -0,0 +1,33 @@ +/* + * arch/arm/mach-integrator/include/mach/io.h + * + * Copyright (C) 1999 ARM Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +/* + * WARNING: this has to mirror definitions in platform.h + */ +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_CONFIG_VADDR 0xec000000 +#define PCI_V3_VADDR 0xed000000 +#define PCI_IO_VADDR 0xee000000 + +#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) + +#endif diff --git a/trunk/arch/arm/mach-integrator/include/mach/platform.h b/trunk/arch/arm/mach-integrator/include/mach/platform.h index 4c0347526851..ec467baade09 100644 --- a/trunk/arch/arm/mach-integrator/include/mach/platform.h +++ b/trunk/arch/arm/mach-integrator/include/mach/platform.h @@ -324,10 +324,6 @@ */ #define PHYS_PCI_V3_BASE 0x62000000 -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_CONFIG_VADDR 0xec000000 -#define PCI_V3_VADDR 0xed000000 - /* ------------------------------------------------------------------------ * Integrator Interrupt Controllers * ------------------------------------------------------------------------ diff --git a/trunk/arch/arm/mach-integrator/integrator_ap.c b/trunk/arch/arm/mach-integrator/integrator_ap.c index 2215d96cd735..7b1055c8e0b9 100644 --- a/trunk/arch/arm/mach-integrator/integrator_ap.c +++ b/trunk/arch/arm/mach-integrator/integrator_ap.c @@ -50,7 +50,6 @@ #include #include #include -#include #include #include @@ -74,7 +73,7 @@ * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M) * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M) * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k) - * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) + * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M) * ef000000 Cache flush * f1000000 10000000 Core module registers * f1100000 11000000 System controller registers @@ -134,20 +133,25 @@ static struct map_desc ap_io_desc[] __initdata = { .length = SZ_4K, .type = MT_DEVICE }, { - .virtual = (unsigned long)PCI_MEMORY_VADDR, + .virtual = PCI_MEMORY_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = (unsigned long)PCI_CONFIG_VADDR, + .virtual = PCI_CONFIG_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE), .length = SZ_16M, .type = MT_DEVICE }, { - .virtual = (unsigned long)PCI_V3_VADDR, + .virtual = PCI_V3_VADDR, .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE), .length = SZ_64K, .type = MT_DEVICE + }, { + .virtual = PCI_IO_VADDR, + .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE), + .length = SZ_64K, + .type = MT_DEVICE } }; @@ -155,7 +159,6 @@ static void __init ap_map_io(void) { iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); vga_base = PCI_MEMORY_VADDR; - pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE)); } #define INTEGRATOR_SC_VALID_INT 0x003fffff @@ -314,9 +317,9 @@ static void __init ap_init(void) /* * Where is the timer (VA)? */ -#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) -#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) -#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) +#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE) +#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE) +#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE) static unsigned long timer_reload; @@ -453,7 +456,7 @@ static void __init ap_init_timer(void) clk = clk_get_sys("ap_timer", NULL); BUG_ON(IS_ERR(clk)); - clk_prepare_enable(clk); + clk_enable(clk); rate = clk_get_rate(clk); writel(0, TIMER0_VA_BASE + TIMER_CTRL); diff --git a/trunk/arch/arm/mach-integrator/integrator_cp.c b/trunk/arch/arm/mach-integrator/integrator_cp.c index 3df5fc369361..82d5c837cc74 100644 --- a/trunk/arch/arm/mach-integrator/integrator_cp.c +++ b/trunk/arch/arm/mach-integrator/integrator_cp.c @@ -59,7 +59,7 @@ #define INTCP_ETH_SIZE 0x10 -#define INTCP_VA_CTRL_BASE __io_address(INTEGRATOR_CP_CTL_BASE) +#define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE) #define INTCP_FLASHPROG 0x04 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0) #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1) @@ -265,8 +265,8 @@ static struct platform_device *intcp_devs[] __initdata = { */ static unsigned int mmc_status(struct device *dev) { - unsigned int status = readl(__io_address(0xca000000 + 4)); - writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8)); + unsigned int status = readl(IO_ADDRESS(0xca000000 + 4)); + writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8)); return status & 8; } diff --git a/trunk/arch/arm/mach-integrator/pci_v3.c b/trunk/arch/arm/mach-integrator/pci_v3.c index bbeca59df66b..b866880e82ac 100644 --- a/trunk/arch/arm/mach-integrator/pci_v3.c +++ b/trunk/arch/arm/mach-integrator/pci_v3.c @@ -41,61 +41,61 @@ /* * The V3 PCI interface chip in Integrator provides several windows from * local bus memory into the PCI memory areas. Unfortunately, there - * are not really enough windows for our usage, therefore we reuse + * are not really enough windows for our usage, therefore we reuse * one of the windows for access to PCI configuration space. The * memory map is as follows: - * + * * Local Bus Memory Usage - * + * * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable * 60000000 - 60FFFFFF PCI IO. 16M * 61000000 - 61FFFFFF PCI Configuration. 16M - * + * * There are three V3 windows, each described by a pair of V3 registers. * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2. * Base0 and Base1 can be used for any type of PCI memory access. Base2 * can be used either for PCI I/O or for I20 accesses. By default, uHAL * uses this only for PCI IO space. - * + * * Normally these spaces are mapped using the following base registers: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF - * + * * This means that I20 and PCI configuration space accesses will fail. - * When PCI configuration accesses are needed (via the uHAL PCI + * When PCI configuration accesses are needed (via the uHAL PCI * configuration space primitives) we must remap the spaces as follows: - * + * * Usage Local Bus Memory Base/Map registers used - * + * * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1 - * + * * To make this work, the code depends on overlapping windows working. - * The V3 chip translates an address by checking its range within + * The V3 chip translates an address by checking its range within * each of the BASE/MAP pairs in turn (in ascending register number * order). It will use the first matching pair. So, for example, * if the same address is mapped by both LB_BASE0/LB_MAP0 and - * LB_BASE1/LB_MAP1, the V3 will use the translation from + * LB_BASE1/LB_MAP1, the V3 will use the translation from * LB_BASE0/LB_MAP0. - * + * * To allow PCI Configuration space access, the code enlarges the * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can * be remapped for use by configuration cycles. - * - * At the end of the PCI Configuration space accesses, + * + * At the end of the PCI Configuration space accesses, * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to * reveal the now restored LB_BASE1/LB_MAP1 window. - * + * * NOTE: We do not set up I2O mapping. I suspect that this is only * for an intelligent (target) device. Using I2O disables most of * the mappings into PCI memory. @@ -127,8 +127,8 @@ * * returns: configuration address to play on the PCI bus * - * To generate the appropriate PCI configuration cycles in the PCI - * configuration address space, you present the V3 with the following pattern + * To generate the appropriate PCI configuration cycles in the PCI + * configuration address space, you present the V3 with the following pattern * (which is very nearly a type 1 (except that the lower two bits are 00 and * not 01). In order for this mapping to work you need to set up one of * the local to PCI aperatures to 16Mbytes in length translating to @@ -138,7 +138,7 @@ * * Type 0: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0| @@ -150,7 +150,7 @@ * * Type 1: * - * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 + * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1| @@ -161,7 +161,7 @@ * 15:11 Device number (5 bits) * 10:8 function number * 7:2 register number - * + * */ static DEFINE_RAW_SPINLOCK(v3_lock); @@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock); #undef V3_LB_BASE_PREFETCH #define V3_LB_BASE_PREFETCH 0 -static void __iomem *v3_open_config_window(struct pci_bus *bus, +static unsigned long v3_open_config_window(struct pci_bus *bus, unsigned int devfn, int offset) { unsigned int address, mapaddress, busnr; @@ -280,7 +280,7 @@ static void v3_close_config_window(void) static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val) { - void __iomem *addr; + unsigned long addr; unsigned long flags; u32 v; @@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where, static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - void __iomem *addr; + unsigned long addr; unsigned long flags; raw_spin_lock_irqsave(&v3_lock, flags); @@ -374,9 +374,12 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) } /* + * the IO resource for this bus * the mem resource for this bus * the prefetch mem resource for this bus */ + pci_add_resource_offset(&sys->resources, + &ioport_resource, sys->io_offset); pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset); pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset); @@ -388,9 +391,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys) * means I can't get additional information on the reason for the pm2fb * problems. I suppose I'll just have to mind-meld with the machine. ;) */ -#define SC_PCI __io_address(INTEGRATOR_SC_PCIENABLE) -#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20) -#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24) +#define SC_PCI IO_ADDRESS(INTEGRATOR_SC_PCIENABLE) +#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20) +#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24) static int v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs) @@ -495,6 +498,7 @@ void __init pci_v3_preinit(void) unsigned int temp; int ret; + pcibios_min_io = 0x6000; pcibios_min_mem = 0x00100000; /* diff --git a/trunk/drivers/iio/common/hid-sensors/hid-sensor-trigger.h b/trunk/arch/arm/mach-iop13xx/include/mach/io.h similarity index 62% rename from trunk/drivers/iio/common/hid-sensors/hid-sensor-trigger.h rename to trunk/arch/arm/mach-iop13xx/include/mach/io.h index fd982971b1b8..f13188518025 100644 --- a/trunk/drivers/iio/common/hid-sensors/hid-sensor-trigger.h +++ b/trunk/arch/arm/mach-iop13xx/include/mach/io.h @@ -1,6 +1,6 @@ /* - * HID Sensors Driver - * Copyright (c) 2012, Intel Corporation. + * iop13xx custom ioremap implementation + * Copyright (c) 2005-2006, Intel Corporation. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -12,15 +12,17 @@ * more details. * * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * this program; if not, write to the Free Software Foundation, Inc., 59 Temple + * Place - Suite 330, Boston, MA 02111-1307 USA. * */ -#ifndef _HID_SENSOR_TRIGGER_H -#define _HID_SENSOR_TRIGGER_H +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H -int hid_sensor_setup_trigger(struct iio_dev *indio_dev, const char *name, - struct hid_sensor_iio_common *attrb); -void hid_sensor_remove_trigger(struct iio_dev *indio_dev); +#define IO_SPACE_LIMIT 0xffffffff + +#define __io(a) __iop13xx_io(a) + +extern void __iomem * __iop13xx_io(unsigned long io_addr); #endif diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h index 7480f58267aa..e190dcd7d72d 100644 --- a/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h +++ b/trunk/arch/arm/mach-iop13xx/include/mach/iop13xx.h @@ -69,11 +69,21 @@ extern unsigned long get_iop_tick_rate(void); * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window * * IO MAP - * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window - * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window + * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window + * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window */ +#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL +#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL #define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */ +#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL +#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ + IOP13XX_PCIX_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ + IOP13XX_PCIX_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PCIX_LOWER_IO_PA\ + - IOP13XX_PCIX_LOWER_IO_VA)) #define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL #define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL @@ -93,8 +103,20 @@ extern unsigned long get_iop_tick_rate(void); IOP13XX_PCIX_LOWER_MEM_BA) /* PCI-E ranges */ +#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL #define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL -#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */ +#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL +#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */ +#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL +#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ + IOP13XX_PCIE_IO_WINDOW_SIZE - 1) +#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PCIE_LOWER_IO_PA\ + - IOP13XX_PCIE_LOWER_IO_VA)) #define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL #define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL @@ -126,16 +148,18 @@ extern unsigned long get_iop_tick_rate(void); * IOP13XX chipset registers */ #define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */ -#define IOP13XX_PMMR_VIRT_MEM_BASE (void __iomem *)(0xfee80000UL) /* PMMR phys. address */ +#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */ #define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000 #define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) #define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\ IOP13XX_PMMR_MEM_WINDOW_SIZE - 1) -#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\ - + IOP13XX_PMMR_PHYS_MEM_BASE) -#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\ - + IOP13XX_PMMR_VIRT_MEM_BASE) +#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\ + (IOP13XX_PMMR_PHYS_MEM_BASE\ + - IOP13XX_PMMR_VIRT_MEM_BASE)) +#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ + (IOP13XX_PMMR_PHYS_MEM_BASE\ + - IOP13XX_PMMR_VIRT_MEM_BASE)) #define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) #define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg)) @@ -145,10 +169,10 @@ extern unsigned long get_iop_tick_rate(void); #define IOP13XX_PMMR_SIZE 0x00080000 /*=================== Defines for Platform Devices =====================*/ -#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300) -#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340) -#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300) -#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340) +#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300) +#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340) +#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300) +#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340) #define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500) #define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520) diff --git a/trunk/arch/arm/mach-iop13xx/include/mach/memory.h b/trunk/arch/arm/mach-iop13xx/include/mach/memory.h index 7c032d0ab24a..1afa99ef97fa 100644 --- a/trunk/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/trunk/arch/arm/mach-iop13xx/include/mach/memory.h @@ -16,12 +16,12 @@ #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE) #define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE) -static inline dma_addr_t __virt_to_lbus(void __iomem *x) +static inline dma_addr_t __virt_to_lbus(unsigned long x) { return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE; } -static inline void __iomem *__lbus_to_virt(dma_addr_t x) +static inline unsigned long __lbus_to_virt(dma_addr_t x) { return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE; } @@ -38,23 +38,23 @@ static inline void __iomem *__lbus_to_virt(dma_addr_t x) #define __arch_dma_to_virt(dev, addr) \ ({ \ - void * __virt; \ + unsigned long __virt; \ dma_addr_t __dma = addr; \ if (is_lbus_device(dev) && __is_lbus_dma(__dma)) \ __virt = __lbus_to_virt(__dma); \ else \ - __virt = (void *)__phys_to_virt(__dma); \ - __virt; \ + __virt = __phys_to_virt(__dma); \ + (void *)__virt; \ }) #define __arch_virt_to_dma(dev, addr) \ ({ \ - void * __virt = addr; \ + unsigned long __virt = (unsigned long)addr; \ dma_addr_t __dma; \ if (is_lbus_device(dev) && __is_lbus_virt(__virt)) \ __dma = __virt_to_lbus(__virt); \ else \ - __dma = __virt_to_phys((unsigned long)__virt); \ + __dma = __virt_to_phys(__virt); \ __dma; \ }) diff --git a/trunk/arch/arm/mach-iop13xx/io.c b/trunk/arch/arm/mach-iop13xx/io.c index 183dc8b5511b..3c364198db9c 100644 --- a/trunk/arch/arm/mach-iop13xx/io.c +++ b/trunk/arch/arm/mach-iop13xx/io.c @@ -23,6 +23,25 @@ #include "pci.h" +void * __iomem __iop13xx_io(unsigned long io_addr) +{ + void __iomem * io_virt; + + switch (io_addr) { + case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: + io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr); + break; + case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: + io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr); + break; + default: + BUG(); + } + + return io_virt; +} +EXPORT_SYMBOL(__iop13xx_io); + static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, size_t size, unsigned int mtype, void *caller) { @@ -33,14 +52,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, if (unlikely(!iop13xx_atux_mem_base)) retval = NULL; else - retval = (iop13xx_atux_mem_base + + retval = (void *)(iop13xx_atux_mem_base + (cookie - IOP13XX_PCIX_LOWER_MEM_RA)); break; case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA: if (unlikely(!iop13xx_atue_mem_base)) retval = NULL; else - retval = (iop13xx_atue_mem_base + + retval = (void *)(iop13xx_atue_mem_base + (cookie - IOP13XX_PCIE_LOWER_MEM_RA)); break; case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA: @@ -48,8 +67,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, (cookie - IOP13XX_PBI_LOWER_MEM_RA), size, mtype, __builtin_return_address(0)); break; + case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA: + retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie); + break; + case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA: + retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie); + break; case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA: - retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie); + retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie); break; default: retval = __arm_ioremap_caller(cookie, size, mtype, @@ -74,7 +99,9 @@ static void __iop13xx_iounmap(volatile void __iomem *addr) goto skip; switch ((u32) addr) { - case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA: + case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA: + case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA: + case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA: goto skip; } __iounmap(addr); diff --git a/trunk/arch/arm/mach-iop13xx/pci.c b/trunk/arch/arm/mach-iop13xx/pci.c index 9082b84aeebb..861cb12ef436 100644 --- a/trunk/arch/arm/mach-iop13xx/pci.c +++ b/trunk/arch/arm/mach-iop13xx/pci.c @@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */ u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */ static struct pci_bus *pci_bus_atux = 0; static struct pci_bus *pci_bus_atue = 0; -void __iomem *iop13xx_atue_mem_base; -void __iomem *iop13xx_atux_mem_base; +u32 iop13xx_atue_mem_base; +u32 iop13xx_atux_mem_base; size_t iop13xx_atue_mem_size; size_t iop13xx_atux_mem_size; @@ -88,7 +88,8 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atux_mem_base = __arm_ioremap_pfn( + iop13xx_atux_mem_base = + (u32) __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA) , 0, iop13xx_atux_mem_size, MT_DEVICE); if (!iop13xx_atux_mem_base) { @@ -98,7 +99,7 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atux_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", __func__, atu, iop13xx_atux_mem_size, iop13xx_atux_mem_base); break; @@ -113,7 +114,8 @@ void iop13xx_map_pci_memory(void) } if (end) { - iop13xx_atue_mem_base = __arm_ioremap_pfn( + iop13xx_atue_mem_base = + (u32) __arm_ioremap_pfn( __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA) , 0, iop13xx_atue_mem_size, MT_DEVICE); if (!iop13xx_atue_mem_base) { @@ -123,13 +125,13 @@ void iop13xx_map_pci_memory(void) } } else iop13xx_atue_mem_size = 0; - PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n", + PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n", __func__, atu, iop13xx_atue_mem_size, iop13xx_atue_mem_base); break; } - printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n", + printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n", atu ? "ATUE" : "ATUX", (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) / SZ_1M, @@ -968,6 +970,7 @@ void __init iop13xx_pci_init(void) __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); /* Setup the Min Address for PCI memory... */ + pcibios_min_io = 0; pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA; /* if Linux is given control of an ATU @@ -1000,7 +1003,7 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) if (nr > 1) return 0; - res = kzalloc(sizeof(struct resource), GFP_KERNEL); + res = kcalloc(2, sizeof(struct resource), GFP_KERNEL); if (!res) panic("PCI: unable to alloc resources"); @@ -1039,13 +1042,17 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) << IOP13XX_ATUX_PCIXSR_FUNC_NUM; __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); - pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA); + res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET; + res[0].end = IOP13XX_PCIX_UPPER_IO_PA; + res[0].name = "IQ81340 ATUX PCI I/O Space"; + res[0].flags = IORESOURCE_IO; - res->start = IOP13XX_PCIX_LOWER_MEM_RA; - res->end = IOP13XX_PCIX_UPPER_MEM_RA; - res->name = "IQ81340 ATUX PCI Memory Space"; - res->flags = IORESOURCE_MEM; + res[1].start = IOP13XX_PCIX_LOWER_MEM_RA; + res[1].end = IOP13XX_PCIX_UPPER_MEM_RA; + res[1].name = "IQ81340 ATUX PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET; + sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA; break; case IOP13XX_INIT_ATU_ATUE: /* Note: the function number field in the PCSR is ro */ @@ -1056,13 +1063,17 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) __raw_writel(pcsr, IOP13XX_ATUE_PCSR); - pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA); + res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET; + res[0].end = IOP13XX_PCIE_UPPER_IO_PA; + res[0].name = "IQ81340 ATUE PCI I/O Space"; + res[0].flags = IORESOURCE_IO; - res->start = IOP13XX_PCIE_LOWER_MEM_RA; - res->end = IOP13XX_PCIE_UPPER_MEM_RA; - res->name = "IQ81340 ATUE PCI Memory Space"; - res->flags = IORESOURCE_MEM; + res[1].start = IOP13XX_PCIE_LOWER_MEM_RA; + res[1].end = IOP13XX_PCIE_UPPER_MEM_RA; + res[1].name = "IQ81340 ATUE PCI Memory Space"; + res[1].flags = IORESOURCE_MEM; sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET; + sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA; sys->map_irq = iop13xx_pcie_map_irq; break; default: @@ -1070,9 +1081,11 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys) return 0; } - request_resource(&iomem_resource, res); + request_resource(&ioport_resource, &res[0]); + request_resource(&iomem_resource, &res[1]); - pci_add_resource_offset(&sys->resources, res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset); + pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset); return 1; } diff --git a/trunk/arch/arm/mach-iop13xx/pci.h b/trunk/arch/arm/mach-iop13xx/pci.h index d45a80b3080e..c70cf5b41e31 100644 --- a/trunk/arch/arm/mach-iop13xx/pci.h +++ b/trunk/arch/arm/mach-iop13xx/pci.h @@ -1,6 +1,6 @@ #include -extern void __iomem *iop13xx_atue_mem_base; -extern void __iomem *iop13xx_atux_mem_base; +extern u32 iop13xx_atue_mem_base; +extern u32 iop13xx_atux_mem_base; extern size_t iop13xx_atue_mem_size; extern size_t iop13xx_atux_mem_size; diff --git a/trunk/arch/arm/mach-iop13xx/setup.c b/trunk/arch/arm/mach-iop13xx/setup.c index 3181f61ea63e..daabb1fa6c2c 100644 --- a/trunk/arch/arm/mach-iop13xx/setup.c +++ b/trunk/arch/arm/mach-iop13xx/setup.c @@ -36,10 +36,20 @@ */ static struct map_desc iop13xx_std_desc[] __initdata = { { /* mem mapped registers */ - .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE, + .virtual = IOP13XX_PMMR_VIRT_MEM_BASE, .pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE), .length = IOP13XX_PMMR_SIZE, .type = MT_DEVICE, + }, { /* PCIE IO space */ + .virtual = IOP13XX_PCIE_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA), + .length = IOP13XX_PCIX_IO_WINDOW_SIZE, + .type = MT_DEVICE, + }, { /* PCIX IO space */ + .virtual = IOP13XX_PCIX_LOWER_IO_VA, + .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA), + .length = IOP13XX_PCIX_IO_WINDOW_SIZE, + .type = MT_DEVICE, }, }; @@ -71,8 +81,8 @@ static struct resource iop13xx_uart1_resources[] = { static struct plat_serial8250_port iop13xx_uart0_data[] = { { - .membase = IOP13XX_UART0_VIRT, - .mapbase = IOP13XX_UART0_PHYS, + .membase = (char*)(IOP13XX_UART0_VIRT), + .mapbase = (IOP13XX_UART0_PHYS), .irq = IRQ_IOP13XX_UART0, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, @@ -84,8 +94,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = { static struct plat_serial8250_port iop13xx_uart1_data[] = { { - .membase = IOP13XX_UART1_VIRT, - .mapbase = IOP13XX_UART1_PHYS, + .membase = (char*)(IOP13XX_UART1_VIRT), + .mapbase = (IOP13XX_UART1_PHYS), .irq = IRQ_IOP13XX_UART1, .uartclk = IOP13XX_UART_XTAL, .regshift = 2, diff --git a/trunk/arch/arm/mach-iop32x/glantank.c b/trunk/arch/arm/mach-iop32x/glantank.c index 02e20c3912ba..c15a100ba779 100644 --- a/trunk/arch/arm/mach-iop32x/glantank.c +++ b/trunk/arch/arm/mach-iop32x/glantank.c @@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = { static void glantank_power_off(void) { - __raw_writeb(0x01, IOMEM(0xfe8d0004)); + __raw_writeb(0x01, 0xfe8d0004); while (1) ; diff --git a/trunk/arch/arm/mach-iop32x/include/mach/io.h b/trunk/arch/arm/mach-iop32x/include/mach/io.h new file mode 100644 index 000000000000..e2ada265bb8d --- /dev/null +++ b/trunk/arch/arm/mach-iop32x/include/mach/io.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-iop32x/include/mach/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IO_H +#define __IO_H + +#include + +#define IO_SPACE_LIMIT 0xffffffff +#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) + +#endif diff --git a/trunk/arch/arm/mach-iop33x/include/mach/io.h b/trunk/arch/arm/mach-iop33x/include/mach/io.h new file mode 100644 index 000000000000..f7c1b6595660 --- /dev/null +++ b/trunk/arch/arm/mach-iop33x/include/mach/io.h @@ -0,0 +1,19 @@ +/* + * arch/arm/mach-iop33x/include/mach/io.h + * + * Copyright (C) 2001 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __IO_H +#define __IO_H + +#include + +#define IO_SPACE_LIMIT 0xffffffff +#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p)) + +#endif diff --git a/trunk/arch/arm/mach-ixp4xx/common.c b/trunk/arch/arm/mach-ixp4xx/common.c index fdf91a160884..a9f80943d01f 100644 --- a/trunk/arch/arm/mach-ixp4xx/common.c +++ b/trunk/arch/arm/mach-ixp4xx/common.c @@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx; *************************************************************************/ static struct map_desc ixp4xx_io_desc[] __initdata = { { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */ - .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT, + .virtual = IXP4XX_PERIPHERAL_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS), .length = IXP4XX_PERIPHERAL_REGION_SIZE, .type = MT_DEVICE }, { /* Expansion Bus Config Registers */ - .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT, + .virtual = IXP4XX_EXP_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS), .length = IXP4XX_EXP_CFG_REGION_SIZE, .type = MT_DEVICE }, { /* PCI Registers */ - .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT, + .virtual = IXP4XX_PCI_CFG_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS), .length = IXP4XX_PCI_CFG_REGION_SIZE, .type = MT_DEVICE }, #ifdef CONFIG_DEBUG_LL { /* Debug UART mapping */ - .virtual = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT, + .virtual = IXP4XX_DEBUG_UART_BASE_VIRT, .pfn = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS), .length = IXP4XX_DEBUG_UART_REGION_SIZE, .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h b/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h index ebc0ba31ce85..b2ef65db0e91 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/cpu.h @@ -14,7 +14,6 @@ #ifndef __ASM_ARCH_CPU_H__ #define __ASM_ARCH_CPU_H__ -#include #include /* Processor id value in CP15 Register 0 */ @@ -38,7 +37,7 @@ static inline u32 ixp4xx_read_feature_bits(void) { - u32 val = ~__raw_readl(IXP4XX_EXP_CFG2); + u32 val = ~*IXP4XX_EXP_CFG2; if (cpu_is_ixp42x_rev_a0()) return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP | @@ -52,7 +51,7 @@ static inline u32 ixp4xx_read_feature_bits(void) static inline void ixp4xx_write_feature_bits(u32 value) { - __raw_writel(~value, IXP4XX_EXP_CFG2); + *IXP4XX_EXP_CFG2 = ~value; } #endif /* _ASM_ARCH_CPU_H */ diff --git a/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index eb68b61ce975..97c530f66e78 100644 --- a/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/trunk/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h @@ -49,21 +49,21 @@ * Expansion BUS Configuration registers */ #define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP4XX_EXP_CFG_BASE_VIRT IOMEM(0xFFBFE000) +#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFE000) #define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000) /* * PCI Config registers */ #define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFFBFF000) +#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFF000) #define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000) /* * Peripheral space */ #define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFFBEB000) +#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBEB000) #define IXP4XX_PERIPHERAL_REGION_SIZE (0x00013000) /* @@ -73,7 +73,7 @@ * aligned so that it * can be used with the low-level debug code. */ #define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000) -#define IXP4XX_DEBUG_UART_BASE_VIRT IOMEM(0xffb00000) +#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000) #define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000) #define IXP4XX_EXP_CS0_OFFSET 0x00 @@ -92,7 +92,7 @@ /* * Expansion Bus Controller registers. */ -#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) +#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) diff --git a/trunk/arch/arm/mach-kirkwood/Makefile.boot b/trunk/arch/arm/mach-kirkwood/Makefile.boot index a13299d758e1..2a576abf409b 100644 --- a/trunk/arch/arm/mach-kirkwood/Makefile.boot +++ b/trunk/arch/arm/mach-kirkwood/Makefile.boot @@ -7,8 +7,7 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb -dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6281.dtb -dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-ts219-6282.dtb +dtb-$(CONFIG_MACH_TS219_DT) += kirkwood-qnap-ts219.dtb dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb -dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb -dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb +dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb +dbt-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb diff --git a/trunk/arch/arm/mach-kirkwood/common.c b/trunk/arch/arm/mach-kirkwood/common.c index 3f7b05f30b46..c4b64adcbfce 100644 --- a/trunk/arch/arm/mach-kirkwood/common.c +++ b/trunk/arch/arm/mach-kirkwood/common.c @@ -42,6 +42,16 @@ ****************************************************************************/ static struct map_desc kirkwood_io_desc[] __initdata = { { + .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE, + .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE), + .length = KIRKWOOD_PCIE1_IO_SIZE, + .type = MT_DEVICE, + }, { .virtual = KIRKWOOD_REGS_VIRT_BASE, .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), .length = KIRKWOOD_REGS_SIZE, @@ -291,7 +301,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM, - IRQ_KIRKWOOD_GE00_ERR, 1600); + IRQ_KIRKWOOD_GE00_ERR); /* The interface forgets the MAC address assigned by u-boot if the clock is turned off, so claim the clk now. */ clk_prepare_enable(ge0); @@ -305,7 +315,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM, - IRQ_KIRKWOOD_GE01_ERR, 1600); + IRQ_KIRKWOOD_GE01_ERR); clk_prepare_enable(ge1); } @@ -507,13 +517,6 @@ void __init kirkwood_wdt_init(void) void __init kirkwood_init_early(void) { orion_time_set_base(TIMER_VIRT_BASE); - - /* - * Some Kirkwood devices allocate their coherent buffers from atomic - * context. Increase size of atomic coherent pool to make sure such - * the allocations won't fail. - */ - init_dma_coherent_pool_size(SZ_1M); } int kirkwood_tclk; diff --git a/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index be90b7d0e10b..d93359379598 100644 --- a/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/trunk/arch/arm/mach-kirkwood/db88f6281-bp-setup.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/io.h b/trunk/arch/arm/mach-kirkwood/include/mach/io.h new file mode 100644 index 000000000000..5d0ab61700d2 --- /dev/null +++ b/trunk/arch/arm/mach-kirkwood/include/mach/io.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-kirkwood/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "kirkwood.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE) + + KIRKWOOD_PCIE_IO_VIRT_BASE); +} + +#define __io(a) __io(a) + +#endif diff --git a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h index af4f0000dcef..c5b68510776b 100644 --- a/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/trunk/arch/arm/mach-kirkwood/include/mach/kirkwood.h @@ -37,12 +37,14 @@ #define KIRKWOOD_NAND_MEM_SIZE SZ_1K #define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000 -#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000 -#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K +#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000 +#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000 +#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000 +#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000 -#define KIRKWOOD_PCIE_IO_SIZE SZ_64K +#define KIRKWOOD_PCIE_IO_SIZE SZ_1M #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 #define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 diff --git a/trunk/arch/arm/mach-kirkwood/pcie.c b/trunk/arch/arm/mach-kirkwood/pcie.c index 532d8acb38f9..6e8b2efa3c35 100644 --- a/trunk/arch/arm/mach-kirkwood/pcie.c +++ b/trunk/arch/arm/mach-kirkwood/pcie.c @@ -56,7 +56,7 @@ struct pcie_port { void __iomem *base; spinlock_t conf_lock; int irq; - struct resource res; + struct resource res[2]; }; static int pcie_port_map[2]; @@ -136,13 +136,21 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp) pp->base = (void __iomem *)PCIE_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE; + /* + * IORESOURCE_IO + */ + pp->res[0].name = "PCIe 0 I/O Space"; + pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE; + pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; + /* * IORESOURCE_MEM */ - pp->res.name = "PCIe 0 MEM"; - pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE; - pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1; - pp->res.flags = IORESOURCE_MEM; + pp->res[1].name = "PCIe 0 MEM"; + pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1; + pp->res[1].flags = IORESOURCE_MEM; } static void __init pcie1_ioresources_init(struct pcie_port *pp) @@ -150,13 +158,21 @@ static void __init pcie1_ioresources_init(struct pcie_port *pp) pp->base = (void __iomem *)PCIE1_VIRT_BASE; pp->irq = IRQ_KIRKWOOD_PCIE1; + /* + * IORESOURCE_IO + */ + pp->res[0].name = "PCIe 1 I/O Space"; + pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE; + pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; + /* * IORESOURCE_MEM */ - pp->res.name = "PCIe 1 MEM"; - pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; - pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1; - pp->res.flags = IORESOURCE_MEM; + pp->res[1].name = "PCIe 1 MEM"; + pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE; + pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1; + pp->res[1].flags = IORESOURCE_MEM; } static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) @@ -181,21 +197,23 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys) case 0: kirkwood_enable_pcie_clk("0"); pcie0_ioresources_init(pp); - pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE); break; case 1: kirkwood_enable_pcie_clk("1"); pcie1_ioresources_init(pp); - pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE); break; default: panic("PCIe setup: invalid controller %d", index); } - if (request_resource(&iomem_resource, &pp->res)) + if (request_resource(&ioport_resource, &pp->res[0])) + panic("Request PCIe%d IO resource failed\n", index); + if (request_resource(&iomem_resource, &pp->res[1])) panic("Request PCIe%d Memory resource failed\n", index); - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); + sys->io_offset = 0; + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); /* * Generic PCIe unit setup. diff --git a/trunk/arch/arm/mach-ks8695/cpu.c b/trunk/arch/arm/mach-ks8695/cpu.c index ddb24222918e..7f3f24053a00 100644 --- a/trunk/arch/arm/mach-ks8695/cpu.c +++ b/trunk/arch/arm/mach-ks8695/cpu.c @@ -36,7 +36,7 @@ static struct __initdata map_desc ks8695_io_desc[] = { { - .virtual = (unsigned long)KS8695_IO_VA, + .virtual = KS8695_IO_VA, .pfn = __phys_to_pfn(KS8695_IO_PA), .length = KS8695_IO_SIZE, .type = MT_DEVICE, diff --git a/trunk/arch/arm/mach-ks8695/include/mach/hardware.h b/trunk/arch/arm/mach-ks8695/include/mach/hardware.h index 5090338c0db2..5e0c388143da 100644 --- a/trunk/arch/arm/mach-ks8695/include/mach/hardware.h +++ b/trunk/arch/arm/mach-ks8695/include/mach/hardware.h @@ -33,7 +33,7 @@ * head debug code as the initial MMU setup only deals in L1 sections. */ #define KS8695_IO_PA 0x03F00000 -#define KS8695_IO_VA IOMEM(0xF0000000) +#define KS8695_IO_VA 0xF0000000 #define KS8695_IO_SIZE SZ_1M #define KS8695_PCIMEM_PA 0x60000000 diff --git a/trunk/arch/arm/mach-ks8695/include/mach/regs-timer.h b/trunk/arch/arm/mach-ks8695/include/mach/regs-timer.h new file mode 100644 index 000000000000..e620cda99d2d --- /dev/null +++ b/trunk/arch/arm/mach-ks8695/include/mach/regs-timer.h @@ -0,0 +1,40 @@ +/* + * arch/arm/mach-ks8695/include/mach/regs-timer.h + * + * Copyright (C) 2006 Ben Dooks + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - Timer registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef KS8695_TIMER_H +#define KS8695_TIMER_H + +#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) +#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) +#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) + + +/* + * Timer registers + */ +#define KS8695_TMCON (0x00) /* Timer Control Register */ +#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ +#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ +#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ +#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ + + +/* Timer Control Register */ +#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ +#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ + +/* Timer0 Timeout Counter Register */ +#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ + + +#endif diff --git a/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h b/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h index 8879d610308a..9495cb4d701a 100644 --- a/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-ks8695/include/mach/uncompress.h @@ -19,15 +19,15 @@ static void putc(char c) { - while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE)) barrier(); - __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH); + __raw_writel(c, KS8695_UART_PA + KS8695_URTH); } static inline void flush(void) { - while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) + while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE)) barrier(); } diff --git a/trunk/arch/arm/mach-ks8695/time.c b/trunk/arch/arm/mach-ks8695/time.c index 46c84bc7792c..ec783a3070ae 100644 --- a/trunk/arch/arm/mach-ks8695/time.c +++ b/trunk/arch/arm/mach-ks8695/time.c @@ -25,98 +25,53 @@ #include #include #include -#include #include #include +#include #include #include "generic.h" -#define KS8695_TMR_OFFSET (0xF0000 + 0xE400) -#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET) -#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET) - /* - * Timer registers + * Returns number of ms since last clock interrupt. Note that interrupts + * will have been disabled by do_gettimeoffset() */ -#define KS8695_TMCON (0x00) /* Timer Control Register */ -#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */ -#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */ -#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */ -#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */ - -/* Timer Control Register */ -#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */ -#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */ - -/* Timer0 Timeout Counter Register */ -#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */ - -static void ks8695_set_mode(enum clock_event_mode mode, - struct clock_event_device *evt) -{ - u32 tmcon; - - if (mode == CLOCK_EVT_FEAT_PERIODIC) { - u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ); - u32 half = DIV_ROUND_CLOSEST(rate, 2); - - /* Disable timer 1 */ - tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - tmcon &= ~TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - - /* Both registers need to count down */ - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); - - /* Re-enable timer1 */ - tmcon |= TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - } -} - -static int ks8695_set_next_event(unsigned long cycles, - struct clock_event_device *evt) - +static unsigned long ks8695_gettimeoffset (void) { - u32 half = DIV_ROUND_CLOSEST(cycles, 2); - u32 tmcon; + unsigned long elapsed, tick2, intpending; - /* Disable timer 1 */ - tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - tmcon &= ~TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - - /* Both registers need to count down */ - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC); - writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD); - - /* Re-enable timer1 */ - tmcon |= TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); - - return 0; + /* + * Get the current number of ticks. Note that there is a race + * condition between us reading the timer and checking for an + * interrupt. We solve this by ensuring that the counter has not + * reloaded between our two reads. + */ + elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); + do { + tick2 = elapsed; + intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1); + elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD); + } while (elapsed > tick2); + + /* Convert to number of ticks expired (not remaining) */ + elapsed = (CLOCK_TICK_RATE / HZ) - elapsed; + + /* Is interrupt pending? If so, then timer has been reloaded already. */ + if (intpending) + elapsed += (CLOCK_TICK_RATE / HZ); + + /* Convert ticks to usecs */ + return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH; } -static struct clock_event_device clockevent_ks8695 = { - .name = "ks8695_t1tc", - .rating = 300, /* Reasonably fast and accurate clock event */ - .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, - .set_next_event = ks8695_set_next_event, - .set_mode = ks8695_set_mode, -}; - /* * IRQ handler for the timer. */ static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id) { - struct clock_event_device *evt = &clockevent_ks8695; - - evt->event_handler(evt); + timer_tick(); return IRQ_HANDLED; } @@ -128,22 +83,18 @@ static struct irqaction ks8695_timer_irq = { static void ks8695_timer_setup(void) { + unsigned long tmout = CLOCK_TICK_RATE / HZ; unsigned long tmcon; - /* Disable timer 0 and 1 */ - tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - tmcon &= ~TMCON_T0EN; - tmcon &= ~TMCON_T1EN; - writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON); + /* disable timer1 */ + tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); + __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); - /* - * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles - * (one on each counter) maximum 2*2^32, but the API will only - * accept up to a 32bit full word (0xFFFFFFFFU). - */ - clockevents_config_and_register(&clockevent_ks8695, - KS8695_CLOCK_RATE, 2, - 0xFFFFFFFFU); + __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC); + __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD); + + /* re-enable timer1 */ + __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON); } static void __init ks8695_timer_init (void) @@ -156,6 +107,8 @@ static void __init ks8695_timer_init (void) struct sys_timer ks8695_timer = { .init = ks8695_timer_init, + .offset = ks8695_gettimeoffset, + .resume = ks8695_timer_setup, }; void ks8695_restart(char mode, const char *cmd) @@ -166,12 +119,12 @@ void ks8695_restart(char mode, const char *cmd) soft_restart(0); /* disable timer0 */ - reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); - writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); + __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); /* enable watchdog mode */ - writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); + __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); /* re-enable timer0 */ - writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); } diff --git a/trunk/arch/arm/mach-lpc32xx/common.c b/trunk/arch/arm/mach-lpc32xx/common.c index 0d4db8c544b5..a48dc2dec485 100644 --- a/trunk/arch/arm/mach-lpc32xx/common.c +++ b/trunk/arch/arm/mach-lpc32xx/common.c @@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void) static struct map_desc lpc32xx_io_desc[] __initdata = { { - .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START), + .virtual = IO_ADDRESS(LPC32XX_AHB0_START), .pfn = __phys_to_pfn(LPC32XX_AHB0_START), .length = LPC32XX_AHB0_SIZE, .type = MT_DEVICE }, { - .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START), + .virtual = IO_ADDRESS(LPC32XX_AHB1_START), .pfn = __phys_to_pfn(LPC32XX_AHB1_START), .length = LPC32XX_AHB1_SIZE, .type = MT_DEVICE }, { - .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START), + .virtual = IO_ADDRESS(LPC32XX_FABAPB_START), .pfn = __phys_to_pfn(LPC32XX_FABAPB_START), .length = LPC32XX_FABAPB_SIZE, .type = MT_DEVICE }, { - .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE), + .virtual = IO_ADDRESS(LPC32XX_IRAM_BASE), .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE), .length = (LPC32XX_IRAM_BANK_SIZE * 2), .type = MT_DEVICE diff --git a/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h b/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h index 69065de97a3d..33e1dde37bd9 100644 --- a/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h +++ b/trunk/arch/arm/mach-lpc32xx/include/mach/hardware.h @@ -25,7 +25,7 @@ /* * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */ -#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ +#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ IO_BASE) #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) diff --git a/trunk/arch/arm/mach-mmp/Kconfig b/trunk/arch/arm/mach-mmp/Kconfig index d697d07a1bf0..7fddd01b85b9 100644 --- a/trunk/arch/arm/mach-mmp/Kconfig +++ b/trunk/arch/arm/mach-mmp/Kconfig @@ -108,21 +108,18 @@ endmenu config CPU_PXA168 bool select CPU_MOHAWK - select COMMON_CLK help Select code specific to PXA168 config CPU_PXA910 bool select CPU_MOHAWK - select COMMON_CLK help Select code specific to PXA910 config CPU_MMP2 bool select CPU_PJ4 - select COMMON_CLK help Select code specific to MMP2. MMP2 is ARMv7 compatible. diff --git a/trunk/arch/arm/mach-mmp/Makefile b/trunk/arch/arm/mach-mmp/Makefile index 095c155d6fb8..b786f7e6cd1f 100644 --- a/trunk/arch/arm/mach-mmp/Makefile +++ b/trunk/arch/arm/mach-mmp/Makefile @@ -2,19 +2,13 @@ # Makefile for Marvell's PXA168 processors line # -obj-y += common.o devices.o time.o irq.o +obj-y += common.o clock.o devices.o time.o irq.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o obj-$(CONFIG_CPU_PXA910) += pxa910.o obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o -ifeq ($(CONFIG_COMMON_CLK), ) -obj-y += clock.o -obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o -obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o -obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o -endif ifeq ($(CONFIG_PM),y) obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o diff --git a/trunk/arch/arm/mach-mmp/clock-mmp2.c b/trunk/arch/arm/mach-mmp/clock-mmp2.c deleted file mode 100644 index 21d22002cd19..000000000000 --- a/trunk/arch/arm/mach-mmp/clock-mmp2.c +++ /dev/null @@ -1,111 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clock.h" - -/* - * APB Clock register offsets for MMP2 - */ -#define APBC_RTC APBC_REG(0x000) -#define APBC_TWSI1 APBC_REG(0x004) -#define APBC_TWSI2 APBC_REG(0x008) -#define APBC_TWSI3 APBC_REG(0x00c) -#define APBC_TWSI4 APBC_REG(0x010) -#define APBC_KPC APBC_REG(0x018) -#define APBC_UART1 APBC_REG(0x02c) -#define APBC_UART2 APBC_REG(0x030) -#define APBC_UART3 APBC_REG(0x034) -#define APBC_GPIO APBC_REG(0x038) -#define APBC_PWM0 APBC_REG(0x03c) -#define APBC_PWM1 APBC_REG(0x040) -#define APBC_PWM2 APBC_REG(0x044) -#define APBC_PWM3 APBC_REG(0x048) -#define APBC_SSP0 APBC_REG(0x04c) -#define APBC_SSP1 APBC_REG(0x050) -#define APBC_SSP2 APBC_REG(0x054) -#define APBC_SSP3 APBC_REG(0x058) -#define APBC_SSP4 APBC_REG(0x05c) -#define APBC_SSP5 APBC_REG(0x060) -#define APBC_TWSI5 APBC_REG(0x07c) -#define APBC_TWSI6 APBC_REG(0x080) -#define APBC_UART4 APBC_REG(0x088) - -#define APMU_USB APMU_REG(0x05c) -#define APMU_NAND APMU_REG(0x060) -#define APMU_SDH0 APMU_REG(0x054) -#define APMU_SDH1 APMU_REG(0x058) -#define APMU_SDH2 APMU_REG(0x0e8) -#define APMU_SDH3 APMU_REG(0x0ec) - -static void sdhc_clk_enable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst |= clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -static void sdhc_clk_disable(struct clk *clk) -{ - uint32_t clk_rst; - - clk_rst = __raw_readl(clk->clk_rst); - clk_rst &= ~clk->enable_val; - __raw_writel(clk_rst, clk->clk_rst); -} - -struct clkops sdhc_clk_ops = { - .enable = sdhc_clk_enable, - .disable = sdhc_clk_disable, -}; - -/* APB peripheral clocks */ -static APBC_CLK(uart1, UART1, 1, 26000000); -static APBC_CLK(uart2, UART2, 1, 26000000); -static APBC_CLK(uart3, UART3, 1, 26000000); -static APBC_CLK(uart4, UART4, 1, 26000000); -static APBC_CLK(twsi1, TWSI1, 0, 26000000); -static APBC_CLK(twsi2, TWSI2, 0, 26000000); -static APBC_CLK(twsi3, TWSI3, 0, 26000000); -static APBC_CLK(twsi4, TWSI4, 0, 26000000); -static APBC_CLK(twsi5, TWSI5, 0, 26000000); -static APBC_CLK(twsi6, TWSI6, 0, 26000000); -static APBC_CLK(gpio, GPIO, 0, 26000000); - -static APMU_CLK(nand, NAND, 0xbf, 100000000); -static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); -static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); - -static struct clk_lookup mmp2_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), - INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), - INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), - INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), - INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), -}; - -void __init mmp2_clk_init(void) -{ - clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); -} diff --git a/trunk/arch/arm/mach-mmp/clock-pxa168.c b/trunk/arch/arm/mach-mmp/clock-pxa168.c deleted file mode 100644 index 5e6c18ccebd4..000000000000 --- a/trunk/arch/arm/mach-mmp/clock-pxa168.c +++ /dev/null @@ -1,91 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clock.h" - -/* - * APB clock register offsets for PXA168 - */ -#define APBC_UART1 APBC_REG(0x000) -#define APBC_UART2 APBC_REG(0x004) -#define APBC_GPIO APBC_REG(0x008) -#define APBC_PWM1 APBC_REG(0x00c) -#define APBC_PWM2 APBC_REG(0x010) -#define APBC_PWM3 APBC_REG(0x014) -#define APBC_PWM4 APBC_REG(0x018) -#define APBC_RTC APBC_REG(0x028) -#define APBC_TWSI0 APBC_REG(0x02c) -#define APBC_KPC APBC_REG(0x030) -#define APBC_TWSI1 APBC_REG(0x06c) -#define APBC_UART3 APBC_REG(0x070) -#define APBC_SSP1 APBC_REG(0x81c) -#define APBC_SSP2 APBC_REG(0x820) -#define APBC_SSP3 APBC_REG(0x84c) -#define APBC_SSP4 APBC_REG(0x858) -#define APBC_SSP5 APBC_REG(0x85c) - -#define APMU_NAND APMU_REG(0x060) -#define APMU_LCD APMU_REG(0x04c) -#define APMU_ETH APMU_REG(0x0fc) -#define APMU_USB APMU_REG(0x05c) - -/* APB peripheral clocks */ -static APBC_CLK(uart1, UART1, 1, 14745600); -static APBC_CLK(uart2, UART2, 1, 14745600); -static APBC_CLK(uart3, UART3, 1, 14745600); -static APBC_CLK(twsi0, TWSI0, 1, 33000000); -static APBC_CLK(twsi1, TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PWM1, 1, 13000000); -static APBC_CLK(pwm2, PWM2, 1, 13000000); -static APBC_CLK(pwm3, PWM3, 1, 13000000); -static APBC_CLK(pwm4, PWM4, 1, 13000000); -static APBC_CLK(ssp1, SSP1, 4, 0); -static APBC_CLK(ssp2, SSP2, 4, 0); -static APBC_CLK(ssp3, SSP3, 4, 0); -static APBC_CLK(ssp4, SSP4, 4, 0); -static APBC_CLK(ssp5, SSP5, 4, 0); -static APBC_CLK(gpio, GPIO, 0, 13000000); -static APBC_CLK(keypad, KPC, 0, 32000); -static APBC_CLK(rtc, RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(lcd, LCD, 0x7f, 312000000); -static APMU_CLK(eth, ETH, 0x09, 0); -static APMU_CLK(usb, USB, 0x12, 0); - -/* device and clock bindings */ -static struct clk_lookup pxa168_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), - INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), - INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), - INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), - INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), - INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), - INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), - INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - -void __init pxa168_clk_init(void) -{ - clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); -} diff --git a/trunk/arch/arm/mach-mmp/clock-pxa910.c b/trunk/arch/arm/mach-mmp/clock-pxa910.c deleted file mode 100644 index 933ea71d0b56..000000000000 --- a/trunk/arch/arm/mach-mmp/clock-pxa910.c +++ /dev/null @@ -1,67 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#include - -#include "common.h" -#include "clock.h" - -/* - * APB Clock register offsets for PXA910 - */ -#define APBC_UART0 APBC_REG(0x000) -#define APBC_UART1 APBC_REG(0x004) -#define APBC_GPIO APBC_REG(0x008) -#define APBC_PWM1 APBC_REG(0x00c) -#define APBC_PWM2 APBC_REG(0x010) -#define APBC_PWM3 APBC_REG(0x014) -#define APBC_PWM4 APBC_REG(0x018) -#define APBC_SSP1 APBC_REG(0x01c) -#define APBC_SSP2 APBC_REG(0x020) -#define APBC_RTC APBC_REG(0x028) -#define APBC_TWSI0 APBC_REG(0x02c) -#define APBC_KPC APBC_REG(0x030) -#define APBC_SSP3 APBC_REG(0x04c) -#define APBC_TWSI1 APBC_REG(0x06c) - -#define APMU_NAND APMU_REG(0x060) -#define APMU_USB APMU_REG(0x05c) - -static APBC_CLK(uart1, UART0, 1, 14745600); -static APBC_CLK(uart2, UART1, 1, 14745600); -static APBC_CLK(twsi0, TWSI0, 1, 33000000); -static APBC_CLK(twsi1, TWSI1, 1, 33000000); -static APBC_CLK(pwm1, PWM1, 1, 13000000); -static APBC_CLK(pwm2, PWM2, 1, 13000000); -static APBC_CLK(pwm3, PWM3, 1, 13000000); -static APBC_CLK(pwm4, PWM4, 1, 13000000); -static APBC_CLK(gpio, GPIO, 0, 13000000); -static APBC_CLK(rtc, RTC, 8, 32768); - -static APMU_CLK(nand, NAND, 0x19b, 156000000); -static APMU_CLK(u2o, USB, 0x1b, 480000000); - -/* device and clock bindings */ -static struct clk_lookup pxa910_clkregs[] = { - INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), - INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), - INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), - INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), - INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), - INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), - INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), - INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), - INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), - INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), - INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), - INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), -}; - -void __init pxa910_clk_init(void) -{ - clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); -} diff --git a/trunk/arch/arm/mach-mmp/common.h b/trunk/arch/arm/mach-mmp/common.h index bd453274fca2..1c9d6c1ea97a 100644 --- a/trunk/arch/arm/mach-mmp/common.h +++ b/trunk/arch/arm/mach-mmp/common.h @@ -7,6 +7,3 @@ extern void timer_init(int irq); extern void __init icu_init_irq(void); extern void __init mmp_map_io(void); extern void mmp_restart(char, const char *); -extern void __init pxa168_clk_init(void); -extern void __init pxa910_clk_init(void); -extern void __init mmp2_clk_init(void); diff --git a/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h b/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h index ddc812f40341..68b0c93ec6a1 100644 --- a/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/trunk/arch/arm/mach-mmp/include/mach/regs-apbc.h @@ -13,6 +13,101 @@ #include +/* + * APB clock register offsets for PXA168 + */ +#define APBC_PXA168_UART1 APBC_REG(0x000) +#define APBC_PXA168_UART2 APBC_REG(0x004) +#define APBC_PXA168_GPIO APBC_REG(0x008) +#define APBC_PXA168_PWM1 APBC_REG(0x00c) +#define APBC_PXA168_PWM2 APBC_REG(0x010) +#define APBC_PXA168_PWM3 APBC_REG(0x014) +#define APBC_PXA168_PWM4 APBC_REG(0x018) +#define APBC_PXA168_RTC APBC_REG(0x028) +#define APBC_PXA168_TWSI0 APBC_REG(0x02c) +#define APBC_PXA168_KPC APBC_REG(0x030) +#define APBC_PXA168_TIMERS APBC_REG(0x034) +#define APBC_PXA168_AIB APBC_REG(0x03c) +#define APBC_PXA168_SW_JTAG APBC_REG(0x040) +#define APBC_PXA168_ONEWIRE APBC_REG(0x048) +#define APBC_PXA168_ASFAR APBC_REG(0x050) +#define APBC_PXA168_ASSAR APBC_REG(0x054) +#define APBC_PXA168_TWSI1 APBC_REG(0x06c) +#define APBC_PXA168_UART3 APBC_REG(0x070) +#define APBC_PXA168_AC97 APBC_REG(0x084) +#define APBC_PXA168_SSP1 APBC_REG(0x81c) +#define APBC_PXA168_SSP2 APBC_REG(0x820) +#define APBC_PXA168_SSP3 APBC_REG(0x84c) +#define APBC_PXA168_SSP4 APBC_REG(0x858) +#define APBC_PXA168_SSP5 APBC_REG(0x85c) + +/* + * APB Clock register offsets for PXA910 + */ +#define APBC_PXA910_UART0 APBC_REG(0x000) +#define APBC_PXA910_UART1 APBC_REG(0x004) +#define APBC_PXA910_GPIO APBC_REG(0x008) +#define APBC_PXA910_PWM1 APBC_REG(0x00c) +#define APBC_PXA910_PWM2 APBC_REG(0x010) +#define APBC_PXA910_PWM3 APBC_REG(0x014) +#define APBC_PXA910_PWM4 APBC_REG(0x018) +#define APBC_PXA910_SSP1 APBC_REG(0x01c) +#define APBC_PXA910_SSP2 APBC_REG(0x020) +#define APBC_PXA910_IPC APBC_REG(0x024) +#define APBC_PXA910_RTC APBC_REG(0x028) +#define APBC_PXA910_TWSI0 APBC_REG(0x02c) +#define APBC_PXA910_KPC APBC_REG(0x030) +#define APBC_PXA910_TIMERS APBC_REG(0x034) +#define APBC_PXA910_TBROT APBC_REG(0x038) +#define APBC_PXA910_AIB APBC_REG(0x03c) +#define APBC_PXA910_SW_JTAG APBC_REG(0x040) +#define APBC_PXA910_TIMERS1 APBC_REG(0x044) +#define APBC_PXA910_ONEWIRE APBC_REG(0x048) +#define APBC_PXA910_SSP3 APBC_REG(0x04c) +#define APBC_PXA910_ASFAR APBC_REG(0x050) +#define APBC_PXA910_ASSAR APBC_REG(0x054) + +/* + * APB Clock register offsets for MMP2 + */ +#define APBC_MMP2_RTC APBC_REG(0x000) +#define APBC_MMP2_TWSI1 APBC_REG(0x004) +#define APBC_MMP2_TWSI2 APBC_REG(0x008) +#define APBC_MMP2_TWSI3 APBC_REG(0x00c) +#define APBC_MMP2_TWSI4 APBC_REG(0x010) +#define APBC_MMP2_ONEWIRE APBC_REG(0x014) +#define APBC_MMP2_KPC APBC_REG(0x018) +#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c) +#define APBC_MMP2_SW_JTAG APBC_REG(0x020) +#define APBC_MMP2_TIMERS APBC_REG(0x024) +#define APBC_MMP2_UART1 APBC_REG(0x02c) +#define APBC_MMP2_UART2 APBC_REG(0x030) +#define APBC_MMP2_UART3 APBC_REG(0x034) +#define APBC_MMP2_GPIO APBC_REG(0x038) +#define APBC_MMP2_PWM0 APBC_REG(0x03c) +#define APBC_MMP2_PWM1 APBC_REG(0x040) +#define APBC_MMP2_PWM2 APBC_REG(0x044) +#define APBC_MMP2_PWM3 APBC_REG(0x048) +#define APBC_MMP2_SSP0 APBC_REG(0x04c) +#define APBC_MMP2_SSP1 APBC_REG(0x050) +#define APBC_MMP2_SSP2 APBC_REG(0x054) +#define APBC_MMP2_SSP3 APBC_REG(0x058) +#define APBC_MMP2_SSP4 APBC_REG(0x05c) +#define APBC_MMP2_SSP5 APBC_REG(0x060) +#define APBC_MMP2_AIB APBC_REG(0x064) +#define APBC_MMP2_ASFAR APBC_REG(0x068) +#define APBC_MMP2_ASSAR APBC_REG(0x06c) +#define APBC_MMP2_USIM APBC_REG(0x070) +#define APBC_MMP2_MPMU APBC_REG(0x074) +#define APBC_MMP2_IPC APBC_REG(0x078) +#define APBC_MMP2_TWSI5 APBC_REG(0x07c) +#define APBC_MMP2_TWSI6 APBC_REG(0x080) +#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084) +#define APBC_MMP2_UART4 APBC_REG(0x088) +#define APBC_MMP2_RIPC APBC_REG(0x08c) +#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */ +#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4) + /* Common APB clock register bit definitions */ #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ diff --git a/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h b/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h index 93c8d0e29bb9..7af8deb63e83 100644 --- a/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h +++ b/trunk/arch/arm/mach-mmp/include/mach/regs-apmu.h @@ -13,6 +13,21 @@ #include +/* Clock Reset Control */ +#define APMU_IRE APMU_REG(0x048) +#define APMU_LCD APMU_REG(0x04c) +#define APMU_CCIC APMU_REG(0x050) +#define APMU_SDH0 APMU_REG(0x054) +#define APMU_SDH1 APMU_REG(0x058) +#define APMU_USB APMU_REG(0x05c) +#define APMU_NAND APMU_REG(0x060) +#define APMU_DMA APMU_REG(0x064) +#define APMU_GEU APMU_REG(0x068) +#define APMU_BUS APMU_REG(0x06c) +#define APMU_SDH2 APMU_REG(0x0e8) +#define APMU_SDH3 APMU_REG(0x0ec) +#define APMU_ETH APMU_REG(0x0fc) + #define APMU_FNCLK_EN (1 << 4) #define APMU_AXICLK_EN (1 << 3) #define APMU_FNRST_DIS (1 << 1) diff --git a/trunk/arch/arm/mach-mmp/irq.c b/trunk/arch/arm/mach-mmp/irq.c index 3c71246cd994..e60c7d98922b 100644 --- a/trunk/arch/arm/mach-mmp/irq.c +++ b/trunk/arch/arm/mach-mmp/irq.c @@ -153,8 +153,10 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc) status = readl_relaxed(data->reg_status) & ~mask; if (status == 0) break; - for_each_set_bit(n, &status, BITS_PER_LONG) { + n = find_first_bit(&status, BITS_PER_LONG); + while (n < BITS_PER_LONG) { generic_handle_irq(icu_data[i].virq_base + n); + n = find_next_bit(&status, BITS_PER_LONG, n + 1); } } } diff --git a/trunk/arch/arm/mach-mmp/mmp2.c b/trunk/arch/arm/mach-mmp/mmp2.c index c2ce3d05b044..c709a24a9d25 100644 --- a/trunk/arch/arm/mach-mmp/mmp2.c +++ b/trunk/arch/arm/mach-mmp/mmp2.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -28,6 +29,7 @@ #include #include "common.h" +#include "clock.h" #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) @@ -96,6 +98,67 @@ void __init mmp2_init_irq(void) mmp2_init_icu(); } +static void sdhc_clk_enable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst |= clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +static void sdhc_clk_disable(struct clk *clk) +{ + uint32_t clk_rst; + + clk_rst = __raw_readl(clk->clk_rst); + clk_rst &= ~clk->enable_val; + __raw_writel(clk_rst, clk->clk_rst); +} + +struct clkops sdhc_clk_ops = { + .enable = sdhc_clk_enable, + .disable = sdhc_clk_disable, +}; + +/* APB peripheral clocks */ +static APBC_CLK(uart1, MMP2_UART1, 1, 26000000); +static APBC_CLK(uart2, MMP2_UART2, 1, 26000000); +static APBC_CLK(uart3, MMP2_UART3, 1, 26000000); +static APBC_CLK(uart4, MMP2_UART4, 1, 26000000); +static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000); +static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000); +static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000); +static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000); +static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000); +static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000); +static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000); + +static APMU_CLK(nand, NAND, 0xbf, 100000000); +static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops); +static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops); + +static struct clk_lookup mmp2_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL), + INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL), + INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL), + INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"), + INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"), +}; + static int __init mmp2_init(void) { if (cpu_is_mmp2()) { @@ -105,27 +168,25 @@ static int __init mmp2_init(void) mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(mmp2_addr_map); pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16); - mmp2_clk_init(); + clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs)); } return 0; } postcore_initcall(mmp2_init); -#define APBC_TIMERS APBC_REG(0x024) - static void __init mmp2_timer_init(void) { unsigned long clk_rst; - __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS); /* * enable bus/functional clock, enable 6.5MHz (divider 4), * release reset */ clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); - __raw_writel(clk_rst, APBC_TIMERS); + __raw_writel(clk_rst, APBC_MMP2_TIMERS); timer_init(IRQ_MMP2_TIMER1); } diff --git a/trunk/arch/arm/mach-mmp/pxa168.c b/trunk/arch/arm/mach-mmp/pxa168.c index b7f074f15498..62d787c34475 100644 --- a/trunk/arch/arm/mach-mmp/pxa168.c +++ b/trunk/arch/arm/mach-mmp/pxa168.c @@ -18,8 +18,8 @@ #include #include -#include #include +#include #include #include #include @@ -50,13 +50,62 @@ void __init pxa168_init_irq(void) icu_init_irq(); } +/* APB peripheral clocks */ +static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); +static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); +static APBC_CLK(uart3, PXA168_UART3, 1, 14745600); +static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); +static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000); +static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000); +static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000); +static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000); +static APBC_CLK(ssp1, PXA168_SSP1, 4, 0); +static APBC_CLK(ssp2, PXA168_SSP2, 4, 0); +static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); +static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); +static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); +static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000); +static APBC_CLK(keypad, PXA168_KPC, 0, 32000); +static APBC_CLK(rtc, PXA168_RTC, 8, 32768); + +static APMU_CLK(nand, NAND, 0x19b, 156000000); +static APMU_CLK(lcd, LCD, 0x7f, 312000000); +static APMU_CLK(eth, ETH, 0x09, 0); +static APMU_CLK(usb, USB, 0x12, 0); + +/* device and clock bindings */ +static struct clk_lookup pxa168_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL), + INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL), + INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL), + INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL), + INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), + INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL), + INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"), + INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"), + INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), +}; + static int __init pxa168_init(void) { if (cpu_is_pxa168()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa168_mfp_addr_map); pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); - pxa168_clk_init(); + clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs)); } return 0; @@ -65,7 +114,6 @@ postcore_initcall(pxa168_init); /* system timer - clock enabled, 3.25MHz */ #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) -#define APBC_TIMERS APBC_REG(0x34) static void __init pxa168_timer_init(void) { @@ -73,10 +121,10 @@ static void __init pxa168_timer_init(void) * ourselves instead of using clk_* API. Clock rate is defined * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); /* 3.25MHz, bus/functional clock enabled, release reset */ - __raw_writel(TIMER_CLK_RST, APBC_TIMERS); + __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); timer_init(IRQ_PXA168_TIMER1); } diff --git a/trunk/arch/arm/mach-mmp/pxa910.c b/trunk/arch/arm/mach-mmp/pxa910.c index 7d84521bb715..6da52e9f2bdc 100644 --- a/trunk/arch/arm/mach-mmp/pxa910.c +++ b/trunk/arch/arm/mach-mmp/pxa910.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -24,6 +25,7 @@ #include #include "common.h" +#include "clock.h" #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) @@ -80,13 +82,44 @@ void __init pxa910_init_irq(void) icu_init_irq(); } +/* APB peripheral clocks */ +static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); +static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); +static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000); +static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000); +static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000); +static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000); +static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000); +static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000); +static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000); +static APBC_CLK(rtc, PXA910_RTC, 8, 32768); + +static APMU_CLK(nand, NAND, 0x19b, 156000000); +static APMU_CLK(u2o, USB, 0x1b, 480000000); + +/* device and clock bindings */ +static struct clk_lookup pxa910_clkregs[] = { + INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), + INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), + INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL), + INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL), + INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL), + INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL), + INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL), + INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL), + INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), + INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL), + INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"), + INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL), +}; + static int __init pxa910_init(void) { if (cpu_is_pxa910()) { mfp_init_base(MFPR_VIRT_BASE); mfp_init_addr(pxa910_mfp_addr_map); pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); - pxa910_clk_init(); + clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs)); } return 0; @@ -95,13 +128,12 @@ postcore_initcall(pxa910_init); /* system timer - clock enabled, 3.25MHz */ #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) -#define APBC_TIMERS APBC_REG(0x34) static void __init pxa910_timer_init(void) { /* reset and configure */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); - __raw_writel(TIMER_CLK_RST, APBC_TIMERS); + __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); + __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); timer_init(IRQ_PXA910_AP1_TIMER1); } diff --git a/trunk/arch/arm/mach-mmp/sram.c b/trunk/arch/arm/mach-mmp/sram.c index 7e8a5a2e1ec7..4304f9519372 100644 --- a/trunk/arch/arm/mach-mmp/sram.c +++ b/trunk/arch/arm/mach-mmp/sram.c @@ -68,7 +68,7 @@ static int __devinit sram_probe(struct platform_device *pdev) struct resource *res; int ret = 0; - if (!pdata || !pdata->pool_name) + if (!pdata && !pdata->pool_name) return -ENODEV; info = kzalloc(sizeof(*info), GFP_KERNEL); diff --git a/trunk/arch/arm/mach-msm/Makefile b/trunk/arch/arm/mach-msm/Makefile index 6a6c197212eb..4ad3969b9881 100644 --- a/trunk/arch/arm/mach-msm/Makefile +++ b/trunk/arch/arm/mach-msm/Makefile @@ -1,11 +1,11 @@ -obj-y += io.o timer.o +obj-y += io.o idle.o timer.o obj-y += clock.o obj-$(CONFIG_DEBUG_FS) += clock-debug.o obj-$(CONFIG_MSM_VIC) += irq-vic.o obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o -obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o +obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o obj-$(CONFIG_ARCH_MSM7X30) += dma.o obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o diff --git a/trunk/arch/arm/mach-msm/acpuclock-arm11.c b/trunk/arch/arm/mach-msm/acpuclock-arm11.c new file mode 100644 index 000000000000..805d4ee53f7e --- /dev/null +++ b/trunk/arch/arm/mach-msm/acpuclock-arm11.c @@ -0,0 +1,525 @@ +/* arch/arm/mach-msm/acpuclock.c + * + * MSM architecture clock driver + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007 QUALCOMM Incorporated + * Author: San Mehat + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "proc_comm.h" +#include "acpuclock.h" + + +#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100) +#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104) +#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124) + +/* + * ARM11 clock configuration for specific ACPU speeds + */ + +#define ACPU_PLL_TCXO -1 +#define ACPU_PLL_0 0 +#define ACPU_PLL_1 1 +#define ACPU_PLL_2 2 +#define ACPU_PLL_3 3 + +#define PERF_SWITCH_DEBUG 0 +#define PERF_SWITCH_STEP_DEBUG 0 + +struct clock_state +{ + struct clkctl_acpu_speed *current_speed; + struct mutex lock; + uint32_t acpu_switch_time_us; + uint32_t max_speed_delta_khz; + uint32_t vdd_switch_time_us; + unsigned long power_collapse_khz; + unsigned long wait_for_irq_khz; +}; + +static struct clk *ebi1_clk; +static struct clock_state drv_state = { 0 }; + +static void __init acpuclk_init(void); + +/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */ +enum { + VDD_0 = 0, + VDD_1 = 1, + VDD_2 = 2, + VDD_3 = 3, + VDD_4 = 3, + VDD_5 = 3, + VDD_6 = 3, + VDD_7 = 7, + VDD_END +}; + +struct clkctl_acpu_speed { + unsigned int a11clk_khz; + int pll; + unsigned int a11clk_src_sel; + unsigned int a11clk_src_div; + unsigned int ahbclk_khz; + unsigned int ahbclk_div; + int vdd; + unsigned int axiclk_khz; + unsigned long lpj; /* loops_per_jiffy */ +/* Index in acpu_freq_tbl[] for steppings. */ + short down; + short up; +}; + +/* + * ACPU speed table. Complete table is shown but certain speeds are commented + * out to optimized speed switching. Initialize loops_per_jiffy to 0. + * + * Table stepping up/down is optimized for 256mhz jumps while staying on the + * same PLL. + */ +#if (0) +static struct clkctl_acpu_speed acpu_freq_tbl[] = { + { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 }, + { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 }, + { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 }, + { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 }, + { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 }, + { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 }, + { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 }, + { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 }, + { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 }, + { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 }, + { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 }, + { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 }, + { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 }, + { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; +#else /* Table of freq we currently use. */ +static struct clkctl_acpu_speed acpu_freq_tbl[] = { + { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 }, + { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 }, + { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 }, + { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 }, + { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 }, + { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 }, + { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 }, + { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; +#endif + + +#ifdef CONFIG_CPU_FREQ_TABLE +static struct cpufreq_frequency_table freq_table[] = { + { 0, 122880 }, + { 1, 128000 }, + { 2, 245760 }, + { 3, 384000 }, + { 4, 528000 }, + { 5, CPUFREQ_TABLE_END }, +}; +#endif + +static int pc_pll_request(unsigned id, unsigned on) +{ + int res; + on = !!on; + +#if PERF_SWITCH_DEBUG + if (on) + printk(KERN_DEBUG "Enabling PLL %d\n", id); + else + printk(KERN_DEBUG "Disabling PLL %d\n", id); +#endif + + res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on); + if (res < 0) + return res; + +#if PERF_SWITCH_DEBUG + if (on) + printk(KERN_DEBUG "PLL %d enabled\n", id); + else + printk(KERN_DEBUG "PLL %d disabled\n", id); +#endif + return res; +} + + +/*---------------------------------------------------------------------------- + * ARM11 'owned' clock control + *---------------------------------------------------------------------------*/ + +unsigned long acpuclk_power_collapse(void) { + int ret = acpuclk_get_rate(); + ret *= 1000; + if (ret > drv_state.power_collapse_khz) + acpuclk_set_rate(drv_state.power_collapse_khz, 1); + return ret; +} + +unsigned long acpuclk_get_wfi_rate(void) +{ + return drv_state.wait_for_irq_khz; +} + +unsigned long acpuclk_wait_for_irq(void) { + int ret = acpuclk_get_rate(); + ret *= 1000; + if (ret > drv_state.wait_for_irq_khz) + acpuclk_set_rate(drv_state.wait_for_irq_khz, 1); + return ret; +} + +static int acpuclk_set_vdd_level(int vdd) +{ + uint32_t current_vdd; + + current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07; + +#if PERF_SWITCH_DEBUG + printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n", + current_vdd, vdd); +#endif + writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR); + udelay(drv_state.vdd_switch_time_us); + if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) { +#if PERF_SWITCH_DEBUG + printk(KERN_ERR "acpuclock: VDD set failed\n"); +#endif + return -EIO; + } + +#if PERF_SWITCH_DEBUG + printk(KERN_DEBUG "acpuclock: VDD switched\n"); +#endif + return 0; +} + +/* Set proper dividers for the given clock speed. */ +static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) { + uint32_t reg_clkctl, reg_clksel, clk_div; + + /* AHB_CLK_DIV */ + clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03; + /* + * If the new clock divider is higher than the previous, then + * program the divider before switching the clock + */ + if (hunt_s->ahbclk_div > clk_div) { + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel &= ~(0x3 << 1); + reg_clksel |= (hunt_s->ahbclk_div << 1); + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } + if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) { + /* SRC0 */ + + /* Program clock source */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~(0x07 << 4); + reg_clkctl |= (hunt_s->a11clk_src_sel << 4); + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock divider */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~0xf; + reg_clkctl |= hunt_s->a11clk_src_div; + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock source selection */ + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */ + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } else { + /* SRC1 */ + + /* Program clock source */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~(0x07 << 12); + reg_clkctl |= (hunt_s->a11clk_src_sel << 12); + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock divider */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl &= ~(0xf << 8); + reg_clkctl |= (hunt_s->a11clk_src_div << 8); + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + + /* Program clock source selection */ + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */ + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } + + /* + * If the new clock divider is lower than the previous, then + * program the divider after switching the clock + */ + if (hunt_s->ahbclk_div < clk_div) { + reg_clksel = readl(A11S_CLK_SEL_ADDR); + reg_clksel &= ~(0x3 << 1); + reg_clksel |= (hunt_s->ahbclk_div << 1); + writel(reg_clksel, A11S_CLK_SEL_ADDR); + } +} + +int acpuclk_set_rate(unsigned long rate, int for_power_collapse) +{ + uint32_t reg_clkctl; + struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s; + int rc = 0; + unsigned int plls_enabled = 0, pll; + + strt_s = cur_s = drv_state.current_speed; + + WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n"); + if (cur_s == NULL) + return -ENOENT; + + if (rate == (cur_s->a11clk_khz * 1000)) + return 0; + + for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) { + if (tgt_s->a11clk_khz == (rate / 1000)) + break; + } + + if (tgt_s->a11clk_khz == 0) + return -EINVAL; + + /* Choose the highest speed speed at or below 'rate' with same PLL. */ + if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) { + while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll) + tgt_s--; + } + + if (strt_s->pll != ACPU_PLL_TCXO) + plls_enabled |= 1 << strt_s->pll; + + if (!for_power_collapse) { + mutex_lock(&drv_state.lock); + if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) { + rc = pc_pll_request(tgt_s->pll, 1); + if (rc < 0) { + pr_err("PLL%d enable failed (%d)\n", + tgt_s->pll, rc); + goto out; + } + plls_enabled |= 1 << tgt_s->pll; + } + /* Increase VDD if needed. */ + if (tgt_s->vdd > cur_s->vdd) { + if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) { + printk(KERN_ERR "Unable to switch ACPU vdd\n"); + goto out; + } + } + } + + /* Set wait states for CPU between frequency changes */ + reg_clkctl = readl(A11S_CLK_CNTL_ADDR); + reg_clkctl |= (100 << 16); /* set WT_ST_CNT */ + writel(reg_clkctl, A11S_CLK_CNTL_ADDR); + +#if PERF_SWITCH_DEBUG + printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n", + strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000); +#endif + + while (cur_s != tgt_s) { + /* + * Always jump to target freq if within 256mhz, regulardless of + * PLL. If differnece is greater, use the predefinied + * steppings in the table. + */ + int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz)); + if (d > drv_state.max_speed_delta_khz) { + /* Step up or down depending on target vs current. */ + int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ? + cur_s->up : cur_s->down; + if (clk_index < 0) { /* This should not happen. */ + printk(KERN_ERR "cur:%u target: %u\n", + cur_s->a11clk_khz, tgt_s->a11clk_khz); + rc = -EINVAL; + goto out; + } + cur_s = &acpu_freq_tbl[clk_index]; + } else { + cur_s = tgt_s; + } +#if PERF_SWITCH_STEP_DEBUG + printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n", + __FUNCTION__, cur_s->a11clk_khz, cur_s->pll); +#endif + if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO + && !(plls_enabled & (1 << cur_s->pll))) { + rc = pc_pll_request(cur_s->pll, 1); + if (rc < 0) { + pr_err("PLL%d enable failed (%d)\n", + cur_s->pll, rc); + goto out; + } + plls_enabled |= 1 << cur_s->pll; + } + + acpuclk_set_div(cur_s); + drv_state.current_speed = cur_s; + /* Re-adjust lpj for the new clock speed. */ + loops_per_jiffy = cur_s->lpj; + udelay(drv_state.acpu_switch_time_us); + } + + /* Nothing else to do for power collapse. */ + if (for_power_collapse) + return 0; + + /* Disable PLLs we are not using anymore. */ + plls_enabled &= ~(1 << tgt_s->pll); + for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++) + if (plls_enabled & (1 << pll)) { + rc = pc_pll_request(pll, 0); + if (rc < 0) { + pr_err("PLL%d disable failed (%d)\n", pll, rc); + goto out; + } + } + + /* Change the AXI bus frequency if we can. */ + if (strt_s->axiclk_khz != tgt_s->axiclk_khz) { + rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000); + if (rc < 0) + pr_err("Setting AXI min rate failed!\n"); + } + + /* Drop VDD level if we can. */ + if (tgt_s->vdd < strt_s->vdd) { + if (acpuclk_set_vdd_level(tgt_s->vdd) < 0) + printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n"); + } + +#if PERF_SWITCH_DEBUG + printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__); +#endif +out: + if (!for_power_collapse) + mutex_unlock(&drv_state.lock); + return rc; +} + +static void __init acpuclk_init(void) +{ + struct clkctl_acpu_speed *speed; + uint32_t div, sel; + int rc; + + /* + * Determine the rate of ACPU clock + */ + + if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */ + /* CLK_SRC0_SEL */ + sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7; + /* CLK_SRC0_DIV */ + div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f; + } else { + /* CLK_SRC1_SEL */ + sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07; + /* CLK_SRC1_DIV */ + div = readl(A11S_CLK_CNTL_ADDR) & 0x0f; + } + + for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) { + if (speed->a11clk_src_sel == sel + && (speed->a11clk_src_div == div)) + break; + } + if (speed->a11clk_khz == 0) { + printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n"); + return; + } + + drv_state.current_speed = speed; + + rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000); + if (rc < 0) + pr_err("Setting AXI min rate failed!\n"); + + printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz); +} + +unsigned long acpuclk_get_rate(void) +{ + WARN_ONCE(drv_state.current_speed == NULL, + "acpuclk_get_rate: not initialized\n"); + if (drv_state.current_speed) + return drv_state.current_speed->a11clk_khz; + else + return 0; +} + +uint32_t acpuclk_get_switch_time(void) +{ + return drv_state.acpu_switch_time_us; +} + +/*---------------------------------------------------------------------------- + * Clock driver initialization + *---------------------------------------------------------------------------*/ + +/* Initialize the lpj field in the acpu_freq_tbl. */ +static void __init lpj_init(void) +{ + int i; + const struct clkctl_acpu_speed *base_clk = drv_state.current_speed; + for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) { + acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy, + base_clk->a11clk_khz, + acpu_freq_tbl[i].a11clk_khz); + } +} + +void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata) +{ + pr_info("acpu_clock_init()\n"); + + ebi1_clk = clk_get(NULL, "ebi1_clk"); + + mutex_init(&drv_state.lock); + drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us; + drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz; + drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us; + drv_state.power_collapse_khz = clkdata->power_collapse_khz; + drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz; + acpuclk_init(); + lpj_init(); +#ifdef CONFIG_CPU_FREQ_TABLE + cpufreq_frequency_table_get_attr(freq_table, smp_processor_id()); +#endif +} diff --git a/trunk/arch/arm/mach-msm/acpuclock.h b/trunk/arch/arm/mach-msm/acpuclock.h new file mode 100644 index 000000000000..415de2eb9a5e --- /dev/null +++ b/trunk/arch/arm/mach-msm/acpuclock.h @@ -0,0 +1,32 @@ +/* arch/arm/mach-msm/acpuclock.h + * + * MSM architecture clock driver header + * + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2007 QUALCOMM Incorporated + * Author: San Mehat + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H +#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H + +int acpuclk_set_rate(unsigned long rate, int for_power_collapse); +unsigned long acpuclk_get_rate(void); +uint32_t acpuclk_get_switch_time(void); +unsigned long acpuclk_wait_for_irq(void); +unsigned long acpuclk_power_collapse(void); +unsigned long acpuclk_get_wfi_rate(void); + + +#endif + diff --git a/trunk/arch/arm/mach-msm/board-mahimahi.c b/trunk/arch/arm/mach-msm/board-mahimahi.c index df00bc03ce74..cf1f89a5dc62 100644 --- a/trunk/arch/arm/mach-msm/board-mahimahi.c +++ b/trunk/arch/arm/mach-msm/board-mahimahi.c @@ -30,6 +30,7 @@ #include #include +#include #include "board-mahimahi.h" #include "devices.h" diff --git a/trunk/arch/arm/mach-msm/board-msm7x27.c b/trunk/arch/arm/mach-msm/board-msm7x27.c new file mode 100644 index 000000000000..451ab1d43c92 --- /dev/null +++ b/trunk/arch/arm/mach-msm/board-msm7x27.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2007 Google, Inc. + * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. + * Author: Brian Swetland + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_CACHE_L2X0 +#include +#endif + +#include +#include +#include +#include + +#include +#include + +#include "devices.h" +#include "socinfo.h" +#include "clock.h" + +static struct resource smc91x_resources[] = { + [0] = { + .start = 0x9C004300, + .end = 0x9C0043ff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MSM_GPIO_TO_INT(132), + .end = MSM_GPIO_TO_INT(132), + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device smc91x_device = { + .name = "smc91x", + .id = 0, + .num_resources = ARRAY_SIZE(smc91x_resources), + .resource = smc91x_resources, +}; + +static struct platform_device *devices[] __initdata = { + &msm_device_uart3, + &msm_device_smd, + &msm_device_dmov, + &msm_device_nand, + &smc91x_device, +}; + +extern struct sys_timer msm_timer; + +static void __init msm7x2x_init_irq(void) +{ + msm_init_irq(); +} + +static void __init msm7x2x_init(void) +{ + if (socinfo_init() < 0) + BUG(); + + if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) { + smc91x_resources[0].start = 0x98000300; + smc91x_resources[0].end = 0x980003ff; + smc91x_resources[1].start = MSM_GPIO_TO_INT(85); + smc91x_resources[1].end = MSM_GPIO_TO_INT(85); + if (gpio_tlmm_config(GPIO_CFG(85, 0, + GPIO_INPUT, + GPIO_PULL_DOWN, + GPIO_2MA), + GPIO_ENABLE)) { + printk(KERN_ERR + "%s: Err: Config GPIO-85 INT\n", + __func__); + } + } + + platform_add_devices(devices, ARRAY_SIZE(devices)); +} + +static void __init msm7x2x_map_io(void) +{ + msm_map_common_io(); + /* Technically dependent on the SoC but using machine_is + * macros since socinfo is not available this early and there + * are plans to restructure the code which will eliminate the + * need for socinfo. + */ + if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) + msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27); + + if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa()) + msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25); + +#ifdef CONFIG_CACHE_L2X0 + if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) { + /* 7x27 has 256KB L2 cache: + 64Kb/Way and 4-Way Associativity; + R/W latency: 3 cycles; + evmon/parity/share disabled. */ + l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000); + } +#endif +} + +static void __init msm7x2x_init_late(void) +{ + smd_debugfs_init(); +} + +MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") + .atag_offset = 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .init_late = msm7x2x_init_late, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") + .atag_offset = 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .init_late = msm7x2x_init_late, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") + .atag_offset = 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .init_late = msm7x2x_init_late, + .timer = &msm_timer, +MACHINE_END + +MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") + .atag_offset = 0x100, + .map_io = msm7x2x_map_io, + .init_irq = msm7x2x_init_irq, + .init_machine = msm7x2x_init, + .init_late = msm7x2x_init_late, + .timer = &msm_timer, +MACHINE_END diff --git a/trunk/arch/arm/mach-msm/board-msm8x60.c b/trunk/arch/arm/mach-msm/board-msm8x60.c index 06003b4ccb10..e37a724cd1eb 100644 --- a/trunk/arch/arm/mach-msm/board-msm8x60.c +++ b/trunk/arch/arm/mach-msm/board-msm8x60.c @@ -93,6 +93,11 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { static void __init msm8x60_dt_init(void) { + if (of_machine_is_compatible("qcom,msm8660-surf")) { + printk(KERN_INFO "Init surf UART registers\n"); + msm8x60_init_uart12dm(); + } + of_platform_populate(NULL, of_default_bus_match_table, msm_auxdata_lookup, NULL); } diff --git a/trunk/arch/arm/mach-msm/board-sapphire.c b/trunk/arch/arm/mach-msm/board-sapphire.c index b7b0fc7e3278..2e569ab10eef 100644 --- a/trunk/arch/arm/mach-msm/board-sapphire.c +++ b/trunk/arch/arm/mach-msm/board-sapphire.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include diff --git a/trunk/arch/arm/mach-msm/clock-pcom.c b/trunk/arch/arm/mach-msm/clock-pcom.c index a52c970df157..63b711311086 100644 --- a/trunk/arch/arm/mach-msm/clock-pcom.c +++ b/trunk/arch/arm/mach-msm/clock-pcom.c @@ -25,7 +25,7 @@ /* * glue for the proc_comm interface */ -static int pc_clk_enable(unsigned id) +int pc_clk_enable(unsigned id) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL); if (rc < 0) @@ -34,7 +34,7 @@ static int pc_clk_enable(unsigned id) return (int)id < 0 ? -EINVAL : 0; } -static void pc_clk_disable(unsigned id) +void pc_clk_disable(unsigned id) { msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL); } @@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action) return (int)id < 0 ? -EINVAL : 0; } -static int pc_clk_set_rate(unsigned id, unsigned rate) +int pc_clk_set_rate(unsigned id, unsigned rate) { /* The rate _might_ be rounded off to the nearest KHz value by the * remote function. So a return value of 0 doesn't necessarily mean @@ -67,7 +67,7 @@ static int pc_clk_set_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -static int pc_clk_set_min_rate(unsigned id, unsigned rate) +int pc_clk_set_min_rate(unsigned id, unsigned rate) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate); if (rc < 0) @@ -76,7 +76,7 @@ static int pc_clk_set_min_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -static int pc_clk_set_max_rate(unsigned id, unsigned rate) +int pc_clk_set_max_rate(unsigned id, unsigned rate) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate); if (rc < 0) @@ -85,7 +85,7 @@ static int pc_clk_set_max_rate(unsigned id, unsigned rate) return (int)id < 0 ? -EINVAL : 0; } -static int pc_clk_set_flags(unsigned id, unsigned flags) +int pc_clk_set_flags(unsigned id, unsigned flags) { int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags); if (rc < 0) @@ -94,7 +94,7 @@ static int pc_clk_set_flags(unsigned id, unsigned flags) return (int)id < 0 ? -EINVAL : 0; } -static unsigned pc_clk_get_rate(unsigned id) +unsigned pc_clk_get_rate(unsigned id) { if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL)) return 0; @@ -102,7 +102,7 @@ static unsigned pc_clk_get_rate(unsigned id) return id; } -static unsigned pc_clk_is_enabled(unsigned id) +unsigned pc_clk_is_enabled(unsigned id) { if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL)) return 0; @@ -110,7 +110,7 @@ static unsigned pc_clk_is_enabled(unsigned id) return id; } -static long pc_clk_round_rate(unsigned id, unsigned rate) +long pc_clk_round_rate(unsigned id, unsigned rate) { /* Not really supported; pc_clk_set_rate() does rounding on it's own. */ diff --git a/trunk/arch/arm/mach-msm/dma.c b/trunk/arch/arm/mach-msm/dma.c index 354b91d4c3ac..02cae5e2951c 100644 --- a/trunk/arch/arm/mach-msm/dma.c +++ b/trunk/arch/arm/mach-msm/dma.c @@ -223,7 +223,8 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id) PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status); if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) { cmd = list_entry(ready_commands[id].next, typeof(*cmd), list); - list_move_tail(&cmd->list, &active_commands[id]); + list_del(&cmd->list); + list_add_tail(&cmd->list, &active_commands[id]); if (cmd->execute_func) cmd->execute_func(cmd); PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id); diff --git a/trunk/arch/arm/mach-msm/idle.c b/trunk/arch/arm/mach-msm/idle.c new file mode 100644 index 000000000000..0c9e13c65743 --- /dev/null +++ b/trunk/arch/arm/mach-msm/idle.c @@ -0,0 +1,49 @@ +/* arch/arm/mach-msm/idle.c + * + * Idle processing for MSM7K - work around bugs with SWFI. + * + * Copyright (c) 2007 QUALCOMM Incorporated. + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +static void msm_idle(void) +{ +#ifdef CONFIG_MSM7X00A_IDLE + asm volatile ( + + "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t" + "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t" + "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t" + "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t" + + "mov r0, #0 /* prepare wfi value */ \n\t" + "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t" + "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t" + "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t" + + "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t" + + : : : "r0","r1" ); +#endif +} + +static int __init msm_idle_init(void) +{ + arm_pm_idle = msm_idle; + return 0; +} + +arch_initcall(msm_idle_init); diff --git a/trunk/arch/arm/mach-msm/include/mach/board.h b/trunk/arch/arm/mach-msm/include/mach/board.h index 5a0811a4c851..435f8edfafd1 100644 --- a/trunk/arch/arm/mach-msm/include/mach/board.h +++ b/trunk/arch/arm/mach-msm/include/mach/board.h @@ -22,6 +22,15 @@ /* platform device data structures */ +struct msm_acpu_clock_platform_data +{ + uint32_t acpu_switch_time_us; + uint32_t max_speed_delta_khz; + uint32_t vdd_switch_time_us; + unsigned long power_collapse_khz; + unsigned long wait_for_irq_khz; +}; + struct clk_lookup; extern struct sys_timer msm_timer; @@ -33,6 +42,7 @@ void __init msm_map_common_io(void); void __init msm_init_irq(void); void __init msm_init_gpio(void); void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks); +void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *); int __init msm_add_sdcc(unsigned int controller, struct msm_mmc_platform_data *plat, unsigned int stat_irq, unsigned long stat_irq_flags); diff --git a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h index facf434d09be..a1752c0284fc 100644 --- a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h +++ b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8960.h @@ -46,7 +46,7 @@ #define MSM8960_TMR0_SIZE SZ_4K #ifdef CONFIG_DEBUG_MSM8960_UART -#define MSM_DEBUG_UART_BASE 0xF0040000 +#define MSM_DEBUG_UART_BASE 0xE1040000 #define MSM_DEBUG_UART_PHYS 0x16440000 #endif diff --git a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 21a2a8859a9a..5aed57dc808c 100644 --- a/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/trunk/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -63,7 +63,7 @@ #define MSM8X60_TMR0_SIZE SZ_4K #ifdef CONFIG_DEBUG_MSM8660_UART -#define MSM_DEBUG_UART_BASE 0xF0040000 +#define MSM_DEBUG_UART_BASE 0xE1040000 #define MSM_DEBUG_UART_PHYS 0x19C40000 #endif diff --git a/trunk/arch/arm/mach-msm/include/mach/system.h b/trunk/arch/arm/mach-msm/include/mach/system.h new file mode 100644 index 000000000000..f5fb2ec87ffe --- /dev/null +++ b/trunk/arch/arm/mach-msm/include/mach/system.h @@ -0,0 +1,19 @@ +/* arch/arm/mach-msm/include/mach/system.h + * + * Copyright (C) 2007 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* low level hardware reset hook -- for example, hitting the + * PSHOLD line on the PMIC to hard reset the system + */ +extern void (*msm_hw_reset_hook)(void); diff --git a/trunk/arch/arm/mach-msm/io.c b/trunk/arch/arm/mach-msm/io.c index 3cb4f4c35710..a1e7b1168850 100644 --- a/trunk/arch/arm/mach-msm/io.c +++ b/trunk/arch/arm/mach-msm/io.c @@ -29,30 +29,30 @@ #include -#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ +#define MSM_CHIP_DEVICE(name, chip) { \ .virtual = (unsigned long) MSM_##name##_BASE, \ .pfn = __phys_to_pfn(chip##_##name##_PHYS), \ .length = chip##_##name##_SIZE, \ - .type = mem_type, \ + .type = MT_DEVICE_NONSHARED, \ } -#define MSM_DEVICE_TYPE(name, mem_type) \ - MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type) -#define MSM_CHIP_DEVICE(name, chip) \ - MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE) #define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM) -#if defined(CONFIG_ARCH_MSM7X00A) +#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \ + || defined(CONFIG_ARCH_MSM7X25) static struct map_desc msm_io_desc[] __initdata = { - MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED), - MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED), - MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED), - MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), - MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), - MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), + MSM_DEVICE(VIC), + MSM_CHIP_DEVICE(CSR, MSM7X00), + MSM_DEVICE(DMOV), + MSM_CHIP_DEVICE(GPIO1, MSM7X00), + MSM_CHIP_DEVICE(GPIO2, MSM7X00), + MSM_DEVICE(CLK_CTL), #if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \ defined(CONFIG_DEBUG_MSM_UART3) - MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED), + MSM_DEVICE(DEBUG_UART), +#endif +#ifdef CONFIG_ARCH_MSM7X30 + MSM_DEVICE(GCC), #endif { .virtual = (unsigned long) MSM_SHARED_RAM_BASE, diff --git a/trunk/arch/arm/mach-msm/proc_comm.c b/trunk/arch/arm/mach-msm/proc_comm.c index 8f1eecd88186..9980dc736e7b 100644 --- a/trunk/arch/arm/mach-msm/proc_comm.c +++ b/trunk/arch/arm/mach-msm/proc_comm.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "proc_comm.h" diff --git a/trunk/arch/arm/mach-msm/smd.c b/trunk/arch/arm/mach-msm/smd.c index c5a2eddc6cdc..657be73297db 100644 --- a/trunk/arch/arm/mach-msm/smd.c +++ b/trunk/arch/arm/mach-msm/smd.c @@ -30,6 +30,7 @@ #include #include +#include #include "smd_private.h" #include "proc_comm.h" @@ -38,6 +39,8 @@ #define CONFIG_QDSP6 1 #endif +void (*msm_hw_reset_hook)(void); + #define MODULE_NAME "msm_smd" enum { @@ -49,14 +52,13 @@ static int msm_smd_debug_mask; struct shared_info { int ready; - void __iomem *state; + unsigned state; }; static unsigned dummy_state[SMSM_STATE_COUNT]; static struct shared_info smd_info = { - /* FIXME: not a real __iomem pointer */ - .state = &dummy_state, + .state = (unsigned) &dummy_state, }; module_param_named(debug_mask, msm_smd_debug_mask, @@ -99,6 +101,10 @@ static void handle_modem_crash(void) pr_err("ARM9 has CRASHED\n"); smd_diag(); + /* hard reboot if possible */ + if (msm_hw_reset_hook) + msm_hw_reset_hook(); + /* in this case the modem or watchdog should reboot us */ for (;;) ; @@ -790,22 +796,22 @@ void *smem_alloc(unsigned id, unsigned size) return smem_find(id, size); } -void __iomem *smem_item(unsigned id, unsigned *size) +void *smem_item(unsigned id, unsigned *size) { struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE; struct smem_heap_entry *toc = shared->heap_toc; if (id >= SMEM_NUM_ITEMS) - return NULL; + return 0; if (toc[id].allocated) { *size = toc[id].size; - return (MSM_SHARED_RAM_BASE + toc[id].offset); + return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset); } else { *size = 0; } - return NULL; + return 0; } void *smem_find(unsigned id, unsigned size_in) @@ -851,7 +857,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data) int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask) { - void __iomem *addr = smd_info.state + item * 4; + unsigned long addr = smd_info.state + item * 4; unsigned long flags; unsigned state; @@ -937,10 +943,10 @@ int smd_core_init(void) /* wait for essential items to be initialized */ for (;;) { unsigned size; - void __iomem *state; + void *state; state = smem_item(SMEM_SMSM_SHARED_STATE, &size); if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) { - smd_info.state = state; + smd_info.state = (unsigned)state; break; } } diff --git a/trunk/arch/arm/mach-msm/timer.c b/trunk/arch/arm/mach-msm/timer.c index 004f93515a4e..812808254936 100644 --- a/trunk/arch/arm/mach-msm/timer.c +++ b/trunk/arch/arm/mach-msm/timer.c @@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = { static union { struct clock_event_device *evt; - struct clock_event_device * __percpu *percpu_evt; + struct clock_event_device __percpu **percpu_evt; } msm_evt; static void __iomem *source_base; diff --git a/trunk/arch/arm/mach-mv78xx0/addr-map.c b/trunk/arch/arm/mach-mv78xx0/addr-map.c index 137e479d15a0..62b53d710efd 100644 --- a/trunk/arch/arm/mach-mv78xx0/addr-map.c +++ b/trunk/arch/arm/mach-mv78xx0/addr-map.c @@ -13,7 +13,6 @@ #include #include #include -#include #include "common.h" /* @@ -38,7 +37,7 @@ #define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4)) #define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4)) -static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) +static void __init __iomem *win_cfg_base(int win) { /* * Find the control register base address for this window. @@ -82,7 +81,7 @@ void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, int maj, int min) { orion_setup_cpu_win(&addr_map_cfg, window, base, size, - TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0); + TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1); } void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, diff --git a/trunk/arch/arm/mach-mv78xx0/common.c b/trunk/arch/arm/mach-mv78xx0/common.c index 6b0c38735527..b4c53b846c9c 100644 --- a/trunk/arch/arm/mach-mv78xx0/common.c +++ b/trunk/arch/arm/mach-mv78xx0/common.c @@ -134,6 +134,11 @@ static struct map_desc mv78xx0_io_desc[] __initdata = { .pfn = 0, .length = MV78XX0_CORE_REGS_SIZE, .type = MT_DEVICE, + }, { + .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0), + .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)), + .length = MV78XX0_PCIE_IO_SIZE * 8, + .type = MT_DEVICE, }, { .virtual = MV78XX0_REGS_VIRT_BASE, .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), @@ -208,8 +213,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge00_init(eth_data, GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM, - IRQ_MV78XX0_GE_ERR, - MV643XX_TX_CSUM_DEFAULT_LIMIT); + IRQ_MV78XX0_GE_ERR); } @@ -220,8 +224,7 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data) { orion_ge01_init(eth_data, GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM, - NO_IRQ, - MV643XX_TX_CSUM_DEFAULT_LIMIT); + NO_IRQ); } diff --git a/trunk/arch/arm/mach-mv78xx0/include/mach/io.h b/trunk/arch/arm/mach-mv78xx0/include/mach/io.h new file mode 100644 index 000000000000..c7d9d00d8fc1 --- /dev/null +++ b/trunk/arch/arm/mach-mv78xx0/include/mach/io.h @@ -0,0 +1,24 @@ +/* + * arch/arm/mach-mv78xx0/include/mach/io.h + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ASM_ARCH_IO_H +#define __ASM_ARCH_IO_H + +#include "mv78xx0.h" + +#define IO_SPACE_LIMIT 0xffffffff + +static inline void __iomem *__io(unsigned long addr) +{ + return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0)) + + MV78XX0_PCIE_IO_VIRT_BASE(0)); +} + +#define __io(a) __io(a) + +#endif diff --git a/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index bd03fed1128e..e807c4c52a0b 100644 --- a/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/trunk/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h @@ -29,15 +29,15 @@ * * virt phys size * fe400000 f102x000 16K core-specific peripheral registers - * fee00000 f0800000 64K PCIe #0 I/O space - * fee10000 f0900000 64K PCIe #1 I/O space - * fee20000 f0a00000 64K PCIe #2 I/O space - * fee30000 f0b00000 64K PCIe #3 I/O space - * fee40000 f0c00000 64K PCIe #4 I/O space - * fee50000 f0d00000 64K PCIe #5 I/O space - * fee60000 f0e00000 64K PCIe #6 I/O space - * fee70000 f0f00000 64K PCIe #7 I/O space - * fd000000 f1000000 1M on-chip peripheral registers + * fe700000 f0800000 1M PCIe #0 I/O space + * fe800000 f0900000 1M PCIe #1 I/O space + * fe900000 f0a00000 1M PCIe #2 I/O space + * fea00000 f0b00000 1M PCIe #3 I/O space + * feb00000 f0c00000 1M PCIe #4 I/O space + * fec00000 f0d00000 1M PCIe #5 I/O space + * fed00000 f0e00000 1M PCIe #6 I/O space + * fee00000 f0f00000 1M PCIe #7 I/O space + * fef00000 f1000000 1M on-chip peripheral registers */ #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 @@ -46,10 +46,11 @@ #define MV78XX0_CORE_REGS_SIZE SZ_16K #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20)) +#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20)) #define MV78XX0_PCIE_IO_SIZE SZ_1M #define MV78XX0_REGS_PHYS_BASE 0xf1000000 -#define MV78XX0_REGS_VIRT_BASE 0xfd000000 +#define MV78XX0_REGS_VIRT_BASE 0xfef00000 #define MV78XX0_REGS_SIZE SZ_1M #define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 diff --git a/trunk/arch/arm/mach-mv78xx0/pcie.c b/trunk/arch/arm/mach-mv78xx0/pcie.c index 26a059b4f472..2e56e86b6d68 100644 --- a/trunk/arch/arm/mach-mv78xx0/pcie.c +++ b/trunk/arch/arm/mach-mv78xx0/pcie.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "common.h" struct pcie_port { @@ -24,13 +23,16 @@ struct pcie_port { u8 root_bus_nr; void __iomem *base; spinlock_t conf_lock; + char io_space_name[16]; char mem_space_name[16]; - struct resource res; + struct resource res[2]; }; static struct pcie_port pcie_port[8]; static int num_pcie_ports; static struct resource pcie_io_space; +static struct resource pcie_mem_space; + void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) { @@ -38,59 +40,102 @@ void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); } -u32 pcie_port_size[8] = { - 0, - 0x30000000, - 0x10000000, - 0x10000000, - 0x08000000, - 0x08000000, - 0x08000000, - 0x04000000, -}; - static void __init mv78xx0_pcie_preinit(void) { int i; u32 size_each; u32 start; - int win = 0; + int win; pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0); pcie_io_space.end = MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1; - pcie_io_space.flags = IORESOURCE_MEM; + pcie_io_space.flags = IORESOURCE_IO; if (request_resource(&iomem_resource, &pcie_io_space)) panic("can't allocate PCIe I/O space"); - if (num_pcie_ports > 7) - panic("invalid number of PCIe ports"); - - size_each = pcie_port_size[num_pcie_ports]; + pcie_mem_space.name = "PCIe MEM Space"; + pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE; + pcie_mem_space.end = + MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1; + pcie_mem_space.flags = IORESOURCE_MEM; + if (request_resource(&iomem_resource, &pcie_mem_space)) + panic("can't allocate PCIe MEM space"); - start = MV78XX0_PCIE_MEM_PHYS_BASE; for (i = 0; i < num_pcie_ports; i++) { struct pcie_port *pp = pcie_port + i; + snprintf(pp->io_space_name, sizeof(pp->io_space_name), + "PCIe %d.%d I/O", pp->maj, pp->min); + pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0; + pp->res[0].name = pp->io_space_name; + pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i); + pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1; + pp->res[0].flags = IORESOURCE_IO; + snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), "PCIe %d.%d MEM", pp->maj, pp->min); pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; - pp->res.name = pp->mem_space_name; - pp->res.flags = IORESOURCE_MEM; - pp->res.start = start; - pp->res.end = start + size_each - 1; + pp->res[1].name = pp->mem_space_name; + pp->res[1].flags = IORESOURCE_MEM; + } + + switch (num_pcie_ports) { + case 0: + size_each = 0; + break; + + case 1: + size_each = 0x30000000; + break; + + case 2 ... 3: + size_each = 0x10000000; + break; + + case 4 ... 6: + size_each = 0x08000000; + break; + + case 7: + size_each = 0x04000000; + break; + + default: + panic("invalid number of PCIe ports"); + } + + start = MV78XX0_PCIE_MEM_PHYS_BASE; + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; + + pp->res[1].start = start; + pp->res[1].end = start + size_each - 1; start += size_each; + } + + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; - if (request_resource(&iomem_resource, &pp->res)) + if (request_resource(&pcie_io_space, &pp->res[0])) + panic("can't allocate PCIe I/O sub-space"); + + if (request_resource(&pcie_mem_space, &pp->res[1])) panic("can't allocate PCIe MEM sub-space"); + } - mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start, - resource_size(&pp->res), - pp->maj, pp->min); + win = 0; + for (i = 0; i < num_pcie_ports; i++) { + struct pcie_port *pp = pcie_port + i; - mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K, + mv78xx0_setup_pcie_io_win(win++, pp->res[0].start, + resource_size(&pp->res[0]), pp->maj, pp->min); + + mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start, + resource_size(&pp->res[1]), + pp->maj, pp->min); } } @@ -111,9 +156,8 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys) orion_pcie_set_local_bus_nr(pp->base, sys->busnr); orion_pcie_setup(pp->base); - pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr)); - - pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); + pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset); + pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset); return 1; } @@ -237,7 +281,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base) pp->root_bus_nr = -1; pp->base = (void __iomem *)base; spin_lock_init(&pp->conf_lock); - memset(&pp->res, 0, sizeof(pp->res)); + memset(pp->res, 0, sizeof(pp->res)); } else { printk("link down, ignoring\n"); } diff --git a/trunk/arch/arm/mach-mxs/Kconfig b/trunk/arch/arm/mach-mxs/Kconfig index 9a8bbda195b2..ccdf83b17cf1 100644 --- a/trunk/arch/arm/mach-mxs/Kconfig +++ b/trunk/arch/arm/mach-mxs/Kconfig @@ -2,6 +2,9 @@ if ARCH_MXS source "arch/arm/mach-mxs/devices/Kconfig" +config MXS_OCOTP + bool + config SOC_IMX23 bool select ARM_AMBA @@ -63,6 +66,7 @@ config MACH_MX28EVK select MXS_HAVE_PLATFORM_MXS_SAIF select MXS_HAVE_PLATFORM_MXS_I2C select MXS_HAVE_PLATFORM_RTC_STMP3XXX + select MXS_OCOTP help Include support for MX28EVK platform. This includes specific configurations for the board and its peripherals. @@ -90,6 +94,7 @@ config MODULE_M28 select MXS_HAVE_PLATFORM_MXS_I2C select MXS_HAVE_PLATFORM_MXS_MMC select MXS_HAVE_PLATFORM_MXSFB + select MXS_OCOTP config MODULE_APX4 bool @@ -101,6 +106,7 @@ config MODULE_APX4 select MXS_HAVE_PLATFORM_MXS_I2C select MXS_HAVE_PLATFORM_MXS_MMC select MXS_HAVE_PLATFORM_MXS_SAIF + select MXS_OCOTP config MACH_TX28 bool "Ka-Ro TX28 module" diff --git a/trunk/arch/arm/mach-mxs/Makefile b/trunk/arch/arm/mach-mxs/Makefile index fed3695a1339..e41590ccb437 100644 --- a/trunk/arch/arm/mach-mxs/Makefile +++ b/trunk/arch/arm/mach-mxs/Makefile @@ -1,6 +1,7 @@ # Common support -obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o +obj-y := devices.o icoll.o iomux.o system.o timer.o mm.o +obj-$(CONFIG_MXS_OCOTP) += ocotp.o obj-$(CONFIG_PM) += pm.o obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o diff --git a/trunk/arch/arm/mach-mxs/mach-mxs.c b/trunk/arch/arm/mach-mxs/mach-mxs.c index ff886e01a0b0..8dabfe81d07c 100644 --- a/trunk/arch/arm/mach-mxs/mach-mxs.c +++ b/trunk/arch/arm/mach-mxs/mach-mxs.c @@ -261,7 +261,7 @@ static void __init apx4devkit_init(void) enable_clk_enet_out(); if (IS_BUILTIN(CONFIG_PHYLIB)) - phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK, + phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK, apx4devkit_phy_fixup); mxsfb_pdata.mode_list = apx4devkit_video_modes; diff --git a/trunk/arch/arm/mach-nomadik/board-nhk8815.c b/trunk/arch/arm/mach-nomadik/board-nhk8815.c index c3841a9a8fa8..f4535a7dadf5 100644 --- a/trunk/arch/arm/mach-nomadik/board-nhk8815.c +++ b/trunk/arch/arm/mach-nomadik/board-nhk8815.c @@ -112,7 +112,8 @@ static struct mtd_partition nhk8815_partitions[] = { static struct nomadik_nand_platform_data nhk8815_nand_data = { .parts = nhk8815_partitions, .nparts = ARRAY_SIZE(nhk8815_partitions), - .options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING, + .options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING \ + | NAND_NO_READRDY, .init = nhk8815_nand_init, }; diff --git a/trunk/arch/arm/mach-nomadik/include/mach/hardware.h b/trunk/arch/arm/mach-nomadik/include/mach/hardware.h index 02035e459f50..6316dba3bfc8 100644 --- a/trunk/arch/arm/mach-nomadik/include/mach/hardware.h +++ b/trunk/arch/arm/mach-nomadik/include/mach/hardware.h @@ -30,7 +30,7 @@ - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL) /* used in asm code, so no casts */ -#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL) +#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL) /* * Base address defination for Nomadik Onchip Logic Block diff --git a/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h b/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h index 7d4687e9cbdf..071003bc8456 100644 --- a/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h +++ b/trunk/arch/arm/mach-nomadik/include/mach/uncompress.h @@ -27,10 +27,10 @@ struct amba_device; #include -#define NOMADIK_UART_DR (void __iomem *)0x101FB000 -#define NOMADIK_UART_LCRH (void __iomem *)0x101FB02c -#define NOMADIK_UART_CR (void __iomem *)0x101FB030 -#define NOMADIK_UART_FR (void __iomem *)0x101FB018 +#define NOMADIK_UART_DR 0x101FB000 +#define NOMADIK_UART_LCRH 0x101FB02c +#define NOMADIK_UART_CR 0x101FB030 +#define NOMADIK_UART_FR 0x101FB018 static void putc(const char c) { diff --git a/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S index 3d1e1c250a1a..a051cb8ae57f 100644 --- a/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S +++ b/trunk/arch/arm/mach-omap1/ams-delta-fiq-handler.S @@ -16,9 +16,8 @@ #include #include -#include +#include -#include #include #include "iomap.h" diff --git a/trunk/arch/arm/mach-omap1/ams-delta-fiq.c b/trunk/arch/arm/mach-omap1/ams-delta-fiq.c index f12a12af3523..68e8e5654c0a 100644 --- a/trunk/arch/arm/mach-omap1/ams-delta-fiq.c +++ b/trunk/arch/arm/mach-omap1/ams-delta-fiq.c @@ -19,7 +19,7 @@ #include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/board-ams-delta.c b/trunk/arch/arm/mach-omap1/board-ams-delta.c index 9518bf5996dc..c53469802c03 100644 --- a/trunk/arch/arm/mach-omap1/board-ams-delta.c +++ b/trunk/arch/arm/mach-omap1/board-ams-delta.c @@ -26,7 +26,6 @@ #include #include #include -#include #include @@ -35,9 +34,10 @@ #include #include -#include -#include -#include +#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-fsample.c b/trunk/arch/arm/mach-omap1/board-fsample.c index 4b6de70c47a6..6872f3fd400f 100644 --- a/trunk/arch/arm/mach-omap1/board-fsample.c +++ b/trunk/arch/arm/mach-omap1/board-fsample.c @@ -28,10 +28,11 @@ #include #include -#include -#include +#include +#include #include -#include +#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/board-generic.c b/trunk/arch/arm/mach-omap1/board-generic.c index 4ec579fdd366..6ec385e2b98e 100644 --- a/trunk/arch/arm/mach-omap1/board-generic.c +++ b/trunk/arch/arm/mach-omap1/board-generic.c @@ -22,7 +22,8 @@ #include #include -#include +#include +#include #include @@ -51,6 +52,9 @@ static struct omap_usb_config generic1610_usb_config __initdata = { }; #endif +static struct omap_board_config_kernel generic_config[] __initdata = { +}; + static void __init omap_generic_init(void) { #ifdef CONFIG_ARCH_OMAP15XX @@ -72,6 +76,8 @@ static void __init omap_generic_init(void) } #endif + omap_board_config = generic_config; + omap_board_config_size = ARRAY_SIZE(generic_config); omap_serial_init(); omap_register_i2c_bus(1, 100, NULL, 0); } diff --git a/trunk/arch/arm/mach-omap1/board-h2.c b/trunk/arch/arm/mach-omap1/board-h2.c index af283a2bc7c7..44a4ab195fbc 100644 --- a/trunk/arch/arm/mach-omap1/board-h2.c +++ b/trunk/arch/arm/mach-omap1/board-h2.c @@ -31,18 +31,17 @@ #include #include #include -#include #include #include #include -#include +#include #include #include -#include -#include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-h3.c b/trunk/arch/arm/mach-omap1/board-h3.c index 06d11b1ee9c6..86cb5a04a404 100644 --- a/trunk/arch/arm/mach-omap1/board-h3.c +++ b/trunk/arch/arm/mach-omap1/board-h3.c @@ -31,7 +31,6 @@ #include #include #include -#include #include #include @@ -39,11 +38,11 @@ #include #include -#include +#include #include -#include +#include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-htcherald.c b/trunk/arch/arm/mach-omap1/board-htcherald.c index 87ab2086ef96..b3f6e943e661 100644 --- a/trunk/arch/arm/mach-omap1/board-htcherald.c +++ b/trunk/arch/arm/mach-omap1/board-htcherald.c @@ -37,12 +37,13 @@ #include #include #include -#include #include #include -#include +#include +#include +#include #include #include @@ -475,7 +476,8 @@ static void __init htcherald_lcd_init(void) break; } if (!tries) - pr_err("Timeout waiting for end of frame -- LCD may not be available\n"); + printk(KERN_WARNING "Timeout waiting for end of frame " + "-- LCD may not be available\n"); /* turn off DMA */ reg = omap_readw(OMAP_DMA_LCD_CCR); diff --git a/trunk/arch/arm/mach-omap1/board-innovator.c b/trunk/arch/arm/mach-omap1/board-innovator.c index db5f7d2976e7..f21c2966daad 100644 --- a/trunk/arch/arm/mach-omap1/board-innovator.c +++ b/trunk/arch/arm/mach-omap1/board-innovator.c @@ -31,11 +31,11 @@ #include #include -#include -#include +#include +#include #include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-nokia770.c b/trunk/arch/arm/mach-omap1/board-nokia770.c index 7d5c06d6a52a..2c0ca8fc3380 100644 --- a/trunk/arch/arm/mach-omap1/board-nokia770.c +++ b/trunk/arch/arm/mach-omap1/board-nokia770.c @@ -21,14 +21,14 @@ #include #include -#include -#include - #include #include #include -#include +#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-osk.c b/trunk/arch/arm/mach-omap1/board-osk.c index 2f1f9b967576..8784705edb60 100644 --- a/trunk/arch/arm/mach-omap1/board-osk.c +++ b/trunk/arch/arm/mach-omap1/board-osk.c @@ -39,15 +39,13 @@ #include #include #include -#include -#include #include #include #include -#include -#include +#include +#include #include #include @@ -304,7 +302,7 @@ static struct omap_lcd_config osk_lcd_config __initdata = { #include #include -#include +#include static struct at24_platform_data at24c04 = { .byte_len = SZ_4K / 8, diff --git a/trunk/arch/arm/mach-omap1/board-palmte.c b/trunk/arch/arm/mach-omap1/board-palmte.c index 1c578d58923a..26bcb9defcdc 100644 --- a/trunk/arch/arm/mach-omap1/board-palmte.c +++ b/trunk/arch/arm/mach-omap1/board-palmte.c @@ -28,18 +28,18 @@ #include #include #include -#include #include #include #include -#include -#include +#include +#include #include #include -#include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-palmtt.c b/trunk/arch/arm/mach-omap1/board-palmtt.c index 97158095083c..4d099446dfa8 100644 --- a/trunk/arch/arm/mach-omap1/board-palmtt.c +++ b/trunk/arch/arm/mach-omap1/board-palmtt.c @@ -27,19 +27,19 @@ #include #include #include -#include #include #include #include #include -#include -#include +#include +#include #include #include -#include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-palmz71.c b/trunk/arch/arm/mach-omap1/board-palmz71.c index e311032e7eeb..355980321c2d 100644 --- a/trunk/arch/arm/mach-omap1/board-palmz71.c +++ b/trunk/arch/arm/mach-omap1/board-palmz71.c @@ -30,18 +30,18 @@ #include #include #include -#include #include #include #include -#include -#include +#include +#include #include #include -#include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-perseus2.c b/trunk/arch/arm/mach-omap1/board-perseus2.c index 198b05417bfc..703d55ecffe2 100644 --- a/trunk/arch/arm/mach-omap1/board-perseus2.c +++ b/trunk/arch/arm/mach-omap1/board-perseus2.c @@ -22,16 +22,17 @@ #include #include #include -#include #include #include #include #include -#include +#include #include -#include +#include +#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/board-sx1-mmc.c b/trunk/arch/arm/mach-omap1/board-sx1-mmc.c index 5932d56e17bf..b59f78850e69 100644 --- a/trunk/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/trunk/arch/arm/mach-omap1/board-sx1-mmc.c @@ -17,7 +17,7 @@ #include #include -#include +#include #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) diff --git a/trunk/arch/arm/mach-omap1/board-sx1.c b/trunk/arch/arm/mach-omap1/board-sx1.c index 13bf2cc56814..8c665bd16ac2 100644 --- a/trunk/arch/arm/mach-omap1/board-sx1.c +++ b/trunk/arch/arm/mach-omap1/board-sx1.c @@ -28,18 +28,19 @@ #include #include #include -#include #include #include #include -#include -#include +#include +#include #include -#include +#include #include -#include +#include +#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/board-voiceblue.c b/trunk/arch/arm/mach-omap1/board-voiceblue.c index ad75e3411d46..3497769eb353 100644 --- a/trunk/arch/arm/mach-omap1/board-voiceblue.c +++ b/trunk/arch/arm/mach-omap1/board-voiceblue.c @@ -31,10 +31,11 @@ #include #include -#include -#include -#include +#include +#include +#include #include +#include #include #include @@ -154,6 +155,9 @@ static struct omap_usb_config voiceblue_usb_config __initdata = { .pins[2] = 6, }; +static struct omap_board_config_kernel voiceblue_config[] = { +}; + #define MACHINE_PANICED 1 #define MACHINE_REBOOTING 2 #define MACHINE_REBOOT 4 @@ -271,6 +275,8 @@ static void __init voiceblue_init(void) voiceblue_smc91x_resources[1].start = gpio_to_irq(8); voiceblue_smc91x_resources[1].end = gpio_to_irq(8); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); + omap_board_config = voiceblue_config; + omap_board_config_size = ARRAY_SIZE(voiceblue_config); omap_serial_init(); omap1_usb_init(&voiceblue_usb_config); omap_register_i2c_bus(1, 100, NULL, 0); diff --git a/trunk/arch/arm/mach-omap1/clock.c b/trunk/arch/arm/mach-omap1/clock.c index 638f4070fc70..a9ee06b6cb42 100644 --- a/trunk/arch/arm/mach-omap1/clock.c +++ b/trunk/arch/arm/mach-omap1/clock.c @@ -587,8 +587,8 @@ void omap1_clk_disable_unused(struct clk *clk) /* Clocks in the DSP domain need api_ck. Just assume bootloader * has not enabled any DSP clocks */ if (clk->enable_reg == DSP_IDLECT2) { - pr_info("Skipping reset check for DSP domain clock \"%s\"\n", - clk->name); + printk(KERN_INFO "Skipping reset check for DSP domain " + "clock \"%s\"\n", clk->name); return; } diff --git a/trunk/arch/arm/mach-omap1/clock_data.c b/trunk/arch/arm/mach-omap1/clock_data.c index 9b45f4b0ee22..c007d80dfb62 100644 --- a/trunk/arch/arm/mach-omap1/clock_data.c +++ b/trunk/arch/arm/mach-omap1/clock_data.c @@ -25,6 +25,7 @@ #include #include #include +#include #include /* for omap_sram_reprogram_clock() */ #include @@ -775,10 +776,11 @@ static struct clk_functions omap1_clk_functions = { static void __init omap1_show_rates(void) { - pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", - ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, - ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, - arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); + pr_notice("Clocking rate (xtal/DPLL1/MPU): " + "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", + ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, + ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, + arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); } u32 cpu_mask; @@ -786,6 +788,7 @@ u32 cpu_mask; int __init omap1_clk_init(void) { struct omap_clk *c; + const struct omap_clock_config *info; int crystal_type = 0; /* Default 12 MHz */ u32 reg; @@ -834,13 +837,19 @@ int __init omap1_clk_init(void) ck_dpll1_p = clk_get(NULL, "ck_dpll1"); ck_ref_p = clk_get(NULL, "ck_ref"); + info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); + if (info != NULL) { + if (!cpu_is_omap15xx()) + crystal_type = info->system_clock_type; + } + if (cpu_is_omap7xx()) ck_ref.rate = 13000000; if (cpu_is_omap16xx() && crystal_type == 2) ck_ref.rate = 19200000; - pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", - omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), + pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " + "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), omap_readw(ARM_CKCTL)); /* We want to be in syncronous scalable mode */ diff --git a/trunk/arch/arm/mach-omap1/devices.c b/trunk/arch/arm/mach-omap1/devices.c index 0cc54dd553e3..fa1fa4deb6aa 100644 --- a/trunk/arch/arm/mach-omap1/devices.c +++ b/trunk/arch/arm/mach-omap1/devices.c @@ -20,11 +20,12 @@ #include #include -#include +#include +#include #include #include +#include -#include #include #include diff --git a/trunk/arch/arm/mach-omap1/dma.c b/trunk/arch/arm/mach-omap1/dma.c index 29007fef84cd..3ef7d52316b4 100644 --- a/trunk/arch/arm/mach-omap1/dma.c +++ b/trunk/arch/arm/mach-omap1/dma.c @@ -27,8 +27,7 @@ #include #include - -#include +#include #define OMAP1_DMA_BASE (0xfffed800) #define OMAP1_LOGICAL_DMA_CH_COUNT 17 @@ -331,9 +330,8 @@ static int __init omap1_system_dma_init(void) d->chan = kzalloc(sizeof(struct omap_dma_lch) * (d->lch_count), GFP_KERNEL); if (!d->chan) { - dev_err(&pdev->dev, - "%s: Memory allocation failed for d->chan!\n", - __func__); + dev_err(&pdev->dev, "%s: Memory allocation failed" + "for d->chan!!!\n", __func__); goto exit_release_d; } diff --git a/trunk/arch/arm/mach-omap1/flash.c b/trunk/arch/arm/mach-omap1/flash.c index 73ae6169aa4a..401eb3c080c2 100644 --- a/trunk/arch/arm/mach-omap1/flash.c +++ b/trunk/arch/arm/mach-omap1/flash.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/gpio15xx.c b/trunk/arch/arm/mach-omap1/gpio15xx.c index 98e6f39224a4..ebef15e5e7b7 100644 --- a/trunk/arch/arm/mach-omap1/gpio15xx.c +++ b/trunk/arch/arm/mach-omap1/gpio15xx.c @@ -17,7 +17,6 @@ */ #include -#include #define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE #define OMAP1510_GPIO_BASE 0xFFFCE000 diff --git a/trunk/arch/arm/mach-omap1/gpio16xx.c b/trunk/arch/arm/mach-omap1/gpio16xx.c index 33f419236b17..2a48cd2e1754 100644 --- a/trunk/arch/arm/mach-omap1/gpio16xx.c +++ b/trunk/arch/arm/mach-omap1/gpio16xx.c @@ -17,7 +17,6 @@ */ #include -#include #define OMAP1610_GPIO1_BASE 0xfffbe400 #define OMAP1610_GPIO2_BASE 0xfffbec00 diff --git a/trunk/arch/arm/mach-omap1/gpio7xx.c b/trunk/arch/arm/mach-omap1/gpio7xx.c index 958ce9acee95..acf12b73eace 100644 --- a/trunk/arch/arm/mach-omap1/gpio7xx.c +++ b/trunk/arch/arm/mach-omap1/gpio7xx.c @@ -17,7 +17,6 @@ */ #include -#include #define OMAP7XX_GPIO1_BASE 0xfffbc000 #define OMAP7XX_GPIO2_BASE 0xfffbc800 diff --git a/trunk/arch/arm/mach-omap1/i2c.c b/trunk/arch/arm/mach-omap1/i2c.c index a0551a6d7451..5446c9912641 100644 --- a/trunk/arch/arm/mach-omap1/i2c.c +++ b/trunk/arch/arm/mach-omap1/i2c.c @@ -20,7 +20,7 @@ */ #include -#include +#include #include void __init omap1_i2c_mux_pins(int bus_id) diff --git a/trunk/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h b/trunk/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h index adb5e7649659..23eed0035ed8 100644 --- a/trunk/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h +++ b/trunk/arch/arm/mach-omap1/include/mach/ams-delta-fiq.h @@ -14,6 +14,8 @@ #ifndef __AMS_DELTA_FIQ_H #define __AMS_DELTA_FIQ_H +#include + /* * Interrupt number used for passing control from FIQ to IRQ. * IRQ12, described as reserved, has been selected. diff --git a/trunk/arch/arm/mach-omap1/include/mach/gpio.h b/trunk/arch/arm/mach-omap1/include/mach/gpio.h index ebf86c0f4f46..e737706a8fe1 100644 --- a/trunk/arch/arm/mach-omap1/include/mach/gpio.h +++ b/trunk/arch/arm/mach-omap1/include/mach/gpio.h @@ -1,3 +1,5 @@ /* * arch/arm/mach-omap1/include/mach/gpio.h */ + +#include diff --git a/trunk/arch/arm/mach-omap1/include/mach/hardware.h b/trunk/arch/arm/mach-omap1/include/mach/hardware.h index 84248d250adb..01e35fa106b8 100644 --- a/trunk/arch/arm/mach-omap1/include/mach/hardware.h +++ b/trunk/arch/arm/mach-omap1/include/mach/hardware.h @@ -1,46 +1,11 @@ /* * arch/arm/mach-omap1/include/mach/hardware.h - * - * Hardware definitions for TI OMAP processors and boards - * - * NOTE: Please put device driver specific defines into a separate header - * file for each driver. - * - * Copyright (C) 2001 RidgeRun, Inc. - * Author: RidgeRun, Inc. Greg Lonnon - * - * Reorganized for Linux-2.6 by Tony Lindgren - * and Dirk Behme - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#ifndef __ASM_ARCH_OMAP_HARDWARE_H -#define __ASM_ARCH_OMAP_HARDWARE_H +#ifndef __MACH_HARDWARE_H +#define __MACH_HARDWARE_H -#include #ifndef __ASSEMBLER__ -#include -#include - /* * NOTE: Please use ioremap + __raw_read/write where possible instead of these */ @@ -70,249 +35,7 @@ static inline u32 omap_cs3_phys(void) ? 0 : OMAP_CS3_PHYS; } -#endif /* ifndef __ASSEMBLER__ */ - -#include - -/* - * --------------------------------------------------------------------------- - * Common definitions for all OMAP processors - * NOTE: Put all processor or board specific parts to the special header - * files. - * --------------------------------------------------------------------------- - */ - -/* - * ---------------------------------------------------------------------------- - * Timers - * ---------------------------------------------------------------------------- - */ -#define OMAP_MPU_TIMER1_BASE (0xfffec500) -#define OMAP_MPU_TIMER2_BASE (0xfffec600) -#define OMAP_MPU_TIMER3_BASE (0xfffec700) -#define MPU_TIMER_FREE (1 << 6) -#define MPU_TIMER_CLOCK_ENABLE (1 << 5) -#define MPU_TIMER_AR (1 << 1) -#define MPU_TIMER_ST (1 << 0) - -/* - * ---------------------------------------------------------------------------- - * Clocks - * ---------------------------------------------------------------------------- - */ -#define CLKGEN_REG_BASE (0xfffece00) -#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) -#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) -#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) -#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) -#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) -#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) -#define ARM_SYSST (CLKGEN_REG_BASE + 0x18) -#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) - -#define CK_RATEF 1 -#define CK_IDLEF 2 -#define CK_ENABLEF 4 -#define CK_SELECTF 8 -#define SETARM_IDLE_SHIFT - -/* DPLL control registers */ -#define DPLL_CTL (0xfffecf00) - -/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */ -#define DSP_CONFIG_REG_BASE IOMEM(0xe1008000) -#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0) -#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) -#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) -#define DSP_RSTCT2 (DSP_CONFIG_REG_BASE + 0x14) - -/* - * --------------------------------------------------------------------------- - * UPLD - * --------------------------------------------------------------------------- - */ -#define ULPD_REG_BASE (0xfffe0800) -#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) -#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24) -#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) -# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ -# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ -#define ULPD_SOFT_REQ (ULPD_REG_BASE + 0x34) -# define SOFT_UDC_REQ (1 << 4) -# define SOFT_USB_CLK_REQ (1 << 3) -# define SOFT_DPLL_REQ (1 << 0) -#define ULPD_DPLL_CTRL (ULPD_REG_BASE + 0x3c) -#define ULPD_STATUS_REQ (ULPD_REG_BASE + 0x40) -#define ULPD_APLL_CTRL (ULPD_REG_BASE + 0x4c) -#define ULPD_POWER_CTRL (ULPD_REG_BASE + 0x50) -#define ULPD_SOFT_DISABLE_REQ_REG (ULPD_REG_BASE + 0x68) -# define DIS_MMC2_DPLL_REQ (1 << 11) -# define DIS_MMC1_DPLL_REQ (1 << 10) -# define DIS_UART3_DPLL_REQ (1 << 9) -# define DIS_UART2_DPLL_REQ (1 << 8) -# define DIS_UART1_DPLL_REQ (1 << 7) -# define DIS_USB_HOST_DPLL_REQ (1 << 6) -#define ULPD_SDW_CLK_DIV_CTRL_SEL (ULPD_REG_BASE + 0x74) -#define ULPD_CAM_CLK_CTRL (ULPD_REG_BASE + 0x7c) - -/* - * --------------------------------------------------------------------------- - * Watchdog timer - * --------------------------------------------------------------------------- - */ - -/* Watchdog timer within the OMAP3.2 gigacell */ -#define OMAP_MPU_WATCHDOG_BASE (0xfffec800) -#define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0) -#define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) -#define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4) -#define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8) - -/* - * --------------------------------------------------------------------------- - * Interrupts - * --------------------------------------------------------------------------- - */ -#ifdef CONFIG_ARCH_OMAP1 - -/* - * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c - * or something similar.. -- PFM. - */ - -#define OMAP_IH1_BASE 0xfffecb00 -#define OMAP_IH2_BASE 0xfffe0000 - -#define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) -#define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) -#define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10) -#define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14) -#define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18) -#define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c) -#define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c) - -#define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00) -#define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04) -#define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10) -#define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14) -#define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18) -#define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) -#define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) - -#define IRQ_ITR_REG_OFFSET 0x00 -#define IRQ_MIR_REG_OFFSET 0x04 -#define IRQ_SIR_IRQ_REG_OFFSET 0x10 -#define IRQ_SIR_FIQ_REG_OFFSET 0x14 -#define IRQ_CONTROL_REG_OFFSET 0x18 -#define IRQ_ISR_REG_OFFSET 0x9c -#define IRQ_ILR0_REG_OFFSET 0x1c -#define IRQ_GMR_REG_OFFSET 0xa0 - +#endif #endif -/* - * ---------------------------------------------------------------------------- - * System control registers - * ---------------------------------------------------------------------------- - */ -#define MOD_CONF_CTRL_0 0xfffe1080 -#define MOD_CONF_CTRL_1 0xfffe1110 - -/* - * ---------------------------------------------------------------------------- - * Pin multiplexing registers - * ---------------------------------------------------------------------------- - */ -#define FUNC_MUX_CTRL_0 0xfffe1000 -#define FUNC_MUX_CTRL_1 0xfffe1004 -#define FUNC_MUX_CTRL_2 0xfffe1008 -#define COMP_MODE_CTRL_0 0xfffe100c -#define FUNC_MUX_CTRL_3 0xfffe1010 -#define FUNC_MUX_CTRL_4 0xfffe1014 -#define FUNC_MUX_CTRL_5 0xfffe1018 -#define FUNC_MUX_CTRL_6 0xfffe101C -#define FUNC_MUX_CTRL_7 0xfffe1020 -#define FUNC_MUX_CTRL_8 0xfffe1024 -#define FUNC_MUX_CTRL_9 0xfffe1028 -#define FUNC_MUX_CTRL_A 0xfffe102C -#define FUNC_MUX_CTRL_B 0xfffe1030 -#define FUNC_MUX_CTRL_C 0xfffe1034 -#define FUNC_MUX_CTRL_D 0xfffe1038 -#define PULL_DWN_CTRL_0 0xfffe1040 -#define PULL_DWN_CTRL_1 0xfffe1044 -#define PULL_DWN_CTRL_2 0xfffe1048 -#define PULL_DWN_CTRL_3 0xfffe104c -#define PULL_DWN_CTRL_4 0xfffe10ac - -/* OMAP-1610 specific multiplexing registers */ -#define FUNC_MUX_CTRL_E 0xfffe1090 -#define FUNC_MUX_CTRL_F 0xfffe1094 -#define FUNC_MUX_CTRL_10 0xfffe1098 -#define FUNC_MUX_CTRL_11 0xfffe109c -#define FUNC_MUX_CTRL_12 0xfffe10a0 -#define PU_PD_SEL_0 0xfffe10b4 -#define PU_PD_SEL_1 0xfffe10b8 -#define PU_PD_SEL_2 0xfffe10bc -#define PU_PD_SEL_3 0xfffe10c0 -#define PU_PD_SEL_4 0xfffe10c4 - -/* Timer32K for 1610 and 1710*/ -#define OMAP_TIMER32K_BASE 0xFFFBC400 - -/* - * --------------------------------------------------------------------------- - * TIPB bus interface - * --------------------------------------------------------------------------- - */ -#define TIPB_PUBLIC_CNTL_BASE 0xfffed300 -#define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8) -#define TIPB_PRIVATE_CNTL_BASE 0xfffeca00 -#define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8) - -/* - * ---------------------------------------------------------------------------- - * MPUI interface - * ---------------------------------------------------------------------------- - */ -#define MPUI_BASE (0xfffec900) -#define MPUI_CTRL (MPUI_BASE + 0x0) -#define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4) -#define MPUI_DEBUG_DATA (MPUI_BASE + 0x8) -#define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc) -#define MPUI_STATUS_REG (MPUI_BASE + 0x10) -#define MPUI_DSP_STATUS (MPUI_BASE + 0x14) -#define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18) -#define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c) - -/* - * ---------------------------------------------------------------------------- - * LED Pulse Generator - * ---------------------------------------------------------------------------- - */ -#define OMAP_LPG1_BASE 0xfffbd000 -#define OMAP_LPG2_BASE 0xfffbd800 -#define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00) -#define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04) -#define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00) -#define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04) - -/* - * ---------------------------------------------------------------------------- - * Pulse-Width Light - * ---------------------------------------------------------------------------- - */ -#define OMAP_PWL_BASE 0xfffb5800 -#define OMAP_PWL_ENABLE (OMAP_PWL_BASE + 0x00) -#define OMAP_PWL_CLK_ENABLE (OMAP_PWL_BASE + 0x04) - -/* - * --------------------------------------------------------------------------- - * Processor specific defines - * --------------------------------------------------------------------------- - */ - -#include "omap7xx.h" -#include "omap1510.h" -#include "omap16xx.h" - -#endif /* __ASM_ARCH_OMAP_HARDWARE_H */ +#include diff --git a/trunk/arch/arm/mach-omap1/include/mach/irqs.h b/trunk/arch/arm/mach-omap1/include/mach/irqs.h index 729992d7d26a..9292fdc1cb0b 100644 --- a/trunk/arch/arm/mach-omap1/include/mach/irqs.h +++ b/trunk/arch/arm/mach-omap1/include/mach/irqs.h @@ -1,268 +1,5 @@ /* - * arch/arm/plat-omap/include/mach/irqs.h - * - * Copyright (C) Greg Lonnon 2001 - * Updated for OMAP-1610 by Tony Lindgren - * - * Copyright (C) 2009 Texas Instruments - * Added OMAP4 support - Santosh Shilimkar - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610 - * are different. + * arch/arm/mach-omap1/include/mach/irqs.h */ -#ifndef __ASM_ARCH_OMAP15XX_IRQS_H -#define __ASM_ARCH_OMAP15XX_IRQS_H - -/* - * IRQ numbers for interrupt handler 1 - * - * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below - * - */ -#define INT_CAMERA 1 -#define INT_FIQ 3 -#define INT_RTDX 6 -#define INT_DSP_MMU_ABORT 7 -#define INT_HOST 8 -#define INT_ABORT 9 -#define INT_BRIDGE_PRIV 13 -#define INT_GPIO_BANK1 14 -#define INT_UART3 15 -#define INT_TIMER3 16 -#define INT_DMA_CH0_6 19 -#define INT_DMA_CH1_7 20 -#define INT_DMA_CH2_8 21 -#define INT_DMA_CH3 22 -#define INT_DMA_CH4 23 -#define INT_DMA_CH5 24 -#define INT_TIMER1 26 -#define INT_WD_TIMER 27 -#define INT_BRIDGE_PUB 28 -#define INT_TIMER2 30 -#define INT_LCD_CTRL 31 - -/* - * OMAP-1510 specific IRQ numbers for interrupt handler 1 - */ -#define INT_1510_IH2_IRQ 0 -#define INT_1510_RES2 2 -#define INT_1510_SPI_TX 4 -#define INT_1510_SPI_RX 5 -#define INT_1510_DSP_MAILBOX1 10 -#define INT_1510_DSP_MAILBOX2 11 -#define INT_1510_RES12 12 -#define INT_1510_LB_MMU 17 -#define INT_1510_RES18 18 -#define INT_1510_LOCAL_BUS 29 - -/* - * OMAP-1610 specific IRQ numbers for interrupt handler 1 - */ -#define INT_1610_IH2_IRQ INT_1510_IH2_IRQ -#define INT_1610_IH2_FIQ 2 -#define INT_1610_McBSP2_TX 4 -#define INT_1610_McBSP2_RX 5 -#define INT_1610_DSP_MAILBOX1 10 -#define INT_1610_DSP_MAILBOX2 11 -#define INT_1610_LCD_LINE 12 -#define INT_1610_GPTIMER1 17 -#define INT_1610_GPTIMER2 18 -#define INT_1610_SSR_FIFO_0 29 - -/* - * OMAP-7xx specific IRQ numbers for interrupt handler 1 - */ -#define INT_7XX_IH2_FIQ 0 -#define INT_7XX_IH2_IRQ 1 -#define INT_7XX_USB_NON_ISO 2 -#define INT_7XX_USB_ISO 3 -#define INT_7XX_ICR 4 -#define INT_7XX_EAC 5 -#define INT_7XX_GPIO_BANK1 6 -#define INT_7XX_GPIO_BANK2 7 -#define INT_7XX_GPIO_BANK3 8 -#define INT_7XX_McBSP2TX 10 -#define INT_7XX_McBSP2RX 11 -#define INT_7XX_McBSP2RX_OVF 12 -#define INT_7XX_LCD_LINE 14 -#define INT_7XX_GSM_PROTECT 15 -#define INT_7XX_TIMER3 16 -#define INT_7XX_GPIO_BANK5 17 -#define INT_7XX_GPIO_BANK6 18 -#define INT_7XX_SPGIO_WR 29 - -/* - * IRQ numbers for interrupt handler 2 - * - * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below - */ -#define IH2_BASE 32 - -#define INT_KEYBOARD (1 + IH2_BASE) -#define INT_uWireTX (2 + IH2_BASE) -#define INT_uWireRX (3 + IH2_BASE) -#define INT_I2C (4 + IH2_BASE) -#define INT_MPUIO (5 + IH2_BASE) -#define INT_USB_HHC_1 (6 + IH2_BASE) -#define INT_McBSP3TX (10 + IH2_BASE) -#define INT_McBSP3RX (11 + IH2_BASE) -#define INT_McBSP1TX (12 + IH2_BASE) -#define INT_McBSP1RX (13 + IH2_BASE) -#define INT_UART1 (14 + IH2_BASE) -#define INT_UART2 (15 + IH2_BASE) -#define INT_BT_MCSI1TX (16 + IH2_BASE) -#define INT_BT_MCSI1RX (17 + IH2_BASE) -#define INT_SOSSI_MATCH (19 + IH2_BASE) -#define INT_USB_W2FC (20 + IH2_BASE) -#define INT_1WIRE (21 + IH2_BASE) -#define INT_OS_TIMER (22 + IH2_BASE) -#define INT_MMC (23 + IH2_BASE) -#define INT_GAUGE_32K (24 + IH2_BASE) -#define INT_RTC_TIMER (25 + IH2_BASE) -#define INT_RTC_ALARM (26 + IH2_BASE) -#define INT_MEM_STICK (27 + IH2_BASE) - -/* - * OMAP-1510 specific IRQ numbers for interrupt handler 2 - */ -#define INT_1510_DSP_MMU (28 + IH2_BASE) -#define INT_1510_COM_SPI_RO (31 + IH2_BASE) - -/* - * OMAP-1610 specific IRQ numbers for interrupt handler 2 - */ -#define INT_1610_FAC (0 + IH2_BASE) -#define INT_1610_USB_HHC_2 (7 + IH2_BASE) -#define INT_1610_USB_OTG (8 + IH2_BASE) -#define INT_1610_SoSSI (9 + IH2_BASE) -#define INT_1610_SoSSI_MATCH (19 + IH2_BASE) -#define INT_1610_DSP_MMU (28 + IH2_BASE) -#define INT_1610_McBSP2RX_OF (31 + IH2_BASE) -#define INT_1610_STI (32 + IH2_BASE) -#define INT_1610_STI_WAKEUP (33 + IH2_BASE) -#define INT_1610_GPTIMER3 (34 + IH2_BASE) -#define INT_1610_GPTIMER4 (35 + IH2_BASE) -#define INT_1610_GPTIMER5 (36 + IH2_BASE) -#define INT_1610_GPTIMER6 (37 + IH2_BASE) -#define INT_1610_GPTIMER7 (38 + IH2_BASE) -#define INT_1610_GPTIMER8 (39 + IH2_BASE) -#define INT_1610_GPIO_BANK2 (40 + IH2_BASE) -#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) -#define INT_1610_MMC2 (42 + IH2_BASE) -#define INT_1610_CF (43 + IH2_BASE) -#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE) -#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) -#define INT_1610_SPI (49 + IH2_BASE) -#define INT_1610_DMA_CH6 (53 + IH2_BASE) -#define INT_1610_DMA_CH7 (54 + IH2_BASE) -#define INT_1610_DMA_CH8 (55 + IH2_BASE) -#define INT_1610_DMA_CH9 (56 + IH2_BASE) -#define INT_1610_DMA_CH10 (57 + IH2_BASE) -#define INT_1610_DMA_CH11 (58 + IH2_BASE) -#define INT_1610_DMA_CH12 (59 + IH2_BASE) -#define INT_1610_DMA_CH13 (60 + IH2_BASE) -#define INT_1610_DMA_CH14 (61 + IH2_BASE) -#define INT_1610_DMA_CH15 (62 + IH2_BASE) -#define INT_1610_NAND (63 + IH2_BASE) -#define INT_1610_SHA1MD5 (91 + IH2_BASE) - -/* - * OMAP-7xx specific IRQ numbers for interrupt handler 2 - */ -#define INT_7XX_HW_ERRORS (0 + IH2_BASE) -#define INT_7XX_NFIQ_PWR_FAIL (1 + IH2_BASE) -#define INT_7XX_CFCD (2 + IH2_BASE) -#define INT_7XX_CFIREQ (3 + IH2_BASE) -#define INT_7XX_I2C (4 + IH2_BASE) -#define INT_7XX_PCC (5 + IH2_BASE) -#define INT_7XX_MPU_EXT_NIRQ (6 + IH2_BASE) -#define INT_7XX_SPI_100K_1 (7 + IH2_BASE) -#define INT_7XX_SYREN_SPI (8 + IH2_BASE) -#define INT_7XX_VLYNQ (9 + IH2_BASE) -#define INT_7XX_GPIO_BANK4 (10 + IH2_BASE) -#define INT_7XX_McBSP1TX (11 + IH2_BASE) -#define INT_7XX_McBSP1RX (12 + IH2_BASE) -#define INT_7XX_McBSP1RX_OF (13 + IH2_BASE) -#define INT_7XX_UART_MODEM_IRDA_2 (14 + IH2_BASE) -#define INT_7XX_UART_MODEM_1 (15 + IH2_BASE) -#define INT_7XX_MCSI (16 + IH2_BASE) -#define INT_7XX_uWireTX (17 + IH2_BASE) -#define INT_7XX_uWireRX (18 + IH2_BASE) -#define INT_7XX_SMC_CD (19 + IH2_BASE) -#define INT_7XX_SMC_IREQ (20 + IH2_BASE) -#define INT_7XX_HDQ_1WIRE (21 + IH2_BASE) -#define INT_7XX_TIMER32K (22 + IH2_BASE) -#define INT_7XX_MMC_SDIO (23 + IH2_BASE) -#define INT_7XX_UPLD (24 + IH2_BASE) -#define INT_7XX_USB_HHC_1 (27 + IH2_BASE) -#define INT_7XX_USB_HHC_2 (28 + IH2_BASE) -#define INT_7XX_USB_GENI (29 + IH2_BASE) -#define INT_7XX_USB_OTG (30 + IH2_BASE) -#define INT_7XX_CAMERA_IF (31 + IH2_BASE) -#define INT_7XX_RNG (32 + IH2_BASE) -#define INT_7XX_DUAL_MODE_TIMER (33 + IH2_BASE) -#define INT_7XX_DBB_RF_EN (34 + IH2_BASE) -#define INT_7XX_MPUIO_KEYPAD (35 + IH2_BASE) -#define INT_7XX_SHA1_MD5 (36 + IH2_BASE) -#define INT_7XX_SPI_100K_2 (37 + IH2_BASE) -#define INT_7XX_RNG_IDLE (38 + IH2_BASE) -#define INT_7XX_MPUIO (39 + IH2_BASE) -#define INT_7XX_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) -#define INT_7XX_LLPC_OE_FALLING (41 + IH2_BASE) -#define INT_7XX_LLPC_OE_RISING (42 + IH2_BASE) -#define INT_7XX_LLPC_VSYNC (43 + IH2_BASE) -#define INT_7XX_WAKE_UP_REQ (46 + IH2_BASE) -#define INT_7XX_DMA_CH6 (53 + IH2_BASE) -#define INT_7XX_DMA_CH7 (54 + IH2_BASE) -#define INT_7XX_DMA_CH8 (55 + IH2_BASE) -#define INT_7XX_DMA_CH9 (56 + IH2_BASE) -#define INT_7XX_DMA_CH10 (57 + IH2_BASE) -#define INT_7XX_DMA_CH11 (58 + IH2_BASE) -#define INT_7XX_DMA_CH12 (59 + IH2_BASE) -#define INT_7XX_DMA_CH13 (60 + IH2_BASE) -#define INT_7XX_DMA_CH14 (61 + IH2_BASE) -#define INT_7XX_DMA_CH15 (62 + IH2_BASE) -#define INT_7XX_NAND (63 + IH2_BASE) - -/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and - * 16 MPUIO lines */ -#define OMAP_MAX_GPIO_LINES 192 -#define IH_GPIO_BASE (128 + IH2_BASE) -#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) -#define OMAP_IRQ_END (IH_MPUIO_BASE + 16) - -/* External FPGA handles interrupts on Innovator boards */ -#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END) -#ifdef CONFIG_MACH_OMAP_INNOVATOR -#define OMAP_FPGA_NR_IRQS 24 -#else -#define OMAP_FPGA_NR_IRQS 0 -#endif -#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS) - -#define NR_IRQS OMAP_FPGA_IRQ_END - -#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) - -#include - -#ifdef CONFIG_FIQ -#define FIQ_START 1024 -#endif - -#endif +#include diff --git a/trunk/arch/arm/mach-omap1/include/mach/smp.h b/trunk/arch/arm/mach-omap1/include/mach/smp.h new file mode 100644 index 000000000000..80a371c06e59 --- /dev/null +++ b/trunk/arch/arm/mach-omap1/include/mach/smp.h @@ -0,0 +1,5 @@ +/* + * arch/arm/mach-omap1/include/mach/smp.h + */ + +#include diff --git a/trunk/arch/arm/mach-omap1/io.c b/trunk/arch/arm/mach-omap1/io.c index 6a5baab1f4cb..6c95a59f0f16 100644 --- a/trunk/arch/arm/mach-omap1/io.c +++ b/trunk/arch/arm/mach-omap1/io.c @@ -16,7 +16,7 @@ #include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/lcd_dma.c b/trunk/arch/arm/mach-omap1/lcd_dma.c index ed42628611bc..5769c71815b2 100644 --- a/trunk/arch/arm/mach-omap1/lcd_dma.c +++ b/trunk/arch/arm/mach-omap1/lcd_dma.c @@ -113,7 +113,8 @@ EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror); void omap_set_lcd_dma_b1_vxres(unsigned long vxres) { if (cpu_is_omap15xx()) { - pr_err("DMA virtual resolution is not supported in 1510 mode\n"); + printk(KERN_ERR "DMA virtual resolution is not supported " + "in 1510 mode\n"); BUG(); } lcd_dma.vxres = vxres; @@ -436,7 +437,8 @@ static int __init omap_init_lcd_dma(void) r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0, "LCD DMA", NULL); if (r != 0) - pr_err("unable to request IRQ for LCD DMA (error %d)\n", r); + printk(KERN_ERR "unable to request IRQ for LCD DMA " + "(error %d)\n", r); return r; } diff --git a/trunk/arch/arm/mach-omap1/leds-h2p2-debug.c b/trunk/arch/arm/mach-omap1/leds-h2p2-debug.c index 6f958aec9459..f6b14a14a957 100644 --- a/trunk/arch/arm/mach-omap1/leds-h2p2-debug.c +++ b/trunk/arch/arm/mach-omap1/leds-h2p2-debug.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include @@ -69,13 +68,11 @@ void h2p2_dbg_leds_event(led_event_t evt) gpio_set_value(GPIO_IDLE, 0); } + __raw_writew(~0, &fpga->leds); led_state &= ~LED_STATE_ENABLED; - if (fpga) { - __raw_writew(~0, &fpga->leds); - if (evt == led_halted) { - iounmap(fpga); - fpga = NULL; - } + if (evt == led_halted) { + iounmap(fpga); + fpga = NULL; } goto done; @@ -161,7 +158,7 @@ void h2p2_dbg_leds_event(led_event_t evt) /* * Actually burn the LEDs */ - if (led_state & LED_STATE_ENABLED && fpga) + if (led_state & LED_STATE_ENABLED) __raw_writew(~hw_led_state, &fpga->leds); done: diff --git a/trunk/arch/arm/mach-omap1/leds.c b/trunk/arch/arm/mach-omap1/leds.c index 4071479f7106..ae6dd93b8ddc 100644 --- a/trunk/arch/arm/mach-omap1/leds.c +++ b/trunk/arch/arm/mach-omap1/leds.c @@ -6,12 +6,11 @@ #include #include #include -#include #include #include -#include +#include #include "leds.h" diff --git a/trunk/arch/arm/mach-omap1/mcbsp.c b/trunk/arch/arm/mach-omap1/mcbsp.c index bdc2e7541adb..adf00975b9bb 100644 --- a/trunk/arch/arm/mach-omap1/mcbsp.c +++ b/trunk/arch/arm/mach-omap1/mcbsp.c @@ -20,9 +20,9 @@ #include #include -#include +#include #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap1/mux.c b/trunk/arch/arm/mach-omap1/mux.c index 667ce5027f63..e9cc52d4cb28 100644 --- a/trunk/arch/arm/mach-omap1/mux.c +++ b/trunk/arch/arm/mach-omap1/mux.c @@ -29,7 +29,7 @@ #include -#include +#include #ifdef CONFIG_OMAP_MUX @@ -451,56 +451,6 @@ static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) #endif } -static struct omap_mux_cfg *mux_cfg; - -int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) -{ - if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0 - || !arch_mux_cfg->cfg_reg) { - printk(KERN_ERR "Invalid pin table\n"); - return -EINVAL; - } - - mux_cfg = arch_mux_cfg; - - return 0; -} - -/* - * Sets the Omap MUX and PULL_DWN registers based on the table - */ -int __init_or_module omap_cfg_reg(const unsigned long index) -{ - struct pin_config *reg; - - if (!cpu_class_is_omap1()) { - printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", - index); - WARN_ON(1); - return -EINVAL; - } - - if (mux_cfg == NULL) { - printk(KERN_ERR "Pin mux table not initialized\n"); - return -ENODEV; - } - - if (index >= mux_cfg->size) { - printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", - index, mux_cfg->size); - dump_stack(); - return -ENODEV; - } - - reg = &mux_cfg->pins[index]; - - if (!mux_cfg->cfg_reg) - return -ENODEV; - - return mux_cfg->cfg_reg(reg); -} -EXPORT_SYMBOL(omap_cfg_reg); - int __init omap1_mux_init(void) { if (cpu_is_omap7xx()) { @@ -518,8 +468,4 @@ int __init omap1_mux_init(void) return omap_mux_register(&arch_mux_cfg); } -#else -#define omap_mux_init() do {} while(0) -#define omap_cfg_reg(x) do {} while(0) -#endif /* CONFIG_OMAP_MUX */ - +#endif diff --git a/trunk/arch/arm/mach-omap1/pm.c b/trunk/arch/arm/mach-omap1/pm.c index 47ec16155483..b2560d32b3a0 100644 --- a/trunk/arch/arm/mach-omap1/pm.c +++ b/trunk/arch/arm/mach-omap1/pm.c @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include diff --git a/trunk/arch/arm/mach-omap1/serial.c b/trunk/arch/arm/mach-omap1/serial.c index b9d6834af835..6809c9e56c93 100644 --- a/trunk/arch/arm/mach-omap1/serial.c +++ b/trunk/arch/arm/mach-omap1/serial.c @@ -22,7 +22,8 @@ #include -#include +#include +#include #include #include "pm.h" diff --git a/trunk/arch/arm/mach-omap1/usb.c b/trunk/arch/arm/mach-omap1/usb.c index 84267edd9421..65f88176fba8 100644 --- a/trunk/arch/arm/mach-omap1/usb.c +++ b/trunk/arch/arm/mach-omap1/usb.c @@ -26,7 +26,7 @@ #include -#include +#include #include diff --git a/trunk/arch/arm/mach-omap2/Kconfig b/trunk/arch/arm/mach-omap2/Kconfig index 346fd26f3aa6..dd2db025f778 100644 --- a/trunk/arch/arm/mach-omap2/Kconfig +++ b/trunk/arch/arm/mach-omap2/Kconfig @@ -62,14 +62,13 @@ config ARCH_OMAP4 select PM_OPP if PM select USB_ARCH_HAS_EHCI if USB_SUPPORT select ARM_CPU_SUSPEND if PM - select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP + select ARCH_NEEDS_CPU_IDLE_COUPLED config SOC_OMAP5 bool "TI OMAP5" select CPU_V7 select ARM_GIC select HAVE_SMP - select ARM_CPU_SUSPEND if PM comment "OMAP Core Type" depends on ARCH_OMAP2 @@ -232,11 +231,10 @@ config MACH_OMAP3_PANDORA select OMAP_PACKAGE_CBB select REGULATOR_FIXED_VOLTAGE if REGULATOR -config MACH_TOUCHBOOK +config MACH_OMAP3_TOUCHBOOK bool "OMAP3 Touch Book" depends on ARCH_OMAP3 default y - select OMAP_PACKAGE_CBB config MACH_OMAP_3430SDP bool "OMAP 3430 SDP board" diff --git a/trunk/arch/arm/mach-omap2/Makefile b/trunk/arch/arm/mach-omap2/Makefile index 7706fdfd0252..f6a24b3f9c4f 100644 --- a/trunk/arch/arm/mach-omap2/Makefile +++ b/trunk/arch/arm/mach-omap2/Makefile @@ -4,30 +4,36 @@ # Common support obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ - common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o + common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o -# INTCPS IP block support - XXX should be moved to drivers/ -obj-$(CONFIG_ARCH_OMAP2) += irq.o -obj-$(CONFIG_ARCH_OMAP3) += irq.o -obj-$(CONFIG_SOC_AM33XX) += irq.o +omap-2-3-common = irq.o +hwmod-common = omap_hwmod.o \ + omap_hwmod_common_data.o +clock-common = clock.o clock_common_data.o \ + clkt_dpll.o clkt_clksel.o +secure-common = omap-smc.o omap-secure.o -# Secure monitor API support -obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o -obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o -obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o +obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) +obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) +obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) +obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o endif -obj-$(CONFIG_TWL4030_CORE) += omap_twl.o +obj-$(CONFIG_TWL4030_CORE) += omap_twl.o +obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # SMP support ONLY available for OMAP4 obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o -obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o -obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o +omap-4-5-common = omap4-common.o omap-wakeupgen.o \ + sleep44xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) +obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -52,7 +58,6 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o -obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o # OPP table initialization ifeq ($(CONFIG_PM_OPP),y) @@ -63,15 +68,15 @@ endif # Power Management ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o +obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o +obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o -obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o -obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o +obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o -obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o +obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o AFLAGS_sleep24xx.o :=-Wa,-march=armv6 AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) @@ -83,76 +88,92 @@ endif endif ifeq ($(CONFIG_CPU_IDLE),y) -obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o -obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o +obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o +obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o endif # PRCM -obj-y += prcm.o prm_common.o -obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o -obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o -obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o -omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ +omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \ prcm_mpu44xx.o prminst44xx.o \ - vc44xx_data.o vp44xx_data.o \ - prm44xx.o -obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) + vc44xx_data.o vp44xx_data.o +obj-y += prm_common.o +obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o +obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o +obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) # OMAP voltage domains -obj-y += voltage.o vc.o vp.o +voltagedomain-common := voltage.o vc.o vp.o +obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common) obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o -obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common) +obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common) # OMAP powerdomain framework -obj-y += powerdomain.o powerdomain-common.o +powerdomain-common += powerdomain.o powerdomain-common.o +obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common) obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common) obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o # PRCM clockdomain control -obj-y += clockdomain.o +clockdomain-common += clockdomain.o +obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o +obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o +obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common) obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common) obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o # Clock framework -obj-y += clock.o clock_common_data.o \ - clkt_dpll.o clkt_clksel.o -obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o -obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o +obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o +obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o -obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o -obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o +obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o -obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o +obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o +obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o -obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o +obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o +obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o +obj-$(CONFIG_SOC_OMAP5) += $(clock-common) obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o # OMAP2 clock rate set data (old "OPP" data) @@ -160,7 +181,6 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o # hwmod data -obj-y += omap_hwmod_common_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o @@ -209,10 +229,10 @@ obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o -obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o +obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o -obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o -obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o +obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o obj-$(CONFIG_MACH_OVERO) += board-overo.o obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o @@ -235,7 +255,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP) += board-zoom-display.o obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o obj-$(CONFIG_MACH_CM_T3517) += board-cm-t3517.o obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o -obj-$(CONFIG_MACH_TOUCHBOOK) += board-omap3touchbook.o +obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o diff --git a/trunk/arch/arm/mach-omap2/am35xx-emac.c b/trunk/arch/arm/mach-omap2/am35xx-emac.c index d0c54c573d34..2c90ac686686 100644 --- a/trunk/arch/arm/mach-omap2/am35xx-emac.c +++ b/trunk/arch/arm/mach-omap2/am35xx-emac.c @@ -19,7 +19,7 @@ #include #include #include -#include "am35xx.h" +#include #include "control.h" #include "am35xx-emac.h" diff --git a/trunk/arch/arm/mach-omap2/board-2430sdp.c b/trunk/arch/arm/mach-omap2/board-2430sdp.c index 95b384d54f8a..9511584fdc4f 100644 --- a/trunk/arch/arm/mach-omap2/board-2430sdp.c +++ b/trunk/arch/arm/mach-omap2/board-2430sdp.c @@ -33,10 +33,11 @@ #include #include +#include #include "common.h" #include #include -#include "gpmc-smc91x.h" +#include #include