From 80f27bf6fba2b2e5d17a28f1fdb81a5593377d21 Mon Sep 17 00:00:00 2001 From: Changhwan Youn Date: Sat, 16 Jul 2011 10:49:47 +0900 Subject: [PATCH] --- yaml --- r: 260618 b: refs/heads/master c: e807acbc6fd1d5ff115f9a8eae0c1af6cf1c46c6 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/common/gic.c | 6 ------ trunk/arch/arm/include/asm/hardware/gic.h | 6 ++++++ 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/[refs] b/[refs] index ed70accdf4df..c61052118f65 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a8769a594a6d061f8018048a7cd1546924c61a5c +refs/heads/master: e807acbc6fd1d5ff115f9a8eae0c1af6cf1c46c6 diff --git a/trunk/arch/arm/common/gic.c b/trunk/arch/arm/common/gic.c index 4ddd0a6ac7ff..23564edbd849 100644 --- a/trunk/arch/arm/common/gic.c +++ b/trunk/arch/arm/common/gic.c @@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock); /* Address of GIC 0 CPU interface */ void __iomem *gic_cpu_base_addr __read_mostly; -struct gic_chip_data { - unsigned int irq_offset; - void __iomem *dist_base; - void __iomem *cpu_base; -}; - /* * Supported arch specific GIC irq extension. * Default make them NULL. diff --git a/trunk/arch/arm/include/asm/hardware/gic.h b/trunk/arch/arm/include/asm/hardware/gic.h index 0691f9dcc500..435d3f86c708 100644 --- a/trunk/arch/arm/include/asm/hardware/gic.h +++ b/trunk/arch/arm/include/asm/hardware/gic.h @@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int); void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); void gic_enable_ppi(unsigned int); + +struct gic_chip_data { + unsigned int irq_offset; + void __iomem *dist_base; + void __iomem *cpu_base; +}; #endif #endif