From 8174c8ba51dbe678b1da93232c373a856432fc8d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 26 Sep 2012 14:37:51 +1000 Subject: [PATCH] --- yaml --- r: 329687 b: refs/heads/master c: dc73b45ad456b173610a211c588d003f7ea77957 h: refs/heads/master i: 329685: ac9266d2cb836db016ecf41d92e6a80e07c19ae2 329683: 6c22378720d92c759c90ff60ddf3185a394d8180 329679: 2a971e1d8654bf4ba6abe4295b5e0a44a3c940a5 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/core/include/subdev/vm.h | 1 + trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c | 1 + trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c | 1 + trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c | 1 + trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c | 1 + trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c | 1 + trunk/drivers/gpu/drm/nouveau/nouveau_ttm.c | 10 +++------- 8 files changed, 10 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index 2404a715243f..062276421e29 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c0abf5c9fa1db7188bd6b8b580614a377dbc7080 +refs/heads/master: dc73b45ad456b173610a211c588d003f7ea77957 diff --git a/trunk/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/trunk/drivers/gpu/drm/nouveau/core/include/subdev/vm.h index 66a4473f3a54..9d595efe667a 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/include/subdev/vm.h +++ b/trunk/drivers/gpu/drm/nouveau/core/include/subdev/vm.h @@ -69,6 +69,7 @@ struct nouveau_vmmgr { struct nouveau_subdev base; u64 limit; + u8 dma_bits; u32 pgt_bits; u8 spg_shift; u8 lpg_shift; diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c index bfe6766d36ec..ad6ad5de51b8 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c @@ -97,6 +97,7 @@ nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV04_PDMA_SIZE; + priv->base.dma_bits = 32; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c index bbeac8d296ed..c5486e4bffa6 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c @@ -98,6 +98,7 @@ nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV41_GART_SIZE; + priv->base.dma_bits = 39; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c index d099cde3a7f5..8c9cece25e63 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c @@ -179,6 +179,7 @@ nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.create = nv04_vm_create; priv->base.limit = NV44_GART_SIZE; + priv->base.dma_bits = 39; priv->base.pgt_bits = 32 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 12; diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c index d83489c44c3a..e067f81c97b3 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c @@ -201,6 +201,7 @@ nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.limit = 1ULL << 40; + priv->base.dma_bits = 40; priv->base.pgt_bits = 29 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 16; diff --git a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c index 44721a4714d1..30c61e6c2017 100644 --- a/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c +++ b/trunk/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c @@ -163,6 +163,7 @@ nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return ret; priv->base.limit = 1ULL << 40; + priv->base.dma_bits = 40; priv->base.pgt_bits = 27 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 17; diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_ttm.c b/trunk/drivers/gpu/drm/nouveau/nouveau_ttm.c index d2fc121ff861..9be9cb58e19b 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -340,14 +340,10 @@ nouveau_ttm_init(struct nouveau_drm *drm) u32 bits; int ret; - if (nv_device(drm->device)->card_type >= NV_50) { - if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40))) - bits = 40; - else - bits = 32; - } else { + bits = nouveau_vmmgr(drm->device)->dma_bits; + if ( drm->agp.stat == ENABLED || + !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) bits = 32; - } ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits)); if (ret)