From 6fe9cbd1119b3cd2595dabaf25a400eed95b170c Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Wed, 13 Jun 2012 18:58:09 +0200 Subject: [PATCH 1/9] clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver Timer 0 is used as free-running clocksource, while timer 1 is used as clock_event_device. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem Reviewed-by: Thomas Gleixner Tested-by: Yehuda Yitschak Tested-by: Lior Amsalem Acked-by: Andrew Lunn CC: Thomas Gleixner CC: John Stultz --- drivers/clocksource/Kconfig | 3 + drivers/clocksource/Makefile | 3 +- drivers/clocksource/time-armada-370-xp.c | 226 +++++++++++++++++++++++ include/linux/time-armada-370-xp.h | 18 ++ 4 files changed, 249 insertions(+), 1 deletion(-) create mode 100644 drivers/clocksource/time-armada-370-xp.c create mode 100644 include/linux/time-armada-370-xp.h diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 99c6b203e6cd..b32363173584 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -16,6 +16,9 @@ config CLKSRC_MMIO config DW_APB_TIMER bool +config ARMADA_370_XP_TIMER + bool + config CLKSRC_DBX500_PRCMU bool "Clocksource PRCMU Timer" depends on UX500_SOC_DB8500 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dd3e661a124d..022015cbee48 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -10,4 +10,5 @@ obj-$(CONFIG_EM_TIMER_STI) += em_sti.o obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o -obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o \ No newline at end of file +obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o +obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c new file mode 100644 index 000000000000..4674f94957cd --- /dev/null +++ b/drivers/clocksource/time-armada-370-xp.c @@ -0,0 +1,226 @@ +/* + * Marvell Armada 370/XP SoC timer handling. + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Timer 0 is used as free-running clocksource, while timer 1 is + * used as clock_event_device. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Timer block registers. + */ +#define TIMER_CTRL_OFF 0x0000 +#define TIMER0_EN 0x0001 +#define TIMER0_RELOAD_EN 0x0002 +#define TIMER0_25MHZ 0x0800 +#define TIMER0_DIV(div) ((div) << 19) +#define TIMER1_EN 0x0004 +#define TIMER1_RELOAD_EN 0x0008 +#define TIMER1_25MHZ 0x1000 +#define TIMER1_DIV(div) ((div) << 22) +#define TIMER_EVENTS_STATUS 0x0004 +#define TIMER0_CLR_MASK (~0x1) +#define TIMER1_CLR_MASK (~0x100) +#define TIMER0_RELOAD_OFF 0x0010 +#define TIMER0_VAL_OFF 0x0014 +#define TIMER1_RELOAD_OFF 0x0018 +#define TIMER1_VAL_OFF 0x001c + +/* Global timers are connected to the coherency fabric clock, and the + below divider reduces their incrementing frequency. */ +#define TIMER_DIVIDER_SHIFT 5 +#define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT) + +/* + * SoC-specific data. + */ +static void __iomem *timer_base; +static int timer_irq; + +/* + * Number of timer ticks per jiffy. + */ +static u32 ticks_per_jiffy; + +static u32 notrace armada_370_xp_read_sched_clock(void) +{ + return ~readl(timer_base + TIMER0_VAL_OFF); +} + +/* + * Clockevent handling. + */ +static int +armada_370_xp_clkevt_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + u32 u; + + /* + * Clear clockevent timer interrupt. + */ + writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS); + + /* + * Setup new clockevent timer value. + */ + writel(delta, timer_base + TIMER1_VAL_OFF); + + /* + * Enable the timer. + */ + u = readl(timer_base + TIMER_CTRL_OFF); + u = ((u & ~TIMER1_RELOAD_EN) | TIMER1_EN | + TIMER1_DIV(TIMER_DIVIDER_SHIFT)); + writel(u, timer_base + TIMER_CTRL_OFF); + + return 0; +} + +static void +armada_370_xp_clkevt_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ + u32 u; + + if (mode == CLOCK_EVT_MODE_PERIODIC) { + /* + * Setup timer to fire at 1/HZ intervals. + */ + writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); + writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); + + /* + * Enable timer. + */ + u = readl(timer_base + TIMER_CTRL_OFF); + + writel((u | TIMER1_EN | TIMER1_RELOAD_EN | + TIMER1_DIV(TIMER_DIVIDER_SHIFT)), + timer_base + TIMER_CTRL_OFF); + } else { + /* + * Disable timer. + */ + u = readl(timer_base + TIMER_CTRL_OFF); + writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); + + /* + * ACK pending timer interrupt. + */ + writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS); + + } +} + +static struct clock_event_device armada_370_xp_clkevt = { + .name = "armada_370_xp_tick", + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .shift = 32, + .rating = 300, + .set_next_event = armada_370_xp_clkevt_next_event, + .set_mode = armada_370_xp_clkevt_mode, +}; + +static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id) +{ + /* + * ACK timer interrupt and call event handler. + */ + + writel(TIMER1_CLR_MASK, timer_base + TIMER_EVENTS_STATUS); + armada_370_xp_clkevt.event_handler(&armada_370_xp_clkevt); + + return IRQ_HANDLED; +} + +static struct irqaction armada_370_xp_timer_irq = { + .name = "armada_370_xp_tick", + .flags = IRQF_DISABLED | IRQF_TIMER, + .handler = armada_370_xp_timer_interrupt +}; + +void __init armada_370_xp_timer_init(void) +{ + u32 u; + struct device_node *np; + unsigned int timer_clk; + int ret; + np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer"); + timer_base = of_iomap(np, 0); + WARN_ON(!timer_base); + + if (of_find_property(np, "marvell,timer-25Mhz", NULL)) { + /* The fixed 25MHz timer is available so let's use it */ + u = readl(timer_base + TIMER_CTRL_OFF); + writel(u | TIMER0_25MHZ | TIMER1_25MHZ, + timer_base + TIMER_CTRL_OFF); + timer_clk = 25000000; + } else { + u32 clk = 0; + ret = of_property_read_u32(np, "clock-frequency", &clk); + WARN_ON(!clk || ret < 0); + u = readl(timer_base + TIMER_CTRL_OFF); + writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ), + timer_base + TIMER_CTRL_OFF); + timer_clk = clk / TIMER_DIVIDER; + } + + /* We use timer 0 as clocksource, and timer 1 for + clockevents */ + timer_irq = irq_of_parse_and_map(np, 1); + + ticks_per_jiffy = (timer_clk + HZ / 2) / HZ; + + /* + * Set scale and timer for sched_clock. + */ + setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk); + + /* + * Setup free-running clocksource timer (interrupts + * disabled). + */ + writel(0xffffffff, timer_base + TIMER0_VAL_OFF); + writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); + + u = readl(timer_base + TIMER_CTRL_OFF); + + writel((u | TIMER0_EN | TIMER0_RELOAD_EN | + TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF); + + clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, + "armada_370_xp_clocksource", + timer_clk, 300, 32, clocksource_mmio_readl_down); + + /* + * Setup clockevent timer (interrupt-driven). + */ + setup_irq(timer_irq, &armada_370_xp_timer_irq); + armada_370_xp_clkevt.cpumask = cpumask_of(0); + clockevents_config_and_register(&armada_370_xp_clkevt, + timer_clk, 1, 0xfffffffe); +} + diff --git a/include/linux/time-armada-370-xp.h b/include/linux/time-armada-370-xp.h new file mode 100644 index 000000000000..dfdfdc03115b --- /dev/null +++ b/include/linux/time-armada-370-xp.h @@ -0,0 +1,18 @@ +/* + * Marvell Armada 370/XP SoC timer handling. + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + */ +#ifndef __TIME_ARMADA_370_XPPRCMU_H +#define __TIME_ARMADA_370_XPPRCMU_H + +#include + +void __init armada_370_xp_timer_init(void); + +#endif From bf54439c34689f53409a066452e58a0533880473 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 1 Jun 2012 18:37:19 +0200 Subject: [PATCH 2/9] arm: mach-mvebu: add header Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem Acked-by: Andrew Lunn Tested-by: Yehuda Yitschak Tested-by: Lior Amsalem --- .../arm/mach-mvebu/include/mach/debug-macro.S | 24 +++++++++++ arch/arm/mach-mvebu/include/mach/timex.h | 13 ++++++ arch/arm/mach-mvebu/include/mach/uncompress.h | 43 +++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 arch/arm/mach-mvebu/include/mach/debug-macro.S create mode 100644 arch/arm/mach-mvebu/include/mach/timex.h create mode 100644 arch/arm/mach-mvebu/include/mach/uncompress.h diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/mach-mvebu/include/mach/debug-macro.S new file mode 100644 index 000000000000..22825760c7e1 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/debug-macro.S @@ -0,0 +1,24 @@ +/* + * Early serial output macro for Marvell SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory Clement + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include + + .macro addruart, rp, rv, tmp + ldr \rp, =ARMADA_370_XP_REGS_PHYS_BASE + ldr \rv, =ARMADA_370_XP_REGS_VIRT_BASE + orr \rp, \rp, #0x00012000 + orr \rv, \rv, #0x00012000 + .endm + +#define UART_SHIFT 2 +#include diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h new file mode 100644 index 000000000000..ab324a3748f2 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/timex.h @@ -0,0 +1,13 @@ +/* + * Marvell Armada SoC time definitions + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define CLOCK_TICK_RATE (100 * HZ) diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h new file mode 100644 index 000000000000..d6a100ccf302 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/uncompress.h @@ -0,0 +1,43 @@ +/* + * Marvell Armada SoC kernel uncompression UART routines + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include + +#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\ + + 0x12000)) +#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\ + + 0x12014)) + +#define LSR_THRE 0x20 + +static void putc(const char c) +{ + int i; + + for (i = 0; i < 0x1000; i++) { + /* Transmit fifo not full? */ + if (*UART_LSR & LSR_THRE) + break; + } + + *UART_THR = c; +} + +static void flush(void) +{ +} + +/* + * nothing to do + */ +#define arch_decomp_setup() +#define arch_decomp_wdog() From 31af49db7b2d700fdaf26ab55ca96428bc2e8b06 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 1 Jun 2012 18:21:46 +0200 Subject: [PATCH 3/9] arm: mach-mvebu: add source files [ben.dooks@codethink.co.uk: fixup style error in system-controller] [ben.dooks@codethink.co.uk: check result of of_match_node()] Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem Acked-by: Andrew Lunn Tested-by: Yehuda Yitschak Tested-by: Lior Amsalem Tested-by: Andrew Lunn --- arch/arm/mach-mvebu/Kconfig | 7 ++ arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/Makefile.boot | 1 + arch/arm/mach-mvebu/common.h | 20 +++++ arch/arm/mach-mvebu/system-controller.c | 105 ++++++++++++++++++++++++ 5 files changed, 134 insertions(+) create mode 100644 arch/arm/mach-mvebu/Kconfig create mode 100644 arch/arm/mach-mvebu/Makefile create mode 100644 arch/arm/mach-mvebu/Makefile.boot create mode 100644 arch/arm/mach-mvebu/common.h create mode 100644 arch/arm/mach-mvebu/system-controller.c diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig new file mode 100644 index 000000000000..72d39e5c0ff4 --- /dev/null +++ b/arch/arm/mach-mvebu/Kconfig @@ -0,0 +1,7 @@ +if ARCH_MVEBU + +menu "Marvell SOC with device tree" + +endmenu + +endif diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile new file mode 100644 index 000000000000..7366ae7357f3 --- /dev/null +++ b/arch/arm/mach-mvebu/Makefile @@ -0,0 +1 @@ +obj-y += system-controller.o diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot new file mode 100644 index 000000000000..b3271754e9fd --- /dev/null +++ b/arch/arm/mach-mvebu/Makefile.boot @@ -0,0 +1 @@ +zreladdr-y := 0x00008000 diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h new file mode 100644 index 000000000000..f0eaa215e629 --- /dev/null +++ b/arch/arm/mach-mvebu/common.h @@ -0,0 +1,20 @@ +/* + * Core functions for Marvell System On Chip + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __ARCH_MVEBU_COMMON_H +#define __ARCH_MVEBU_COMMON_H + +void mvebu_restart(char mode, const char *cmd); + +#endif diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c new file mode 100644 index 000000000000..b8079df8c986 --- /dev/null +++ b/arch/arm/mach-mvebu/system-controller.c @@ -0,0 +1,105 @@ +/* + * System controller support for Armada 370 and XP platforms. + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * The Armada 370 and Armada XP SoCs both have a range of + * miscellaneous registers, that do not belong to a particular device, + * but rather provide system-level features. This basic + * system-controller driver provides a device tree binding for those + * registers, and implements utility functions offering various + * features related to those registers. + * + * For now, the feature set is limited to restarting the platform by a + * soft-reset, but it might be extended in the future. + */ + +#include +#include +#include +#include + +static void __iomem *system_controller_base; + +struct mvebu_system_controller { + u32 rstoutn_mask_offset; + u32 system_soft_reset_offset; + + u32 rstoutn_mask_reset_out_en; + u32 system_soft_reset; +}; +static struct mvebu_system_controller *mvebu_sc; + +const struct mvebu_system_controller armada_370_xp_system_controller = { + .rstoutn_mask_offset = 0x60, + .system_soft_reset_offset = 0x64, + .rstoutn_mask_reset_out_en = 0x1, + .system_soft_reset = 0x1, +}; + +const struct mvebu_system_controller orion_system_controller = { + .rstoutn_mask_offset = 0x108, + .system_soft_reset_offset = 0x10c, + .rstoutn_mask_reset_out_en = 0x4, + .system_soft_reset = 0x1, +}; + +static struct of_device_id of_system_controller_table[] = { + { + .compatible = "marvell,orion-system-controller", + .data = (void *) &orion_system_controller, + }, { + .compatible = "marvell,armada-370-xp-system-controller", + .data = (void *) &armada_370_xp_system_controller, + }, + { /* end of list */ }, +}; + +void mvebu_restart(char mode, const char *cmd) +{ + if (!system_controller_base) { + pr_err("Cannot restart, system-controller not available: check the device tree\n"); + } else { + /* + * Enable soft reset to assert RSTOUTn. + */ + writel(mvebu_sc->rstoutn_mask_reset_out_en, + system_controller_base + + mvebu_sc->rstoutn_mask_offset); + /* + * Assert soft reset. + */ + writel(mvebu_sc->system_soft_reset, + system_controller_base + + mvebu_sc->system_soft_reset_offset); + } + + while (1) + ; +} + +static int __init mvebu_system_controller_init(void) +{ + struct device_node *np; + + np = of_find_matching_node(NULL, of_system_controller_table); + if (np) { + const struct of_device_id *match = + of_match_node(of_system_controller_table, np); + BUG_ON(!match); + system_controller_base = of_iomap(np, 0); + mvebu_sc = (struct mvebu_system_controller *)match->data; + } + + return 0; +} + +arch_initcall(mvebu_system_controller_init); From 9ae6f740b49f933eeff972a79fd2a8b7e4592cf5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Wed, 13 Jun 2012 19:01:28 +0200 Subject: [PATCH 4/9] arm: mach-mvebu: add support for Armada 370 and Armada XP with DT [ben.dooks@codethink.co.uk: ensure error check on of_property_read_u32] [ben.dooks@codethink.co.uk: use mpic address instead of bus-unit's ] [ben.dooks@codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic] [ben.dooks@codethink.co.uk: move mpic per-cpu register base ] [ben.dooks@codethink.co.uk: number fetch should use irqd_to_hwirq()] Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem Signed-off-by: Ben Dooks Acked-by: Andrew Lunn Tested-by: Yehuda Yitschak Tested-by: Lior Amsalem --- arch/arm/boot/dts/armada-370-db.dts | 42 ++++++ arch/arm/boot/dts/armada-370-xp.dtsi | 68 +++++++++ arch/arm/boot/dts/armada-370.dtsi | 35 +++++ arch/arm/boot/dts/armada-xp-db.dts | 50 +++++++ arch/arm/boot/dts/armada-xp.dtsi | 55 ++++++++ arch/arm/mach-mvebu/Kconfig | 9 ++ arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/armada-370-xp.c | 63 +++++++++ arch/arm/mach-mvebu/common.h | 3 + .../mach-mvebu/include/mach/armada-370-xp.h | 22 +++ arch/arm/mach-mvebu/irq-armada-370-xp.c | 130 ++++++++++++++++++ 11 files changed, 478 insertions(+) create mode 100644 arch/arm/boot/dts/armada-370-db.dts create mode 100644 arch/arm/boot/dts/armada-370-xp.dtsi create mode 100644 arch/arm/boot/dts/armada-370.dtsi create mode 100644 arch/arm/boot/dts/armada-xp-db.dts create mode 100644 arch/arm/boot/dts/armada-xp.dtsi create mode 100644 arch/arm/mach-mvebu/armada-370-xp.c create mode 100644 arch/arm/mach-mvebu/include/mach/armada-370-xp.h create mode 100644 arch/arm/mach-mvebu/irq-armada-370-xp.c diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts new file mode 100644 index 000000000000..fffd5c2a3041 --- /dev/null +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -0,0 +1,42 @@ +/* + * Device Tree file for Marvell Armada 370 evaluation board + * (DB-88F6710-BP-DDR3) + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "armada-370.dtsi" + +/ { + model = "Marvell Armada 370 Evaluation Board"; + compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + serial@d0012000 { + clock-frequency = <200000000>; + status = "okay"; + }; + timer@d0020300 { + clock-frequency = <600000000>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi new file mode 100644 index 000000000000..6b6b932a5a7d --- /dev/null +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -0,0 +1,68 @@ +/* + * Device Tree Include file for Marvell Armada 370 and Armada XP SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * Ben Dooks + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions that are common to the Armada + * 370 and Armada XP SoC. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Marvell Armada 370 and XP SoC"; + compatible = "marvell,armada_370_xp"; + + cpus { + cpu@0 { + compatible = "marvell,sheeva-v7"; + }; + }; + + mpic: interrupt-controller@d0020000 { + compatible = "marvell,mpic"; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&mpic>; + ranges; + + serial@d0012000 { + compatible = "ns16550"; + reg = <0xd0012000 0x100>; + reg-shift = <2>; + interrupts = <41>; + status = "disabled"; + }; + serial@d0012100 { + compatible = "ns16550"; + reg = <0xd0012100 0x100>; + reg-shift = <2>; + interrupts = <42>; + status = "disabled"; + }; + + timer@d0020300 { + compatible = "marvell,armada-370-xp-timer"; + reg = <0xd0020300 0x30>; + interrupts = <37>, <38>, <39>, <40>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi new file mode 100644 index 000000000000..3228ccc83332 --- /dev/null +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -0,0 +1,35 @@ +/* + * Device Tree Include file for Marvell Armada 370 family SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada 370 SoC that are not + * common to all Armada SoCs. + */ + +/include/ "armada-370-xp.dtsi" + +/ { + model = "Marvell Armada 370 family SoC"; + compatible = "marvell,armada370", "marvell,armada-370-xp"; + + mpic: interrupt-controller@d0020000 { + reg = <0xd0020a00 0x1d0>, + <0xd0021870 0x58>; + }; + + soc { + system-controller@d0018200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0xd0018200 0x100>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts new file mode 100644 index 000000000000..f97040d4258d --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -0,0 +1,50 @@ +/* + * Device Tree file for Marvell Armada XP evaluation board + * (DB-78460-BP) + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; +/include/ "armada-xp.dtsi" + +/ { + model = "Marvell Armada XP Evaluation Board"; + compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + serial@d0012000 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@d0012100 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@d0012200 { + clock-frequency = <250000000>; + status = "okay"; + }; + serial@d0012300 { + clock-frequency = <250000000>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi new file mode 100644 index 000000000000..e1fa7e6edfe8 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -0,0 +1,55 @@ +/* + * Device Tree Include file for Marvell Armada XP family SoC + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * Ben Dooks + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * Contains definitions specific to the Armada 370 SoC that are not + * common to all Armada SoCs. + */ + +/include/ "armada-370-xp.dtsi" + +/ { + model = "Marvell Armada XP family SoC"; + compatible = "marvell,armadaxp", "marvell,armada-370-xp"; + + mpic: interrupt-controller@d0020000 { + reg = <0xd0020a00 0x1d0>, + <0xd0021870 0x58>; + }; + + soc { + serial@d0012200 { + compatible = "ns16550"; + reg = <0xd0012200 0x100>; + reg-shift = <2>; + interrupts = <43>; + status = "disabled"; + }; + serial@d0012300 { + compatible = "ns16550"; + reg = <0xd0012300 0x100>; + reg-shift = <2>; + interrupts = <44>; + status = "disabled"; + }; + + timer@d0020300 { + marvell,timer-25Mhz; + }; + + system-controller@d0018200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0xd0018200 0x500>; + }; + }; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 72d39e5c0ff4..caa2c5e734fe 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -2,6 +2,15 @@ if ARCH_MVEBU menu "Marvell SOC with device tree" +config MACH_ARMADA_370_XP + bool "Marvell Armada 370 and Aramada XP boards" + select ARMADA_370_XP_TIMER + select CPU_V7 + help + + Say 'Y' here if you want your kernel to support boards based on + Marvell Armada 370 or Armada XP with device tree. + endmenu endif diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 7366ae7357f3..e61d2b8fdf50 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -1 +1,2 @@ obj-y += system-controller.o +obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c new file mode 100644 index 000000000000..4ef923b032ec --- /dev/null +++ b/arch/arm/mach-mvebu/armada-370-xp.c @@ -0,0 +1,63 @@ +/* + * Device Tree support for Armada 370 and XP platforms. + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +static struct map_desc armada_370_xp_io_desc[] __initdata = { + { + .virtual = ARMADA_370_XP_REGS_VIRT_BASE, + .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE), + .length = ARMADA_370_XP_REGS_SIZE, + .type = MT_DEVICE, + }, +}; + +void __init armada_370_xp_map_io(void) +{ + iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc)); +} + +struct sys_timer armada_370_xp_timer = { + .init = armada_370_xp_timer_init, +}; + +static void __init armada_370_xp_dt_init(void) +{ + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); +} + +static const char * const armada_370_xp_dt_board_dt_compat[] = { + "marvell,a370-db", + "marvell,axp-db", + NULL, +}; + +DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)") + .init_machine = armada_370_xp_dt_init, + .map_io = armada_370_xp_map_io, + .init_irq = armada_370_xp_init_irq, + .handle_irq = armada_370_xp_handle_irq, + .timer = &armada_370_xp_timer, + .restart = mvebu_restart, + .dt_compat = armada_370_xp_dt_board_dt_compat, +MACHINE_END diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index f0eaa215e629..02f89eaa25fe 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -17,4 +17,7 @@ void mvebu_restart(char mode, const char *cmd); +void armada_370_xp_init_irq(void); +void armada_370_xp_handle_irq(struct pt_regs *regs); + #endif diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h new file mode 100644 index 000000000000..25f0ca8d7820 --- /dev/null +++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h @@ -0,0 +1,22 @@ +/* + * Generic definitions for Marvell Armada_370_XP SoCs + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __MACH_ARMADA_370_XP_H +#define __MACH_ARMADA_370_XP_H + +#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 +#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 +#define ARMADA_370_XP_REGS_SIZE SZ_1M + +#endif /* __MACH_ARMADA_370_XP_H */ diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c new file mode 100644 index 000000000000..645a8d3698eb --- /dev/null +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -0,0 +1,130 @@ +/* + * Marvell Armada 370 and Armada XP SoC IRQ handling + * + * Copyright (C) 2012 Marvell + * + * Lior Amsalem + * Gregory CLEMENT + * Thomas Petazzoni + * Ben Dooks + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Interrupt Controller Registers Map */ +#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) +#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) + +#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) +#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) + +#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) + +#define ARMADA_370_XP_NR_IRQS (115) + +static void __iomem *per_cpu_int_base; +static void __iomem *main_int_base; +static struct irq_domain *armada_370_xp_mpic_domain; + +static void armada_370_xp_irq_mask(struct irq_data *d) +{ + writel(irqd_to_hwirq(d), + per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); +} + +static void armada_370_xp_irq_unmask(struct irq_data *d) +{ + writel(irqd_to_hwirq(d), + per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); +} + +static struct irq_chip armada_370_xp_irq_chip = { + .name = "armada_370_xp_irq", + .irq_mask = armada_370_xp_irq_mask, + .irq_mask_ack = armada_370_xp_irq_mask, + .irq_unmask = armada_370_xp_irq_unmask, +}; + +static int armada_370_xp_mpic_irq_map(struct irq_domain *h, + unsigned int virq, irq_hw_number_t hw) +{ + armada_370_xp_irq_mask(irq_get_irq_data(virq)); + writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); + + irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip, + handle_level_irq); + irq_set_status_flags(virq, IRQ_LEVEL); + set_irq_flags(virq, IRQF_VALID | IRQF_PROBE); + + return 0; +} + +static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { + .map = armada_370_xp_mpic_irq_map, + .xlate = irq_domain_xlate_onecell, +}; + +static int __init armada_370_xp_mpic_of_init(struct device_node *node, + struct device_node *parent) +{ + main_int_base = of_iomap(node, 0); + per_cpu_int_base = of_iomap(node, 1); + + BUG_ON(!main_int_base); + BUG_ON(!per_cpu_int_base); + + armada_370_xp_mpic_domain = + irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS, + &armada_370_xp_mpic_irq_ops, NULL); + + if (!armada_370_xp_mpic_domain) + panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n"); + + irq_set_default_host(armada_370_xp_mpic_domain); + return 0; +} + +asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs + *regs) +{ + u32 irqstat, irqnr; + + do { + irqstat = readl_relaxed(per_cpu_int_base + + ARMADA_370_XP_CPU_INTACK_OFFS); + irqnr = irqstat & 0x3FF; + + if (irqnr < 1023) { + irqnr = + irq_find_mapping(armada_370_xp_mpic_domain, irqnr); + handle_IRQ(irqnr, regs); + continue; + } + + break; + } while (1); +} + +static const struct of_device_id mpic_of_match[] __initconst = { + {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init}, + {}, +}; + +void __init armada_370_xp_init_irq(void) +{ + of_irq_init(mpic_of_match); +} From 0d01b7a153561eee6f878238caf76c53bb1dc0d5 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Fri, 1 Jun 2012 18:33:17 +0200 Subject: [PATCH 5/9] arm: mach-mvebu: add documentation for new device tree bindings Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem Tested-by: Yehuda Yitschak Tested-by: Lior Amsalem Acked-by: Andrew Lunn --- .../bindings/arm/armada-370-xp-mpic.txt | 23 ++++++++++++++++++ .../bindings/arm/armada-370-xp-timer.txt | 11 +++++++++ .../devicetree/bindings/arm/armada-370-xp.txt | 24 +++++++++++++++++++ .../bindings/arm/mvebu-system-controller.txt | 17 +++++++++++++ 4 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt create mode 100644 Documentation/devicetree/bindings/arm/armada-370-xp.txt create mode 100644 Documentation/devicetree/bindings/arm/mvebu-system-controller.txt diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt new file mode 100644 index 000000000000..70c0dc5f00ed --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-370-xp-mpic.txt @@ -0,0 +1,23 @@ +Marvell Armada 370 and Armada XP Interrupt Controller +----------------------------------------------------- + +Required properties: +- compatible: Should be "marvell,mpic" +- interrupt-controller: Identifies the node as an interrupt controller. +- #interrupt-cells: The number of cells to define the interrupts. Should be 1. + The cell is the IRQ number +- reg: Should contain PMIC registers location and length. First pair + for the main interrupt registers, second pair for the per-CPU + interrupt registers + +Example: + + mpic: interrupt-controller@d0020000 { + compatible = "marvell,mpic"; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0xd0020000 0x1000>, + <0xd0021000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt new file mode 100644 index 000000000000..8b6ea2267c94 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-370-xp-timer.txt @@ -0,0 +1,11 @@ +Marvell Armada 370 and Armada XP Global Timers +---------------------------------------------- + +Required properties: +- compatible: Should be "marvell,armada-370-xp-timer" +- interrupts: Should contain the list of Global Timer interrupts +- reg: Should contain the base address of the Global Timer registers + +Optional properties: +- marvell,timer-25Mhz: Tells whether the Global timer supports the 25 + Mhz fixed mode (available on Armada XP and not on Armada 370) diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/armada-370-xp.txt new file mode 100644 index 000000000000..c6ed90ea6e17 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-370-xp.txt @@ -0,0 +1,24 @@ +Marvell Armada 370 and Armada XP Platforms Device Tree Bindings +--------------------------------------------------------------- + +Boards with a SoC of the Marvell Armada 370 and Armada XP families +shall have the following property: + +Required root node property: + +compatible: must contain "marvell,armada-370-xp" + +In addition, boards using the Marvell Armada 370 SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armada370" + +In addition, boards using the Marvell Armada XP SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armadaxp" + diff --git a/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt new file mode 100644 index 000000000000..081c6a786c8a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mvebu-system-controller.txt @@ -0,0 +1,17 @@ +MVEBU System Controller +----------------------- +MVEBU (Marvell SOCs: Armada 370/XP, Dove, mv78xx0, Kirkwood, Orion5x) + +Required properties: + +- compatible: one of: + - "marvell,orion-system-controller" + - "marvell,armada-370-xp-system-controller" +- reg: Should contain system controller registers location and length. + +Example: + + system-controller@d0018200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0xd0018200 0x500>; + }; From 3e9c95017c2abaa36291866ac5f8fcf6840e76de Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 1 Jun 2012 18:48:35 +0200 Subject: [PATCH 6/9] arm: mach-mvebu: add defconfig Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem Acked-by: Andrew Lunn Tested-by: Yehuda Yitschak Tested-by: Lior Amsalem --- arch/arm/configs/mvebu_defconfig | 46 ++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 arch/arm/configs/mvebu_defconfig diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig new file mode 100644 index 000000000000..2e86b31c33cf --- /dev/null +++ b/arch/arm/configs/mvebu_defconfig @@ -0,0 +1,46 @@ +CONFIG_EXPERIMENTAL=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_ARCH_MVEBU=y +CONFIG_MACH_ARMADA_370_XP=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_USE_OF=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_VFP=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_EARLY_PRINTK=y From 3e93a22b486ba75191f8d054dd757a67244d337c Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Mon, 4 Jun 2012 18:38:56 +0200 Subject: [PATCH 7/9] arm: mach-mvebu: add compilation/configuration change Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem Acked-by: Andrew Lunn Tested-by: Yehuda Yitschak Tested-by: Lior Amsalem --- arch/arm/Kconfig | 14 ++++++++++++++ arch/arm/Makefile | 1 + 2 files changed, 15 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a91009c61870..e7fbe53cbbf5 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -533,6 +533,18 @@ config ARCH_IXP4XX help Support for Intel's IXP4XX (XScale) family of processors. +config ARCH_MVEBU + bool "Marvell SOCs with Device Tree support" + select GENERIC_CLOCKEVENTS + select MULTI_IRQ_HANDLER + select SPARSE_IRQ + select CLKSRC_MMIO + select GENERIC_IRQ_CHIP + select IRQ_DOMAIN + select COMMON_CLK + help + Support for the Marvell SoC Family with device tree support + config ARCH_DOVE bool "Marvell Dove" select CPU_V7 @@ -987,6 +999,8 @@ endchoice # Kconfigs may be included either alphabetically (according to the # plat- suffix) or along side the corresponding mach-* source. # +source "arch/arm/mach-mvebu/Kconfig" + source "arch/arm/mach-at91/Kconfig" source "arch/arm/mach-bcmring/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 0298b00fe241..f1a1a7170103 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -157,6 +157,7 @@ machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 machine-$(CONFIG_ARCH_IMX_V4_V5) := imx machine-$(CONFIG_ARCH_IMX_V6_V7) := imx machine-$(CONFIG_ARCH_MXS) := mxs +machine-$(CONFIG_ARCH_MVEBU) := mvebu machine-$(CONFIG_ARCH_NETX) := netx machine-$(CONFIG_ARCH_NOMADIK) := nomadik machine-$(CONFIG_ARCH_OMAP1) := omap1 From 75f41273ec558d4ffc22c2dbf7637d42f167cf25 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Fri, 1 Jun 2012 18:50:52 +0200 Subject: [PATCH 8/9] arm: mach-mvebu: add entry to MAINTAINERS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The new mach-mvebu directory will be maintained by Andrew Lunn and Jason Cooper (as the existing maintainers for previous Marvell EBU SoCs) together with Grégory Clément for the Armada 370/XP SoCs. Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index eb22272b2116..b8a65fbf0473 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -894,6 +894,14 @@ ARM/MAGICIAN MACHINE SUPPORT M: Philipp Zabel S: Maintained +ARM/Marvell Armada 370 and Armada XP SOC support +M: Jason Cooper +M: Andrew Lunn +M: Gregory Clement +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm/mach-mvebu/ + ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support M: Jason Cooper M: Andrew Lunn From f3e16ccd03fab2f8440609bd44feb882b5fdd31d Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Mon, 4 Jun 2012 18:50:12 +0200 Subject: [PATCH 9/9] ARM: mvebu: MPIC: read number of interrupts from control register Read the number of MPIC interrupts from the controller and only register that many. [gregory.clement@free-electrons.com: rename armada symbol name to fit with new name: armada_370_xp] Signed-off-by: Ben Dooks Signed-off-by: Gregory CLEMENT Signed-off-by: Thomas Petazzoni Signed-off-by: Lior Amsalem --- arch/arm/mach-mvebu/irq-armada-370-xp.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c index 645a8d3698eb..5f5f9394b6b2 100644 --- a/arch/arm/mach-mvebu/irq-armada-370-xp.c +++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c @@ -29,13 +29,12 @@ #define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48) #define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C) +#define ARMADA_370_XP_INT_CONTROL (0x00) #define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30) #define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34) #define ARMADA_370_XP_CPU_INTACK_OFFS (0x44) -#define ARMADA_370_XP_NR_IRQS (115) - static void __iomem *per_cpu_int_base; static void __iomem *main_int_base; static struct irq_domain *armada_370_xp_mpic_domain; @@ -81,14 +80,18 @@ static struct irq_domain_ops armada_370_xp_mpic_irq_ops = { static int __init armada_370_xp_mpic_of_init(struct device_node *node, struct device_node *parent) { + u32 control; + main_int_base = of_iomap(node, 0); per_cpu_int_base = of_iomap(node, 1); BUG_ON(!main_int_base); BUG_ON(!per_cpu_int_base); + control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL); + armada_370_xp_mpic_domain = - irq_domain_add_linear(node, ARMADA_370_XP_NR_IRQS, + irq_domain_add_linear(node, (control >> 2) & 0x3ff, &armada_370_xp_mpic_irq_ops, NULL); if (!armada_370_xp_mpic_domain)