From 81d1a358501e80607d58352ed41a4b3c5e88c10b Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 3 Nov 2009 18:09:46 +0100 Subject: [PATCH] --- yaml --- r: 172457 b: refs/heads/master c: 8963c49fdba293fbc21aee1bbae9afa99a52755f h: refs/heads/master i: 172455: 1db50174bcfb3c68e5fd2140defd9fa8eb3e0e67 v: v3 --- [refs] | 2 +- trunk/arch/arm/plat-mxc/include/mach/iomux-mx3.h | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 03f151fd7ebc..60954aaf055c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 2097abcb8c5a1ccd8c126f6680df28ff6b6b96d0 +refs/heads/master: 8963c49fdba293fbc21aee1bbae9afa99a52755f diff --git a/trunk/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/trunk/arch/arm/plat-mxc/include/mach/iomux-mx3.h index 446f86763816..0dcfb7779174 100644 --- a/trunk/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/trunk/arch/arm/plat-mxc/include/mach/iomux-mx3.h @@ -623,6 +623,8 @@ enum iomux_pins { #define MX31_PIN_GPIO3_0__GPIO3_0 IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO) #define MX31_PIN_GPIO3_1__GPIO3_1 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO) #define MX31_PIN_TXD2__GPIO1_28 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D4__GPIO3_4 IOMUX_MODE(MX31_PIN_CSI_D4, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSI_D5__GPIO3_5 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO) #define MX31_PIN_USBOTG_DATA0__USBOTG_DATA0 IOMUX_MODE(MX31_PIN_USBOTG_DATA0, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_DATA1__USBOTG_DATA1 IOMUX_MODE(MX31_PIN_USBOTG_DATA1, IOMUX_CONFIG_FUNC) #define MX31_PIN_USBOTG_DATA2__USBOTG_DATA2 IOMUX_MODE(MX31_PIN_USBOTG_DATA2, IOMUX_CONFIG_FUNC) @@ -693,7 +695,11 @@ enum iomux_pins { #define MX31_PIN_DCD_DCE1__GPIO2_11 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO) #define MX31_PIN_STXD5__GPIO1_21 IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO) #define MX31_PIN_SRXD5__GPIO1_22 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO) - +#define MX31_PIN_GPIO1_3__GPIO1_3 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CSPI2_SS1__CSPI3_SS1 IOMUX_MODE(MX31_PIN_CSPI2_SS1, IOMUX_CONFIG_ALT1) +#define MX31_PIN_RTS1__GPIO2_6 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_CTS1__GPIO2_7 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO) +#define MX31_PIN_LCS0__GPIO3_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 * cspi1_ss1*/