From 820d5f0928a8f41da12c4aa2fd13ed67ebba0cbd Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 14 Dec 2010 11:34:51 +0000 Subject: [PATCH] --- yaml --- r: 228805 b: refs/heads/master c: 9097eef024db4f1850015e837a84aca0aa40a288 h: refs/heads/master i: 228803: 8ca71f934a42af240f81a004ed740db4e2eefd6e v: v3 --- [refs] | 2 +- trunk/drivers/char/agp/intel-gtt.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 61cd3111e1ac..dda077be1af4 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b13c2b96bf15b9dd0f1a45fd788f3a3025c5aec6 +refs/heads/master: 9097eef024db4f1850015e837a84aca0aa40a288 diff --git a/trunk/drivers/char/agp/intel-gtt.c b/trunk/drivers/char/agp/intel-gtt.c index 326ca2ef06b5..356f73e0d17e 100644 --- a/trunk/drivers/char/agp/intel-gtt.c +++ b/trunk/drivers/char/agp/intel-gtt.c @@ -1135,12 +1135,19 @@ static void i9xx_chipset_flush(void) writel(1, intel_private.i9xx_flush_page); } -static void i965_write_entry(dma_addr_t addr, unsigned int entry, +static void i965_write_entry(dma_addr_t addr, + unsigned int entry, unsigned int flags) { + u32 pte_flags; + + pte_flags = I810_PTE_VALID; + if (flags == AGP_USER_CACHED_MEMORY) + pte_flags |= I830_PTE_SYSTEM_CACHED; + /* Shift high bits down */ addr |= (addr >> 28) & 0xf0; - writel(addr | I810_PTE_VALID, intel_private.gtt + entry); + writel(addr | pte_flags, intel_private.gtt + entry); } static bool gen6_check_flags(unsigned int flags)