From 831132d373f6af0f2acea9104e244304d3d599dd Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 5 Dec 2012 13:51:19 -0700 Subject: [PATCH] --- yaml --- r: 343285 b: refs/heads/master c: f2692bd9be3415ccfcb3a2d33b12ab6621c53067 h: refs/heads/master i: 343283: 20b62bf7ed7bd3df7db5938b675b7ea4174287e2 v: v3 --- [refs] | 2 +- trunk/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index bd6582a17438..34d12b490bb4 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7508320678b7819ac6aeb89580b8622a424ce586 +refs/heads/master: f2692bd9be3415ccfcb3a2d33b12ab6621c53067 diff --git a/trunk/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/trunk/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c index aef45d3113ba..3dee68612c9e 100644 --- a/trunk/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c +++ b/trunk/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c @@ -3307,7 +3307,7 @@ static void config_pcie(struct adapter *adap) G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE)); log2_width = fls(adap->params.pci.width) - 1; acklat = ack_lat[log2_width][pldsize]; - if (val & 1) /* check LOsEnable */ + if (val & PCI_EXP_LNKCTL_ASPM_L0S) /* check LOsEnable */ acklat += fst_trn_tx * 4; rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;