From 831f0f831771f284961496e4d7c71c0fdd8969e3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 14 Dec 2012 00:23:06 -0500 Subject: [PATCH] --- yaml --- r: 345601 b: refs/heads/master c: 9d89d78e3a20980205966fba6345645547e59ceb h: refs/heads/master i: 345599: aaac4fa127fbdcc862eac359156af6c7be553b4b v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/evergreen_cs.c | 24 +++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 73246f046aa1..1f669782af0d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 8696e33f06b0c52195152cc6a0e3d52233f486c1 +refs/heads/master: 9d89d78e3a20980205966fba6345645547e59ceb diff --git a/trunk/drivers/gpu/drm/radeon/evergreen_cs.c b/trunk/drivers/gpu/drm/radeon/evergreen_cs.c index 9a9d3ae6c188..74c6b42d2597 100644 --- a/trunk/drivers/gpu/drm/radeon/evergreen_cs.c +++ b/trunk/drivers/gpu/drm/radeon/evergreen_cs.c @@ -2256,6 +2256,18 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, command = radeon_get_ib_value(p, idx+4); size = command & 0x1fffff; info = radeon_get_ib_value(p, idx+1); + if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */ + (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */ + ((((info & 0x00300000) >> 20) == 0) && + (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */ + ((((info & 0x60000000) >> 29) == 0) && + (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */ + /* non mem to mem copies requires dw aligned count */ + if (size % 4) { + DRM_ERROR("CP DMA command requires dw count alignment\n"); + return -EINVAL; + } + } if (command & PACKET3_CP_DMA_CMD_SAS) { /* src address space is register */ /* GDS is ok */ @@ -3472,6 +3484,18 @@ static int evergreen_vm_packet3_check(struct radeon_device *rdev, case PACKET3_CP_DMA: command = ib[idx + 4]; info = ib[idx + 1]; + if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */ + (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */ + ((((info & 0x00300000) >> 20) == 0) && + (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */ + ((((info & 0x60000000) >> 29) == 0) && + (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */ + /* non mem to mem copies requires dw aligned count */ + if ((command & 0x1fffff) % 4) { + DRM_ERROR("CP DMA command requires dw count alignment\n"); + return -EINVAL; + } + } if (command & PACKET3_CP_DMA_CMD_SAS) { /* src address space is register */ if (((info & 0x60000000) >> 29) == 0) {