From 838a54528c1faa3f017d56a0ba001af229af7b5e Mon Sep 17 00:00:00 2001 From: Eilon Greenstein Date: Mon, 2 Mar 2009 07:59:20 +0000 Subject: [PATCH] --- yaml --- r: 135012 b: refs/heads/master c: 0d1a8d2d7dd9f6588ed9544a9aa88fd9bd9467d3 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/net/bnx2x_reg.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index e2837980c4a4..b1ab6c6e0e6d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 98589bb1099732847c5deedc213c17c50dd1bc75 +refs/heads/master: 0d1a8d2d7dd9f6588ed9544a9aa88fd9bd9467d3 diff --git a/trunk/drivers/net/bnx2x_reg.h b/trunk/drivers/net/bnx2x_reg.h index 360a2564aa98..8de80cca13d3 100644 --- a/trunk/drivers/net/bnx2x_reg.h +++ b/trunk/drivers/net/bnx2x_reg.h @@ -5410,7 +5410,7 @@ #define PCICFG_COMMAND_INT_DISABLE (1<<10) #define PCICFG_COMMAND_RESERVED (0x1f<<11) #define PCICFG_STATUS_OFFSET 0x06 -#define PCICFG_REVESION_ID 0x08 +#define PCICFG_REVESION_ID_OFFSET 0x08 #define PCICFG_CACHE_LINE_SIZE 0x0c #define PCICFG_LATENCY_TIMER 0x0d #define PCICFG_BAR_1_LOW 0x10 @@ -5438,7 +5438,7 @@ #define PCICFG_PM_CSR_STATE (0x3<<0) #define PCICFG_PM_CSR_PME_ENABLE (1<<8) #define PCICFG_PM_CSR_PME_STATUS (1<<15) -#define PCICFG_MSI_CAP_ID 0x58 +#define PCICFG_MSI_CAP_ID_OFFSET 0x58 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) #define PCICFG_MSI_CONTROL_MENA (0x7<<20) @@ -5446,7 +5446,7 @@ #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) #define PCICFG_GRC_ADDRESS 0x78 #define PCICFG_GRC_DATA 0x80 -#define PCICFG_MSIX_CAP_ID 0xa0 +#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)