From 84afd249cb9758480edfb27c80936b83893c6101 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Fri, 22 Oct 2010 05:11:08 +0000 Subject: [PATCH] --- yaml --- r: 213733 b: refs/heads/master c: b9ac41e314f0b43641bc01bd553fd2e0458ed832 h: refs/heads/master i: 213731: eea1db3aa5b20c66d49a6afb113c35000d45962e v: v3 --- [refs] | 2 +- trunk/arch/blackfin/include/asm/bfin5xx_spi.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 4d86a4ddb3eb..df99eb755e09 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: fec84d21c52bca67949a17aaf7d410b497f8e1b0 +refs/heads/master: b9ac41e314f0b43641bc01bd553fd2e0458ed832 diff --git a/trunk/arch/blackfin/include/asm/bfin5xx_spi.h b/trunk/arch/blackfin/include/asm/bfin5xx_spi.h index 4223cf08ce83..0b5136e334b5 100644 --- a/trunk/arch/blackfin/include/asm/bfin5xx_spi.h +++ b/trunk/arch/blackfin/include/asm/bfin5xx_spi.h @@ -41,6 +41,25 @@ #define BIT_STU_SENDOVER 0x0001 #define BIT_STU_RECVFULL 0x0020 +/* + * All Blackfin system MMRs are padded to 32bits even if the register + * itself is only 16bits. So use a helper macro to streamline this. + */ +#define __BFP(m) u16 m; u16 __pad_##m + +/* + * bfin spi registers layout + */ +struct bfin_spi_regs { + __BFP(ctl); + __BFP(flg); + __BFP(stat); + __BFP(tdbr); + __BFP(rdbr); + __BFP(baud); + __BFP(shadow); +}; + #define MAX_CTRL_CS 8 /* cs in spi controller */ /* device.platform_data for SSP controller devices */