From 84fab1b1fb99e72320a92e65fc66a7aaeaa84d2a Mon Sep 17 00:00:00 2001
From: Pratyush Anand <pratyush.anand@st.com>
Date: Thu, 21 Jun 2012 17:44:28 +0530
Subject: [PATCH] --- yaml --- r: 316957 b: refs/heads/master c:
 45627ac6a4f063d19b0bd9863d20ac1dabda99a7 h: refs/heads/master i:   316955:
 705d387822b2a332e38ad183c88f2873f6e3d39a v: v3

---
 [refs]                        | 2 +-
 trunk/drivers/usb/dwc3/core.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index d9d65b1856b9..8529c2885f82 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 45c396ce6bdad60ee94e6eed8cc7f09678651102
+refs/heads/master: 45627ac6a4f063d19b0bd9863d20ac1dabda99a7
diff --git a/trunk/drivers/usb/dwc3/core.c b/trunk/drivers/usb/dwc3/core.c
index 49c060205c9a..ac151e9acf20 100644
--- a/trunk/drivers/usb/dwc3/core.c
+++ b/trunk/drivers/usb/dwc3/core.c
@@ -148,6 +148,8 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc)
 	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
+	mdelay(100);
+
 	/* After PHYs are stable we can take Core out of reset state */
 	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 	reg &= ~DWC3_GCTL_CORESOFTRESET;