From 851bbf04c46312ff287e474670018d4d01cba6b6 Mon Sep 17 00:00:00 2001
From: Matt Carlson <mcarlson@broadcom.com>
Date: Mon, 20 Apr 2009 06:57:41 +0000
Subject: [PATCH] --- yaml --- r: 149798 b: refs/heads/master c:
 33466d938f43ab65312466ba5472b9c6ee200cce h: refs/heads/master v: v3

---
 [refs]                  | 2 +-
 trunk/drivers/net/tg3.c | 7 +++++++
 trunk/drivers/net/tg3.h | 2 ++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 086a45f9cb20..4327906cbc4c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: df259d8cba7d7880dc04d34c7a6e0ce15fbc9644
+refs/heads/master: 33466d938f43ab65312466ba5472b9c6ee200cce
diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c
index 9b04954b6943..ed7a86df98cd 100644
--- a/trunk/drivers/net/tg3.c
+++ b/trunk/drivers/net/tg3.c
@@ -6717,6 +6717,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 		tw32(TG3_CPMU_HST_ACC, val);
 	}
 
+	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
+		val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
+		val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
+		       PCIE_PWR_MGMT_L1_THRESH_4MS;
+		tw32(PCIE_PWR_MGMT_THRESH, val);
+	}
+
 	/* This works around an issue with Athlon chipsets on
 	 * B3 tigon3 silicon.  This bit has no effect on any
 	 * other revision.  But do not set this on PCI Express
diff --git a/trunk/drivers/net/tg3.h b/trunk/drivers/net/tg3.h
index afbabf283c51..f1016cb1a89a 100644
--- a/trunk/drivers/net/tg3.h
+++ b/trunk/drivers/net/tg3.h
@@ -1697,6 +1697,8 @@
 
 #define PCIE_PWR_MGMT_THRESH		0x00007d28
 #define PCIE_PWR_MGMT_L1_THRESH_MSK	 0x0000ff00
+#define PCIE_PWR_MGMT_L1_THRESH_4MS	 0x0000ff00
+#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN	 0x01000000
 
 
 /* OTP bit definitions */