From 8529b48fbba819a7f788a9a30d904bc450d676e6 Mon Sep 17 00:00:00 2001
From: Philipp Zabel <philipp.zabel@gmail.com>
Date: Thu, 10 Jul 2008 02:16:27 +0200
Subject: [PATCH] --- yaml --- r: 104073 b: refs/heads/master c:
 279cac484e55317456900fe3567c7cb5bd46fd5f h: refs/heads/master i:   104071:
 f9bf73a62b77aad9366fa72cc34b7286a6bb6ac2 v: v3

---
 [refs]                          |  2 +-
 trunk/include/linux/mfd/asic3.h | 38 +++------------------------------
 2 files changed, 4 insertions(+), 36 deletions(-)

diff --git a/[refs] b/[refs]
index a12317ffb0e4..e279aa455c1e 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4a67b528e0be5d855b1a7bb71ec769d954765f6c
+refs/heads/master: 279cac484e55317456900fe3567c7cb5bd46fd5f
diff --git a/trunk/include/linux/mfd/asic3.h b/trunk/include/linux/mfd/asic3.h
index 0eae3083da43..8f8c46c41f44 100644
--- a/trunk/include/linux/mfd/asic3.h
+++ b/trunk/include/linux/mfd/asic3.h
@@ -265,44 +265,12 @@ struct asic3_platform_data {
 #define ASIC3_EXTCF_CF_SLEEP             (1 << 15) /* CF sleep mode control */
 
 /*********************************************
- *  The Onewire interface registers
- *
- *  OWM_CMD
- *  OWM_DAT
- *  OWM_INTR
- *  OWM_INTEN
- *  OWM_CLKDIV
+ *  The Onewire interface (DS1WM) is handled
+ *  by the ds1wm driver.
  *
  *********************************************/
 
-#define ASIC3_OWM_Base		0xC00
-
-#define ASIC3_OWM_CMD         0x00
-#define ASIC3_OWM_DAT         0x04
-#define ASIC3_OWM_INTR        0x08
-#define ASIC3_OWM_INTEN       0x0C
-#define ASIC3_OWM_CLKDIV      0x10
-
-#define ASIC3_OWM_CMD_ONEWR         (1 << 0)
-#define ASIC3_OWM_CMD_SRA           (1 << 1)
-#define ASIC3_OWM_CMD_DQO           (1 << 2)
-#define ASIC3_OWM_CMD_DQI           (1 << 3)
-
-#define ASIC3_OWM_INTR_PD          (1 << 0)
-#define ASIC3_OWM_INTR_PDR         (1 << 1)
-#define ASIC3_OWM_INTR_TBE         (1 << 2)
-#define ASIC3_OWM_INTR_TEMP        (1 << 3)
-#define ASIC3_OWM_INTR_RBF         (1 << 4)
-
-#define ASIC3_OWM_INTEN_EPD        (1 << 0)
-#define ASIC3_OWM_INTEN_IAS        (1 << 1)
-#define ASIC3_OWM_INTEN_ETBE       (1 << 2)
-#define ASIC3_OWM_INTEN_ETMT       (1 << 3)
-#define ASIC3_OWM_INTEN_ERBF       (1 << 4)
-
-#define ASIC3_OWM_CLKDIV_PRE       (3 << 0) /* two bits wide at bit 0 */
-#define ASIC3_OWM_CLKDIV_DIV       (7 << 2) /* 3 bits wide at bit 2 */
-
+#define ASIC3_OWM_BASE		0xC00
 
 /*****************************************************************************
  *  The SD configuration registers are at a completely different location